Delay line calibration circuit comprising asynchronous arbiter element

Abstract

A delay line calibration circuit is disclosed herein. The calibration circuit has an arbiter circuit having a unit for determining which of two signals that arrive first; a first and a second synchronous element each having an input for receiving a clock signal, and one of them having a unit for outputting the clock signal a clock period later; and a calibration circuit having inputs connected to the outputs of the arbiter circuit for receiving a signal from it indicative of whether the signal input to the arbiter circuit from the delay line is ahead or after the signal input to the arbiter circuit from the second element, the calibration circuit further being connected to the delay line for calibrating the delay line in accordance with the signal received from the arbiter circuit. The invention in at least one embodiment provides improved calibration of delay lines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present invention will be explained in detail in the following with reference to the accompanying drawings, in which:

FIG. 1 illustrates a prior art pulse-width modulator using tapped delay line.

FIGS. 2 a and 2b illustrate two mutual exclusion elements.

FIG. 3 illustrates a block diagram of an embodiment of the present invention.

FIG. 4 illustrates a modulator in which the present invention can be used.

Claims

1. A delay line calibration circuit for controlling the delay of a delay line, the delay line calibration circuit comprising: an arbiter circuit comprising at least two inputs for receiving two signals, a unit configured to determine which of said two signals arrive first, and outputs, wherein a first of said at least two inputs is connected to said delay line;a first and a second element configured to provide synchronized clock signals, the first and second element each comprising an input for receiving a clock signal, wherein the first element comprises an output connected to the delay line and the second element comprises an output connected to a second of said at least two inputs of said arbiter circuit, anda calibration circuit comprising inputs connected to the outputs of said arbiter circuit and configured to receive a signal from said arbiter circuit indicative of whether the signal input to the arbiter circuit from the delay line is ahead or after the signal input to the arbiter circuit from the second element, said calibration circuit connected to said delay line and configured to calibrate the delay line in accordance with the signal received from the arbiter circuit.

2. The circuit of claim 1 wherein the second element is configured to output the signal applied to the delay line a clock period later.

3. The circuit of claim 1 wherein said arbiter circuit comprises a NAND arbiter for handling a rising edge of a clock signal.

4. The circuit of claim 1 wherein the arbiter circuit comprises a NOR arbiter for handling a falling edge of a clock signal.

5. The circuit of claim 1 wherein the calibration circuit is connected to delay elements of said delay line.

6. The circuit of claim 1 wherein said calibration circuit comprises a storage unit for storing delay calibration parameter values.

7. The circuit of claim 6 wherein said calibration circuit further comprises a unit for executing an updating algorithm for updating said calibration parameter values.

8. A modulator device comprising: a pulse-width modulator;a delay line calibration circuit configured to control the delay of a delay line comprising delay elements such that the delay of the delay line in its perfectly calibrated state is equal to one clock period of an input clock signal, wherein said delay line calibration circuit comprises an arbiter circuit comprising at least two inputs for receiving two signals, a unit configured to determine which of said signals arrive first, and outputs, wherein a first of said two inputs is connected to said delay line;a first and a second element configured to provide synchronized clock signals, the first and second elements each comprising an input for receiving a clock signal, wherein the first element comprises an output connected to the delay line, and wherein the second element comprises an output connected to a second of said two inputs of said arbiter circuit and is configured to output the signal applied to the delay line a clock period later; anda calibration circuit comprising inputs connected to the outputs of said arbiter circuit, the calibration circuit configured to receive a signal from said arbiter circuit indicative of whether the signal input to the arbiter circuit from the delay line is ahead or after the signal input to the arbiter circuit from the second element, said calibration circuit connected to said delay line and configured to calibrate the delay line in accordance with the signal received from the arbiter circuit.

9. The modulator device of claim 8 wherein the pulse-width modulator is connected to said first and second elements of said delay line calibration circuit.

10. The modulator device of claim 8 wherein said arbiter circuit comprises a NAND arbiter for handling a rising edge of a clock signal.

11. The modulator device of claim 8 wherein the arbiter circuit comprises a NOR arbiter for handling a falling edge of a clock signal.

12. The modulator device of claim 8 wherein the calibration circuit is connected to delay elements of said delay line.

13. The modulator device of claim 8 wherein said calibration circuit comprises a storage unit for storing delay calibration parameter values.

14. The modulator device of claim 13 wherein said calibration circuit further comprises a unit for executing an updating algorithm for updating said calibration parameter values.

15. A delay line calibration circuit configured to control the delay of a delay line comprising delay elements such that the delay of the delay line in its perfectly calibrated state is equal to one clock period of an input clock signal, wherein said delay line calibration circuit comprises: an arbiter circuit comprising at least two inputs configured to receive two signals, means for determining which of said signals arrive first, and outputs, wherein a first of said two inputs is connected to said delay line;a first means and a second means for providing synchronized clock signals each comprising an input for receiving a clock signal, wherein the first means for providing synchronized clock signals includes an output connected to the delay line and wherein the second means for providing synchronized clock signals comprises an output connected to a second of said two inputs of said arbiter circuit, anda calibration circuit comprising inputs connected to the outputs of said arbiter circuit and configured to receive a signal from said arbiter circuit indicative of whether the signal input to the arbiter circuit from the delay line is ahead or after the signal input to the arbiter circuit from the second element, said calibration circuit connected to said delay line and configured to calibrate the delay line in accordance with the signal received from the arbiter circuit.

16. The circuit of claim 15 wherein said arbiter circuit comprises a NAND arbiter for handling a rising edge of a clock signal.

17. The circuit of claim 15 wherein the arbiter circuit comprises a NOR arbiter for handling a falling edge of a clock signal.

18. The circuit of claim 15 wherein the calibration circuit is connected to delay elements of said delay line.

19. The circuit of claim 15 wherein said calibration circuit comprises a storage unit for storing delay calibration parameter values.