Patent Application
20100262671
The present invention relates generally to testing of devices used in network-based communication systems, and more particularly to testing of mappers or other devices that are to be arranged in a master-slave configuration in such a communication system.
Conventional network-based communication systems include systems configured to operate in accordance with well-known synchronous transport standards, such as the synchronous optical network (SONET) and synchronous digital hierarchy (SDH) standards.
The SONET standard was developed by the Exchange Carriers Standards Association (ECSA) for the American National Standards Institute (ANSI), and is described in the document ANSI T1.105-1988, entitled “American National Standard for Telecommunications—Digital Hierarchy Optical Interface Rates and Formats Specification” (September 1988), which is incorporated by reference herein. SDH is a corresponding standard developed by the International Telecommunication Union (ITU), set forth in ITU standards documents G.707 and G.708, which are incorporated by reference herein.
The basic unit of transmission in the SONET standard is referred to as a synchronous transport signal level-1 (STS-1). It has a serial transmission rate of 51.84 Megabits per second (Mbps).
Synchronous transport signals at higher levels may be concatenated or channelized. For example, an intermediate unit of transmission in the SONET standard is referred to as synchronous transport signal level-3, concatenated (STS-3c). It has a serial transmission rate of 155.52 Mbps. The corresponding unit in the SDH standard is referred to as STM-1. In a concatenated synchronous transport signal, the entire payload is available as a single channel. A channelized signal, by way of contrast, is divided into multiple channels each having a fixed rate. For example, the channelized counterpart to the concatenated STS-3c signal is denoted STS-3. STS-3 is a channelized signal that comprises three separate STS-1 signals each at 51.84 Mbps.
A given STS-3c or STM-1 signal is organized in frames having a duration of 125 microseconds, each of which may be viewed as comprising nine rows by 270 columns of bytes, for a total frame capacity of 2,430 bytes per frame. The first nine bytes of each row are overhead, while the remaining 261 bytes of each row are payload. The overhead includes transport overhead (TOH) and path overhead (POH). The TOH includes section overhead (SOH), pointer information, and line overhead (LOH). Additional details regarding signal and frame formats can be found in the above-cited documents.
In conventional SONET or SDH network-based communication systems, synchronous transport signals like STS-3c or STM-1 are mapped to or from corresponding higher-rate optical signals such as a SONET OC-12 signal or an SDH STM-4 signal. An OC-12 optical signal carries four STS-3c signals, and thus has a rate of 622.08 Mbps. The SDH counterpart to the OC-12 signal is the STM-4 signal, which carries four STM-1 signals, and thus also has a rate of 622.08 Mbps. The mapping of these and other synchronous transport signals to or from higher-rate optical signals generally occurs in a physical layer device commonly referred to as a mapper, which may be used to implement an add-drop multiplexer (ADM) or other node of a SONET or SDH communication system.
Such a mapper typically interacts with a link layer processor. A link layer processor is one example of what is more generally referred to herein as a link layer device, where the term “link layer” generally denotes a switching function layer. Another example of a link layer device is a field programmable gate array (FPGA). These and other link layer devices can be used to implement processing associated with various packet-based protocols, such as Internet Protocol (IP) and Asynchronous Transfer Mode (ATM), as well as other protocols, such as Fiber Distributed Data Interface (FDDI).
A mapper is often implemented in the form of an integrated circuit, also referred to herein as a “chip.” In a given physical layer device, multiple mappers may be arranged in a master-slave configuration, with one of the mappers operating as a master and a number of other mappers operating as slaves. Such a configuration must be tested to ensure that it meets specified requirements such as maximum delay differences between frame starting positions of the various inter-device traffic flows and pulses of a frame synchronization signal sent from a master to a slave. However, it can be very difficult to implement such testing using conventional techniques. This is due in part to the fact that the mappers typically have gate counts that may be on the order of ten million gates or more. The complexity of the mappers makes it difficult to determine and test an appropriate set of delay parameters for achieving frame synchronization in a particular master-slave configuration. For example, most simulation environments are unable to accommodate multiple instances of the mapper. Also, a typical testing system designed to test only a single mapper at a time is generally unable to measure certain internal signals that influence the selection of appropriate delay parameters. A conventional approach is therefore to construct a separate multiple-device testing system that simultaneously incorporates all of the master and slave devices. This involves substantial additional time and expense beyond that required for device level testing of a single mapper.
Accordingly, a need exists for an improved approach to testing of multiple mappers or other physical layer devices that are to be arranged in a master-slave configuration in a synchronous transport communication system.
Illustrative embodiments of the present invention overcome the above-noted drawbacks of conventional practice by providing techniques for testing of multiple mappers or other physical layer devices that are to be incorporated into a synchronous transport communication system, such as a SONET or SDH system.
In accordance with an aspect of the invention, multiple mapper integrated circuits or other devices to be arranged in a master-slave configuration are individually tested using a single-device testing system that ensures that the devices, when eventually arranged in the master-slave configuration, will satisfy a synchronization requirement or other interconnection requirement of that configuration. The testing system comprises traffic generation circuitry configured to generate traffic flows for application to respective inputs of a first device, delay circuitry configured to provide selectable delays to respective ones of the input traffic flows, and traffic checking circuitry configured to determine if output traffic flows received from respective outputs of the first device are substantially error free. The testing system further comprises controller circuitry configured to switch the first device between master and slave modes of operation, to control the delay circuitry to adjust frame starting positions of respective ones of the input traffic flows, and to control the first device to adjust frame starting positions of respective ones of the output traffic flows. Also included in the testing system is monitor circuitry configured to determine sets of measured delay parameters for the respective master and slave modes of operation.
In testing the first device, the controller circuitry of the testing system configures that device into one of a master mode of operation and a slave mode of operation, and adjusts frame starting positions of respective traffic flows associated with the configured mode until measured delay parameters of that mode substantially match corresponding ones of a selected set of prospective delay parameters. If the traffic checking circuitry determines that the traffic flows of the one configured mode as adjusted are substantially error free, the controller circuitry configures the first device into the other mode, and adjusts frame starting positions of respective traffic flows associated with the other configured mode of the first device until measured delay parameters of that mode substantially match corresponding ones of the selected set of prospective delay parameters. If the traffic checking circuitry determines that the traffic flows of the other configured mode as adjusted are substantially error free, the first device is identified as satisfying the requirement for interconnection with the one or more other devices in the master-slave configuration, and the selected set of prospective delay parameters is identified as an acceptable set of delay parameters for use with the first device in the master-slave configuration.
The testing may be repeated for other sets of prospective delay parameters, to determine if such other sets of prospective delay parameters should also be identified as acceptable for use with the first device in the master-slave configuration.
The testing may also be repeated for each of one or more other devices to be arranged in the master-slave configuration, using at least one selected set of prospective delay parameters that is identified as acceptable for use with the first device in the master-slave configuration.
The first device and the one or more other devices may comprise respective SONET/SDH mappers. The master-slave configuration may comprise, for example, the first device configured as a master mapper and two or more other devices configured as slave mappers.
Illustrative embodiments of the invention as described herein provide a number of significant advantages over the conventional techniques previously described. For example, these embodiments allow the determination and testing of an appropriate set of delay parameters for achieving frame synchronization in a particular master-slave configuration, without the need for a separate multiple-device testing system that simultaneously incorporates all of the master and slave devices. Instead, the delay parameters for the master-slave configuration can be determined and verified in an efficient manner using a modified version of a testing system that tests only a single mapper at a time, and thus in less time and at lower cost than is currently possible using conventional approaches.
The invention will be illustrated herein in conjunction with exemplary testing systems for testing mappers that are to be arranged in a master-slave configuration in a network-based communication system. It should be understood, however, that the invention is more generally applicable to any testing system in which it is desirable to provide improved efficiency and accuracy in testing of devices that are to be arranged in a master-slave configuration.
The link layer processor 104 is an example of what is more generally referred to herein as a “link layer device.” Such a device is intended to be broadly construed to encompass any type of processor which performs processing operations associated with a link layer of a network-based system. The term “physical layer device” as used herein is intended to encompass a device which provides an interface between a link layer device and a physical transmission medium of a network-based system.
In the
The mappers 102 perform signal mapping functions on SONET/SDH signals of a type generally known in the art. For example, network 108 may comprise routers, switches or other network elements of a SONET/SDH network operating as described in the above-cited SONET/SDH standards documents. It should be noted that the term “SONET/SDH” as used herein refers to SONET and/or SDH. The mappers 102 may provide an interface between such SONET/SDH network elements and other system elements, such as plesiochronous digital hierarchy (PDH) elements that process DS1/E1 and/or DS3/E3 signals.
The mappers 102 and link layer processor 104 may include additional functionality of a conventional type. Such additional functionality, being well known to those skilled in the art, will not be described in detail herein, but may include functionality associated with known mappers, such as the LSI Hypermapper™, Ultramapper™ and Supermapper™ devices, and known link layer devices, such as the LSI Link Layer Processor. These LSI devices are commercially available from LSI Corporation of Allentown, Pa., U.S.A. The network processor 106 may comprise, for example, a conventional network processor such as an LSI Advanced PayloadPlus® network processor in the APP300, APP500 or APP650 product family, also commercially available from LSI Corporation.
Additional details regarding conventional aspects of a SONET/SDH mapper can be found in, for example, TMXF84622 Ultramapper™ 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0, Ultramapper™ Resource Document, Jun. 6, 2002, which is incorporated by reference herein.
The mappers 102, link layer processor 104, and network processor 106 in this illustrative embodiment are installed on a line card 109 of the system 100. The line card 109 is coupled between network 108 and a switch fabric 110 of the system 100 as shown. The link layer processor 104 and network processor 106 are configured to communicate packets, cells or other protocol data units (PDUs) between the network 108 and the switch fabric 110 which controls switching of PDU data. As indicated previously, the mappers 102 serve to interface the link layer processor 104 to physical transmission media of the network 108, which may comprise optical fiber links or any other type of transmission media.
Also installed on the line card 109 is a host processor 112. This processor is used to configure and control one or more of the other processing elements of the line card, such as the mappers 102, link layer processor 104 and network processor 106. As a more particular example, a given such host processor utilized to configure and control both the mappers 102 and the link layer processor 104 is referred to herein as a microprocessor unit (MPU). Portions of the host processor functionality may be incorporated into one or more of elements 102, 104 or 106 in alternative embodiments of the invention.
Various elements of the system 100 may be implemented, by way of example and without limitation, utilizing a microprocessor, central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), FPGA, or other type of data processing device, as well as portions or combinations of these and other devices.
It should be noted that the line card configuration shown in
The interface 105 between the mappers 102 and the link layer processor 104 may comprise a conventional interface over which signals are transmitted from mappers to a link layer processor, and over which signals are received by mappers from a link layer processor.
The mappers 102 may be equipped with payload extraction and insertion functionality, such that SONET/SDH payloads can be communicated between the mappers and the link layer device. See U.S. patent application Ser. No. 11/839,971, filed Aug. 16, 2007 and entitled “Synchronous Transport Signal Mapper with Payload Extraction and Insertion Functionality,” which is commonly assigned herewith and incorporated by reference herein.
The mappers 102 may also or alternatively be configured to support 1+1 protection switching. For example, the mappers may comprise a working device and a protection device, with in-band communication of alarm status information or other types of information between the protection device and the working device. Such arrangements are described in U.S. patent application Ser. No. 11/935,533, filed Nov. 6, 2007 and entitled “In-Band Communication of Alarm Status Information in a Synchronous Transport Communication System,” which is commonly assigned herewith and incorporated by reference herein.
The interface 107 between the link layer processor 104 and the network processor 106 may be, for example, a conventional interface such as a SPI-3 interface as described in Implementation Agreement OTF-SP13-01.0, “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices,” Optical Internetworking Forum, 2001, which is incorporated by reference herein. Other types of known interfaces, such as POS-2, may also be used.
Although the link layer processor 104 and network processor 106 are shown as separate elements in this illustrative embodiment, other embodiments may combine the functionality of the link layer processor and the network processor into a single link layer device. The general term “link layer device” as used herein is thus intended to encompass devices which incorporate at least a portion of the functionality commonly associated with a network processor.
For example, a given link layer device may be configured to provide flow control, traffic shaping and other functions. It may include an internal memory, as well as an interface to an external memory. Such memory elements may be utilized for implementing PDU buffer memory, queuing and dispatch buffer memory, etc. The link layer device may further include one or more memory controllers, as well as appropriate interface circuitry for interfacing with the mappers 102 or other physical layer device(s), the switch fabric 110, and other external devices, such as the host processor 112, which may be configured to communicate with the link layer device over a standard bus architecture, e.g., a peripheral component interconnect (PCI) bus. The link layer device may also include a scheduler, queuing and dispatch logic, as well as other conventional elements not explicitly shown in the figure. The operation of these and other conventional elements, being well understood by those skilled in the art, is not described in detail herein.
Numerous alternative interfacing arrangements are possible. It is also possible that, in other embodiments, a given link layer device may be combined with one or more physical layer devices into a single device. Thus the mappers 102 and any associated physical layer device(s) need not be physically separate from the link layer processor 104 as in the
It may be assumed with reference to the system 100 of
It should also be noted that the particular arrangement of system elements shown in
Although the master-slave configuration in the
Traffic flows between the master 102M and the slaves 102S in
As mentioned previously herein, in testing a given implementation of multiple mappers arranged in a master-slave configuration, it is important to determine and test an appropriate set of delay parameters for achieving frame synchronization in that configuration. The delay parameters should be selected such that the master-slave configuration meets specified requirements such as, for example, maximum specified delay differences between a pulse of a frame synchronization signal and frame starting positions of the various traffic flows associated with the interconnection of the master 102M and the slaves 102S. Illustrative embodiments of the invention allow such delay parameters to be determined and tested in a particularly efficient and accurate manner without the need to collectively implement all of the interconnected mappers in a separate multiple-device testing system.
In the master-slave configuration of
As indicated previously, each of the mappers 102 in the present embodiment is assumed to be controllable between operation as a master and operation as a slave. For a given mapper operating in the master mode, the frame sync is an output, while for a given mapper operating in the slave mode, it is an input. The present invention, however, does not require that each mapper be controllable in this manner.
The above-noted specified requirements include maximum delay differences between frame starting positions of the various traffic flows, as indicated by the respective Frame Sync pulses. This is generally due to limitations in buffer size and chip latency within the mappers.
The internal frame sync signals of the master and slave are internal signals that are not visible outside of the respective chips. That is, such signals cannot be observed at external pins of the packaged integrated circuits.
The timing diagram of
As the associated traffic and frame sync signals are observable externally to the mappers, the delay differences D1, D2 and D3 can be measured externally.
It should be noted that the delay differences D1, D2 and D3 are defined differently for different contexts herein, as will be explained in greater detail below.
The timing diagram of
As the internal frame sync signals of the master and slave are internal signals that cannot be observed at external pins of the packaged integrated circuits, the delay differences D4, D5 and D6 cannot be measured externally.
The maximum internal delay differences D4, D5 and D6 that can be accommodated within a particular master-slave configuration are determined by factors such as the internal buffer size and chip latency of the master and slave chips. For example, limits on D4 are determined by the buffer size and chip latency of the slave 102S.
It is important to determine a configuration of the master and slave mappers that satisfies the maximum internal delay differences D4, D5 and D6, in order to ensure that frequency synchronization can be maintained. As noted above, the delay differences D1, D2 and D3 are observable externally to the mappers.
Referring now to
The testing system 400 further comprises a generator 430, checker 432 and programmable delay component 434 for each of the line protection interface, mate interface and new mate interface of the mapper chip 402. The generator, checker and programmable delay components are more particularly denoted 430-1, 432-1 and 434-1 for the line protection interface, 430-2, 432-2 and 434-2 for the mate interface, and 430-3, 432-3 and 434-3 for the new mate interface. Other elements of the testing system 400 include a master/slave controller 410, 2-to-1 multiplexers 411A and 411B, a sync position controller 412, a frame sync generator/monitor 414, a sync position monitor 416, a delay parameter selector 418, and a comparison element 420.
The flow diagram of
As the mapper chip 402 at this point in the process is in its master mode of operation, D1 is the delay difference between the frame sync output and the frame starting position of the new mate output traffic, D2 is the delay difference between the frame sync output and the frame starting position of new mate input traffic, and D3 is the delay difference between the frame sync output and the frame starting position of the line protection output traffic. The sync position monitor 416 measures the delay differences D1, D2 and D3, and a determination is made in step 508, using comparison element 420, as to whether or not those measured delay differences match the corresponding pre-set values stored in element 418. The “pre-set values” in the present embodiment are an example of what is more generally referred to herein as “a selected set of prospective delay parameters.” Other embodiments can use other types of difference parameters, or more generally, delay parameters.
If the measured D1, D2 and D3 values match the corresponding pre-set values, the process moves to step 510, and otherwise returns to step 506 for the sync position controller 412 to make a further adjustment in the frame starting positions of the chip input and output traffic. The sync position controller will thus continue adjusting the frame starting positions until a determination is made in step 508 that the measured values match the pre-set values.
In step 510, a determination is made as to whether or not the traffic has no errors or is otherwise substantially error free for the selected set of delay differences D1, D2 and D3. In this context, “substantially error free” is intended to encompass an error rate at or below an acceptable level, and thus should not be construed as requiring zero errors. If the traffic is not substantially error free, the selected set of parameters is not a workable set, and the process therefore moves to step 522 to determine if there are any other sets of parameters to be tested. If there is at least one additional set of parameters remaining to be tested, the process returns to step 504 to select a given such additional set for testing. Otherwise there is no workable set of parameters, and the test ends with a negative result in step 524.
If the traffic is determined in step 510 to be substantially error free, the process in step 512 switches the mapper chip 402 to its slave mode of operation using master/slave controller 410, configuring it to work for normal traffic. The sync position controller 412 then adjusts the frame starting positions of the input and output traffic, as indicated in step 514.
It should be noted that steps 514, 516 and 518 performed with the mapper chip 402 in its slave mode of operation are generally analogous to respective steps 506, 508 and 510 previously performed with the mapper chip in its master mode of operation.
As the mapper chip 402 at this point in the process is in its slave mode of operation, the definitions of the D1, D2 and D3 values are different than when the mapper chip was in its master mode of operation. More specifically, with the mapper chip in its slave mode of operation, D1 is the delay difference between the frame sync input and the frame starting position of the new mate input traffic, D2 is the delay difference between the frame sync input and the frame starting position of new mate output traffic, and D3 is the delay difference between the frame sync input and the frame starting position of the mate input traffic. The sync position monitor 416 measures these delay differences D1, D2 and D3, and a determination is made in step 516, using comparison element 420, as to whether or not those measured delay differences match the corresponding pre-set values stored in element 418.
If the measured D1, D2 and D3 values match the corresponding pre-set values, the process moves to step 518, and otherwise returns to step 514 for the sync position controller 412 to make a further adjustment in the frame starting positions of the chip input and output traffic. The sync position controller will thus continue adjusting the frame starting positions until a determination is made in step 516 that the measured values match the pre-set values.
In step 518, a determination is made as to whether or not the traffic has no errors or is otherwise substantially error free for the selected set of delay differences D1, D2 and D3. If the traffic is not substantially error free, the selected set of parameters is not a workable set, and the process therefore moves to step 522 to determine if there are any other sets of parameters to be tested. If there is at least one additional set of parameters remaining to be tested, the process returns to step 504 to select a given such additional set for testing. If the traffic is determined in step 518 to be substantially error free, the process in step 520 logs the selected set of parameters as a workable set for both master and slave modes of operation of the mapper chip 402. One or more additional sets of parameters may be tested if determined to be available in step 522, and otherwise the testing ends in step 524.
As indicated previously, if the test ends in step 524 without any workable set of parameters being found, it generally means that the mapper chip 402 cannot be connected in a master-slave configuration of the type shown in
It should be understood that the particular process steps of
Also, although the master mode of operation is tested first in the
The illustrative embodiments of
The memory 604 may store selected sets of prospective delay parameters that are to be tested in the manner described in conjunction with
In other embodiments, portions of the testing circuitry 606, such as the controllers 616, may be implemented within the processor 602.
As noted previously, the illustrative embodiments avoid the need for a testing system that can simultaneously test multiple mappers in a master-slave configuration. A single-mapper testing system such as that shown in
A testing system in accordance with the invention may be implemented in the form of one or more integrated circuit devices suitable for installation on a board or card of an otherwise conventional testing system.
In a given such integrated circuit implementation, identical die are typically formed in a repeated pattern on a surface of a semiconductor wafer. Each die includes at least a portion of testing system as described herein, and may include other structures or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
Again, it should be emphasized that the embodiments of the invention as described herein are intended to be illustrative only. For example, the invention can be implemented using a wide variety of other types of master-slave configurations, with different numbers of master and slave devices, than those previously described in conjunction with the illustrative embodiments.
It should also be understood that although the illustrative embodiments are described primarily in the SONET/SDH context using master-slave configurations having particular frame sync relationship requirements between master and slave devices, the disclosed techniques can be adapted in a straightforward manner for use in numerous other communication system applications involving interconnection of master and slave devices.
In addition, the particular arrangements of testing system circuitry and other elements as shown in
These and numerous other alternative embodiments within the scope of the following claims will be readily apparent to those skilled in the art.
