Delay time estimation method and recording medium storing estimation program

Abstract

The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to delay time estimation methods for estimating a delay time in a logic circuit composed of transistors and to recording mediums in which a computer program for executing a delay time estimation method is stored. More particularly, the present invention relates to a delay-time estimation method and a recording medium storing an estimation program with which efficient and precise estimation of delay time is possible.

[0003] 2. Description of the Related Art

[0004] The necessity for accurate signal analysis in a logic circuit is growing for designers of high-speed large-scale LSIs. Signal delay is one of the most important parameters because it is important for an LSI designer to know a timing margin in order to determine whether an LSI can operate properly. Methods for modeling and estimating time delay have been proposed.

[0005] FIGS. 9 through 11 show a processing flow for delay time estimation according to the related art. Referring to FIG. 9, the related-art delay estimation includes extraction of information relating to connection of the target circuit from a layout. The extracted circuit is modeled as a series comprising inverters (INV) 101 and 102 connected via a wire 103. Based on this circuit connection information, circuit configuration information in which a load is modeled by an RC component is produced, as shown in FIG. 10. A source model 106 corresponding to the inverter 101 is modeled by a combination of a power source 104 and resistance 105. A load component 108 comprises an RC distributed constant circuit 107 corresponding to the wire 103, and input pin capacitance Cg corresponding to the inverter 102, the RC distributed constant circuit 107 and the capacitance Cg being determined so that the admittance downstream from an output terminal of the gate provides a match with a third-order approximation.

[0006] The resistance and capacitance constituting the load component 108 is approximated by a finite number of RC components. The input capacitance of the RC distributed constant circuit 107 is modeled by capacitance C2. The combined output capacitance of the RC distributed constant circuit 107 and input pin capacitance Cg of the inverter 102 is modeled by capacitance C1. The capacitance C1, capacitance C2 and resistance R of the RC distributed constant circuit 107 form a π-load model 109 as shown in FIG. 11.

[0007] The π-load model, formed by two C components and one R component, is constructed such that, for any type of source model 106, a voltage waveform, occurring at the output terminal of the gate when the circuit of FIG. 10 is established, is approximated by a voltage waveform obtained as a result of analyzing the circuit of FIG. 11.

[0008] The approximation described above is disclosed in Peter R. O'Brien and Thomas L. Savarino, Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation, Proc. IEEE International Conference on Computer-Aided Design, 1989. Admittance Y(s) looking downstream from the gate output terminal is estimated (FIG. 3, equations (19)-(32)). The admittance Y(s) thus obtained is used to estimate R, C1 and C2 (equations (14)-(16)).

[0009] The load model 109 is then connected to the source model 106 so as to estimate a delay time through response analysis. The voltage level of the power source 104 and the resistance 105 have respective values determined by modeling conditions. The method of computing the voltage level and resistance is described in details in Florentin Dartu, Noel Menezes, Jessica Qian, and Lawrence T. Pillage, A Gate-Delay Model for High-Speed CMOS Circuits, Proc. 31st ACM/IEEE Design Automation Conference, 1994, so that a detailed description is omitted.

[0010] A description will now be given of the operation according to the related art.

[0011] FIG. 12 shows a construction of the inverter 101 comprising a PMOS transistor and an NMOS transistor. In a rising transition at the output terminal Y, as the potential at the input terminal A goes from a low level (L) to a high level (H), the PMOS transistor P1 makes a transition from an OFF state to an ON state so as to charge an output load. When an increase in the potential between the source and drain of the PMOS transistor P1 is relatively smaller than the magnitude of change in the gate potential, a transition from a region, characterized by an increase in a current with time, to another region characterized by a rapid exponential decrease in the current occurs (see pattern 2 of FIG. 5). Referring to FIG. 13, in the related-art source model 106, an internal voltage source E(t), whose voltage level shows a linear variation between 0 ad Vdd in a time Δt, is used to represent the transition described above.

[0012] According to the related art, the a-load model 109 shown in FIG. 11 subject to delay estimation is approximated by a purely capacitive load model as shown in FIG. 14 providing an equivalent response. In this case, equivalent capacitance is determined by considering the shielding effect provided by the resistance R constituting the π-load model 109. A delay time is determined by searching a table listing delay time along with gradients of predetermined input waveforms and output load capacitance. The table is searched so that a delay time that matches the modeling condition is determined by interpolation.

[0013] The related-art delay time estimation has a disadvantage in that it is not adapted for another possible transition pattern (pattern 1 of FIG. 5) in which there is a transition from a first region, characterized by an increase in current with time, to a second region, characterized by a gradual decrease in current, and then to a third region, characterized by an exponential decrease. The related-art internal power source model E(t) as shown in FIG. 13, characterized by a linear variation between 0 and Vdd in a time Δt, fails to represent a saturation region in which the current gradually decreases (region 2 of FIG. 5). Therefore, the related-art method fails to provide delay time estimation that matches the operating characteristic of transistors.

[0014] Another disadvantage of the related art is that there is a need for a library of two-dimensional delay tables listing gradients of input waveforms and output load capacitance, thus making it necessary to store a large volume of data. Interpolation errors are incurred as a result of using the tables. If the π-load model is to be used instead of the purely capacitive model, the dimension of the table increases so that the volume of data is increased, thereby rendering its implementation impossible. The practice of conversion into equivalent capacitance, performed in this background, generates errors.

SUMMARY OF THE INVENTION

[0015] Accordingly, a general object of the present invention is to provide a delay time estimation method and a recording medium storing an estimation program in which the aforementioned disadvantages are eliminated.

[0016] Another and more specific object of the present invention is provide a precise delay time estimation method and a recording medium storing an estimation program in which a saturation region, characterized by a gradual decrease in current, is represented so that delay time estimation that matches the transistor characteristic.

[0017] The aforementioned objects can be achieved by a delay time estimation method for estimating a delay time in a logic circuit that includes a MOS transistor, comprising the steps of: modeling the MOS transistor by a resistive element having fixed resistance and a power source voltage that varies with time; and segmenting an operating characteristic of the MOS transistor thus modeled into a fist region in which a current increases as a gate potential varies, a second region corresponding to a saturation region of the MOS transistor in which region the current gradually decreases as the gate potential remains constant, and a third region corresponding to a linearity region of the MOS transistor in which region the current decreases as the gate potential remains constant.

[0018] The delay time estimation method may be adapted for a circuit in-which a plurality of logic circuits that includes MOS transistors and comprise the steps of: segmenting an operating characteristic of last-stage MOS transistor constituting a logic circuit of a last stage into a first region in which a current increases as a gate potential varies, a second region corresponding to a saturation region of the last-stage MOS transistor in which region the current gradually decreases as a gate potential remains constant and a third region corresponding to a linearity region of the last-stage MOS transistor in which region the current decreases as the gate potential remains constant.

[0019] E=Rs×i(t)+v(t) may hold for t=Δt1 and t=Δt1+Δt2, where E denotes the power source voltage, Rs denotes resistance of a model of the power source, i(t) denotes a charge current of a load model, v(t) denotes a charge voltage of the load model, and wherein V1, Δt1 and Δt2 are determined based on a fact that values of E-v(t) and i(t) reside on an Ids-Vds characteristic curve at a given gate potential, where Ids denotes a drain-source current and Vds denotes a drain-source voltage, and where V1 denotes a voltage at a boundary between the first region and the second region, Δt1 denotes a time required to arrive at the boundary, and Δt2 denotes time required to reach the power source voltage via the second region.

[0020] The delay time estimation method may employ a delay library including function information for specifying polygonal lines that provide a model of an Ids-Vds characteristic at a given potential and also including function information related to a slew rate specifying a fixed delay.

[0021] The aforementioned objects can also be achieved by a recording medium storing a computer program that executes a delay time computation method.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:

[0023] FIG. 1 illustrates extraction of circuit connection information according to a first embodiment of the present invention;

[0024] FIG. 2 illustrates generation of circuit configuration information;

[0025] FIG. 3 illustrates generation of load model;

[0026] FIG. 4 is a graph showing variation of power source voltage with time;

[0027] FIG. 5 is a graph showing patterns of waveform of a current;

[0028] FIG. 6 is a Ids-Vds characteristic graph according to the E(t) model of the present invention;

[0029] FIG. 7 is an illustration of an operating point;

[0030] FIG. 8 illustrates delay time estimation in multiple-stage cells;

[0031] FIG. 9 illustrates extraction of circuit connection information according to the related art;

[0032] FIG. 10 illustrates generation of circuit configuration information according to the related art;

[0033] FIG. 11 illustrates generation of load model according to the related art;

[0034] FIG. 12 illustrates logic paths of a two-input inverter circuit comprising two transistors;

[0035] FIG. 13 is a graph showing variation of power source voltage with time according to the related art; and

[0036] FIG. 14 is a purely capacitive approximation of a π-load model subject to delay time estimation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] First Embodiment

[0038] FIGS. 1 through 3 show a processing flow for delay time estimation according to a first embodiment of the present invention. FIG. 1 shows extraction of circuit connection information comprising inverters 1 and 2 connected via a wire 3. Each of the inverters 1 and 2 is comprised of a PMOS transistor and a NMOS transistor (see FIG. 12). Circuit configuration information as shown in FIG. 2 is then generated. A source model 6 corresponding to the inverter 1 is modeled by a combination of a power source 4 and resistance 5. A load component 8 comprises a RC distributed constant circuit 7 corresponding to the wire 3, and input pin capacitance Cg corresponding to the inverter 2.

[0039] The input capacitance of the RC distributed constant circuit 7 of the load component 8 is modeled by capacitance C2. The combined output capacitance of the RC distributed constant circuit 7 and input pin capacitance Cg is modeled by capacitance C1. The capacitance C1, capacitance C2 and resistance R of the RC distributed constant circuit 7 form a π-load model 9 as shown in FIG. 3. The description so far corresponds to the description of the related art with reference to FIGS. 9 through 11.

[0040] The present invention introduces a model of a power source E, referred to hereinafter as an E(t) model, to represent the source model 6. In the E(t) model, time-dependence of the source resistor of the transistor is represented. As shown in FIG. 4, a power source voltage waveform is represented using polygonal lines. The voltage varies from 0 to V1 in a time Δt1 and varies from V1 to Vdd in a time Δt2.

[0041] The E(t) model according to the invention is designed to produce an appropriate match with a current flowing from an output pin of a gate to a load. Therefore, the current waveform is considered in determining the configuration of E(t). As shown in FIG. 5, two patterns of current waveforms could occur depending on the driving capability of the cell and the magnitude of the load. In a first pattern, the current makes a transition from region 1 in which the current increases with time, to region 2 in which the current gradually decreases and finally to region 3 in which the current decreases exponentially. In a second pattern, the current makes a transition from region 1 in which the current increases with time to region 3 in which the current rapidly decreases exponentially.

[0042] A consideration is given of the waveform of the E(t) model adapted for the current characteristic described above. Region 3 is a linearity region in which the current determined by the time constant of the circuit flows. Therefore, E(t)=Vdd is applicable to region 3. As a consequence of this, E(t) functions of different waveforms should be applied to regions 1 and 2 respectively. The E(t) function for region 1 differs from that of region 2 with respect to variation with time. However, both E(t) functions for regions 1 and 2 show continuity at points corresponding to respective bounds of regions 1 and 2. As shown in FIG. 4, in the first embodiment, straight lines with different gradients are used to represent respective functions for respective regions to facilitate the ease of computation.

[0043] The time at which E(t) starts to rise does not always match a point of time t=0. The delay between the point of time t=0 and the time at which E(t) starts to rise is defined as a fixed delay to. The waveform of E(t) is expressed as a polygonal line showing that the voltage increases to E1 for a first period of time Δt1 after an elapse of the fixed delay t0. In a subsequent period of time Δt2, the voltage increases to Vdd. t0, Δt1, V1, Δt2 indicate parameters that describe the circuit response.

[0044] The present invention introduces the use of a delay library. The delay library is constructed by function information Δt1, V1, Δt2 specifying the Ids-Vds polygonal line at a given gate potential and by function information Tslew, Tslew being an input slew rate that specifies the fixed delay t0, and given as a pre-extracted delay parameter. A large volume of data for the delay table according to the related art is not necessary. The fixed delay to is given as a function of Tslew. Tslew may be defined as a time that elapses before the input waveform completes its transition to 0 or Vdd. For example, the fixed delay t0 is approximated by, for example, an equation t0(Tslew)=K10+K20*Tslewα. In this case, the function information of the input slew rate specifying the fixed delay and stored in the delay library includes K10, K20 and α.

[0045] In pattern 2, region 2 is absent. In this case, the waveform of E(t) adapted for transition from region 1 to region 3 is given assuming that Δt2=0 and V1=E.

[0046] Using the waveform of E(t) shown in FIG. 4, the gate output v2(t) of the model at a rising edge of the waveform is defined by the following equations.

[0047] First, under the following definition of z, p1, p2 denoting poles of a transfer function, 1$\begin{array}{cc}\{\begin{array}{c}z=\frac{1}{{\mathrm{RC}}_1}+\frac{1}{{\mathrm{RC}}_2}\\ p_1,p_2=\frac{1}{2}\left\{\left(\frac{1}{{\mathrm{RC}}_1}+\frac{1}{{\mathrm{RC}}_2}+\frac{1}{{\mathrm{RsC}}_2}\right)\pm \sqrt{{\left(\frac{1}{{\mathrm{RC}}_1}+\frac{1}{{\mathrm{RC}}_2}+\frac{1}{{\mathrm{RsC}}_2}\right)}^2-\frac{4}{{\mathrm{RRsC}}_1{C}_2}}\right\},\end{array}& \left(1\right)\end{array}$

[0048] functions f(t,Δt,V) and a(t,V) are defined as follows: 2$\begin{array}{cc}\{\begin{array}{c}f\left(t,\Delta t,V\right)=\{t-\frac{z}{p_1{p}_2}+\frac{p_1-z}{p_1\left(p_1-p_2\right)}\exp \left(-p_{1}t\right)\frac{p_2-z}{p_2\left(p_1-p_2\right)}\exp \left(-p_{2}t\right)\frac{V}{\Delta t}\\ a\left(t,V\right)=\left\{1-\frac{p_1-z}{p_1-p_2}\exp \left(-p_{1}t\right)+\frac{p_1-z}{p_1-p_2}\exp \left(-p_{2}t\right)\right\}V\end{array}.& \left(2\right)\end{array}$

[0049] Then, a model waveform description of v2(t) will now be defined more specifically in the following. 3$\begin{array}{cc}\text{<Case 1>}\Delta t_1=0v_2\left(t\right)=\{\begin{array}{c}0\\ a\left(t-\mathrm{t0},V_1\right)+f\left(t-t_0,\Delta t_2,E-V_1\right)\\ a\left(t-\mathrm{t0},V_1\right)+f\left(t-t_0,\Delta t_2,E-V_1\right)-f\left(t-t_0-\Delta t_2,\Delta t_2,E-V_1\right)\end{array}\begin{array}{c}\left(0\leqq t\leqq t_0\right)\\ \left(t_0<t\leqq t_0+\Delta t_2\right)\\ \left(t>t_0+\Delta t_2\right)\end{array}& \left(3\right)\\ \text{<Case 2>}\Delta t_2=0v_2\left(t\right)=\{\begin{array}{c}0\\ f\left(t-t_0,\Delta t_1,E\right)\\ f\left(t-t_0,\Delta t_1,E\right)-f\left(t-t_0-\Delta t_1,\Delta t_1,E\right)\end{array}\begin{array}{c}\left(0\leqq t\leqq t_0\right)\\ \left(t_0\leqq t\leqq t_0+\Delta t_1\right)\\ \left(t>t_0+\Delta t_1\right)\end{array}& \left(4\right)\\ \text{<Case 3>}\Delta t_1,\Delta t_3\ne 0v_2\left(t\right)=\{\begin{array}{c}0\\ f\left(t-t_0,\Delta t_1,V_1\right)\\ f\left(t-t_0,\Delta t_1,V_1\right)-f\left(t-t_0-\Delta t_1,\Delta t_1,V_1\right)+\\ f\left(t-t_0-\Delta t_1,\Delta t_2,E-V_1\right)\\ f\left(t-t_0,\Delta t_1,V_1\right)-f\left(t-t_0-\Delta t_1,\Delta t_1,V_1\right)+\\ f\left(t-t_0-\Delta t_1,\Delta t_2,E-V_1\right)-f\left(t-t_0-\Delta t_1-\Delta t_2,\Delta t_2,E-V_1\right)\end{array}\begin{array}{c}\left(0\leqq t\leqq t_0\right)\\ \left(t_0\leqq t\leqq t_0+\Delta t_1\right)\\ \left(t_0+\Delta t_1<t\leqq t_0+{\mathrm{\Delta t}}_1+\Delta t_2\right)\\ \\ \left(t>t_0+\Delta t_1+\Delta t_2\right)\\ \end{array}& \left(5\right)\end{array}$

[0050] A description will now be given of determination of the function information Δt1, V1 and Δt2 that specify the polygonal lines of Ids-Vds characteristic. Referring FIG. 5 showing transitions of the operating point of the transistor, three types of transitions, i.e., transition from region 1 to region 2, transition from region 1 to region 3 and transition from region 2 to region 3 are bounded by respective turning points. All of the three turning points reside on the Ids-Vds characteristic where Vgs=Vdd. This means that the turning points can be defined when the Ids-Vds characteristic where Vgs=Vdd is available. Region 3 corresponds to the linearity region of the MOS transistor, where charging and discharging occurs via a fixed resistance Rs, as required by the model. Therefore, the Ids-Vds characteristic of region 3 should be described under the condition Ids=Vds/Rs. Region 2 corresponds to the saturation region of the MOS transistor and described as a region where the current gradually decreases. In order to describe these features, the Ids-Vds characteristic where Vgs=Vdd is represented as shown in FIG. 6, using Rs, I0 and I1. In this model, the region where Vds<RsI1 is defined as the linearity region, and the region where Vds>RsI1 is defined as the saturation region. By defining the saturation current I0 when Vds=Vdd separately, the characteristic where the current gradually decreases as Vds decreases (V2 increases) in the saturation region is depicted.

[0051] In determining Δt1, V1 and Δt2, Rs, I0 and I1 are given as pre-extracted parameters.

[0052] 1. Determination of Δt1

[0053] First, Δt1 is determined. In determining Δt1, it is assumed that the transistor operates according to pattern 2. From the E(t) model circuit diagram shown in FIG. 3, it is known that

E (t)=v2(t)+Rsi(t)  (6)

[0054] Since we are assuming that pattern 2 takes place, transition occurs from region 1 to region 3. Δt a turning point t=t0+Δt1, E(t0+Δt1)=E so that

v 2 (t0+Δt1)+Rsi(t0+Δt1)=E  (7)

[0055] Since it is assumed that the transistor operates according to pattern 2, Δt2=0 so that equation (4) is used 4$\begin{array}{cc}{v}_2\left(t_0+\Delta t_1\right)=\left\{\Delta t_1-\frac{z}{p_1{p}_2}+\frac{p_1-z}{p_1\left(p_1-p_2\right)}\exp \left(-p_1\Delta t_1\right)-\frac{p_2-z}{p_2\left(p_1-p_2\right)}\exp \left(-p_2\Delta t_1\right)\right\}\frac{E}{\Delta t_1}& \left(8\right)\end{array}$

[0056] Where i(t+Δt1) is a current in the saturation region.

[0057] (1) According to the simplest transistor model, i∝(vgs−vth)2. Approximating Vgs by a linear equation, i∝ct2.

[0058] (2) If we consider the fixed delay, i=0 at t=t0.

[0059] (3) Using the linear equation approximation, Vgs=Vdd at t=Tslew, resulting in the Ids-Vds characteristic of FIG. 6. The current at t=Tslew is equal to the current I1 at the boundary of the linearity region and the saturation region where Vgs=Vdd. Therefore, i=I1 at t=Tslew. The equation that satisfies this condition is given by 5$\begin{array}{cc}i\left(t\right)={I_1\left(\frac{t-t_0}{\mathrm{Tslew}-t_0}\right)}^2& \left(9\right)\end{array}$

[0060] Equation (9) is used for i(t0+Δ1). Substituting these equations into (7), we obtain 6$\begin{array}{cc}\left\{-\frac{z}{p_1{p}_2}+\frac{p_1-z}{p_1\left(p_1-p_2\right)}\exp \left(-p_1\Delta t_1\right)\frac{p_2-z}{p_2\left(p_1-p_2\right)}\exp \left(-p_2\Delta t_1\right)\right\}E+{\mathrm{RsI}}_1\Delta \frac{t_1^3}{{\left(\mathrm{Tslew}-t_0\right)}^2}=0& \left(10\right)\end{array}$

[0061] This equation has a solution at Δt1.

[0062] When the solution to equation (1) is Δt1>Tslew−t0, i(t0+Δt1)>I1 so that there is digression from the Ids-Vds characteristic of FIG. 6 since the boundary between region 1 and region 3 must reside on a straight line defining the gradient determined by RS. The reason for this is that the initial assumption that pattern 2 is the operation pattern failed as a result of transition from region 1 to region 2. In this case, we should proceed assuming that the transistor operates according to pattern 1. In pattern 1, the boundary between region 1 and region 2 is at t=t0+Δt1 where Vgs=E. Using the same linear equation for Vgs, the time is given by t=Tslew so that Δt1=Tslwe−t0.

[0063] In an exceptional case, it may be that Tslew−t0≦0. This is considered as a situation where it takes the current to take time before being output and where Vgs=E already when the output current starts flowing. According to the model, instant transition to the Ids-Vds where Vgs=Vdd occurs. Therefore, a model results in which region 1 is absent so that the operation starts in region 2 (Δt1=0).

[0064] Summarizing the above discussion, Δt1 is determined depending on the respective conditions as described below.

[0065] (1) Case 1: Tslew−t0≦0

[0066] Δt1=0

[0067] (2) Case 2: 0≦—t1≦Tslew−t0

[0068] Δt1 satisfies the following equation 7$\begin{array}{cc}\left\{-\frac{z}{p_1{p}_2}+\frac{p_1-z}{p_1\left(p_1-p_2\right)}\exp \left(-{\mathrm{p1\Delta t}}_1\right)\frac{p_2-z}{p_2\left(p_1-p_2\right)}\exp \left(-p_2\Delta t_1\right)\right\}E+{\mathrm{RsI}}_1\Delta \frac{t_1^3}{{\left(\mathrm{Tslew}-\mathrm{t0}\right)}^2}=0& \left(11\right)\end{array}$

[0069] (3) Case 3: when the solution to equation (11) is Δt1>Tslew−t0

[0070] Δt1=Tslew−t0

[0071] 2. Determination of V1

[0072] The following relationship holds for V1.

V 2 (t0+Δtl)+Rsi(t0+Δt1)=v1  (12)

[0073] V1 is determined based on equation (12).

[0074] (1) Case 1: Δt1=0

[0075] Vgs=Vdd at t=to so that I(t0) resides on the Ids-Vds characteristic of FIG. 6. From the definition of the fixed delay, v2(t0)=0 so that Vds=Vdd, showing that i(t0)=I0. Accordingly,

V 1 =RsI 0   (13)

[0076] (2) Case: 0<Δt1≦sTslew−t0

[0077] In this case, the,transistor operates according to pattern 2 where the transition from region 1 to region 3 occurs. Therefore,

V1=E  (14)

[0078] (3) Case 3: Δt1=Tslew−t0

[0079] Under this condition, the transistor operates according to pattern 1 so that Vgs=Vdd at t=t0+—t1. Since 0<v2(t0+Δt1)<RSI1, the operating point resides at a position shown in FIG. 7. In this case, i(t0+Δt1) is given by the following equation. 8$\begin{array}{cc}i\left(t_0+\Delta t_1\right)=I_0-\frac{v_2\left(t_0+\Delta t_1\right)}{E-{\mathrm{RsI}}_1}\left(I_0-I_1\right)& \left(15\right)\end{array}$

[0080] Using equation (5), v2(t0+Δt1) is given by the following equation. 9$\begin{array}{cc}{v}_2\left(t_0+\Delta t_1\right)=\left\{\Delta t_1-\frac{z}{p_1{p}_2}+\frac{p_1-z}{p_1\left(p_1-p_2\right)}\exp \left(-p_1\Delta t_1\right)-\frac{p_2-z}{p_2\left(p_1-p_2\right)}\exp \left(-p_2\Delta t_1\right)\right\}\frac{V_1}{\Delta t_1}& \left(16\right)\end{array}$

[0081] From the equations (12), (15) and (16), V1 is given by the following equation. 10$\begin{array}{cc}{v}_1=\frac{{\mathrm{RsI}}_0}{1-\frac{E-{\mathrm{RsI}}_0}{E-{\mathrm{RsI}}_I}\left\{\Delta t_1-\frac{z}{p_1{p}_2}+\frac{p_1-z}{p_1\left(p_1-p_2\right)}\exp \left(-p_1\Delta t_1\right)\frac{p_2-z}{p_2\left(p_1-p_2\right)}\exp \left(-p_2\Delta t_1\right)\right\}\frac{1}{\Delta t_1}}& \left(17\right)\end{array}$

[0082] 3. Determination of Δt2

[0083] In case 2, the transistor operates according to pattern 2 so that Δt2 is equal to 0. In case 1 and case 3, the following equation holds at a boundary between region 2 and region 3.

v 2 (to+Δt1+Δt2)+Rsi(t0+Δt1+Δt2)=E  (18)

[0084] Region 2 is a saturation region where Vgs=Vdd. Δt the boundary between region 2 and region 3, i=I1. For v2(t0+Δt1+Δt2), equation (3) (for case 1) or equation (for case 3) is used similarly to the other processes for determination of the function information.

[0085] Therefore, Δt2 for case 1 or case 3 satisfies

v 2 (t0+Δt1+Δt2)+RsI1=E  (19)

[0086] In case 1 or case 3, equation (19) has a solution at —t2>0.

[0087] A summary is given below how the function information is determined for different cases.

[0088] <Case 1> Tslew−t0≦0

[0089] Δt1=0

[0090] V1=RsI0

[0091] Δt2 should satisfy

[0092] v2(t0+Δt1+Δt2)+RsI1=E

[0093] <Case 2> 0<Δt1≦Tslew−t0, where Δt1 is a solution to the equation below 11$\begin{array}{cc}\left\{-\frac{z}{p_1{p}_2}+\frac{p_1-z}{p_1\left(p_1-p_2\right)}\exp \left(-p_1\Delta t_1\right)\frac{p_2-z}{p_2\left(p_1-p_2\right)}\exp \left(-p_2\Delta t_1\right)\right\}E+{\mathrm{RsI}}_1\Delta \frac{t_1^3}{{\left(\mathrm{Tslew}-t_0\right)}^2}=0\Delta t_1{V}_1=E\Delta t_2=0& \left(20\right)\end{array}$

[0094] <Case 3> when the first solution to the equation (20) is Δt1>Tslew−t012$\begin{array}{cc}\Delta t_1=Tslew-t_0{V}_1=\frac{Rs{I}_0}{1-\frac{E-Rs{I}_0}{E-Rs{I}_1}\left\{\Delta t_1-\frac{z}{p_1{p}_2}+\frac{p_1-z}{p_1\left(p_1-p_2\right)}\exp \left(-p_1\Delta t_1\right)-\frac{p_2-z}{p_2\left(p_1-p_2\right)}\exp \left(-p_2\Delta t_1\right)\right\}\frac{1}{\Delta t_1}}{v}_2\left(t_0+{\mathrm{\Delta t}}_1+{\mathrm{\Delta t}}_2\right)+Rs{I}_1=E\Delta t_2& \left(21\right)\end{array}$

[0095] The concept described above applies equally to the rising edge and the falling edge.

[0096] As described, according to the first embodiment, the power source is represeted as two types of combinations of straight lines showing variation with time. Accordingly, the gradual decrease of current in the saturation region of the transistor is properly reflected so that the delay time is estimated in a precise manner.

[0097] Second Embodiment

[0098] The method of estimation described above applies to a single-stage cell configuration in which the input directly controls the gate of the output transistor. In a multi-stage cell configuration (for example, a driving cell) the drain of the transistor having its input controlled controls the input of the next transistor so as to operate the output transistor.

[0099] The method of estimation for the single-cell configuration applies equally to the last stage of the multi-stage cell. Therefore, for the last stage, the same computation as performed for the single-cell is performed. In order to effect this computation, it is necessary to know the time to arrive at Vth and the value of Tslew for the input of the last stage of the internal node. A description will be given with reference to FIG. 8.

[0100] Vth_n denotes the threshold voltage of the NMOS transistor in the cell (inverter), Vth_p denotes the threshold voltage of the PMOS transistor in the cell (inverter). TslewP indicates the time required for the input waveform of the first stage cell to go from Vth_n to the power source voltage Vdd. T slewN indicates the time required for the output waveform of the first stage cell (input waveform of the last stage cell) to go from Vth_p to the ground voltage 0V.

[0101] The waveform of the first stage may be used to determine the time 0 and Tslew of the the corresponding cell. The reference time for computation of the last stage delayed with respect to the input to the cell. The delay time is denoted tmlt. Tslew of the last stage is different from Tslewp.

[0102] In the multi-stage cell, the delay time is determined by adding the delay determined using Tslew to tmlt. Therefore, in the multi-stage cell, the method for estimation of Tslew and Tmlt should be determined. Both Tslew and tmlt are internal node values and, therefore, are not considered to be dependent on the load connected to the output Y. Accordingly, Tslew and tmlt are functions of Tslewp specifying the waveform of the input A. The same approach employed to estimate the fixed delay of the single-stage cell is employed to estimate Tslew and tmlt. That is, Tslew and tmlt are considered to increase as Tslewp increases. Accordingly, the internal delay of the multi-stage cell is given by

t mlt =K 1m +K 2m Tslew p α t   (22)

[0103] Tslew internal to the multi-stage cell is given by

Tslew=K 1t +K 2t Tslew p α t   (23)

[0104] where K1m, K2m, αm, K1t, K1t and αt indicate delay parameters extracted before the estimation. These delay parameters are stored in the delay library. tmlt and Tslew are determined by using the delay library.

[0105] In delay time estimation, computation of internal node values is either skipped or not skipped depending on whether the single-stage cell or the multi-stage cell is subject to estimation. An efficient approach is to provide the following conditions in equations (22) and (23) when the single-stage cell is under consideration so that tmlt=0 and Tslew=Tslewp.

Klm=K2m=0, αm=1

K1t=0, K2t=αt=1  (24)

[0106] As described, accordingly to the second embodiment, a plurality of logic stages (CMOS logic gates) in a cell is divided into the last stage and the preceding stage(s). By estimating the waveform of the gate input at the last stage, the polygonal lines of the power source are estimated in a precise manner.

[0107] Third Embodiment

[0108] A recording medium is provided that stores a computer program for executing a delay time estimation according to the first and second embodiments. When a computer reads the program from the medium and executes the same, the delay time estimation of the invention can be efficiently performed.

[0109] The present invention is not limited to the above-described embodiments, and variations and modifications may be made without departing from the scope of the present invention.

Claims

1. A delay time estimation method for estimating a delay time in a logic circuit that includes a MOS transistor, comprising the steps of: modeling the MOS transistor by a resistive element having fixed resistance and a power source voltage that varies with time; and segmenting an operating characteristic of the MOS transistor thus modeled into a fist region in which a current increases as a gate potential varies, a second region corresponding to a saturation region of the MOS transistor in which region the current gradually decreases as the gate potential remains constant, and a third region corresponding to a linearity region of the MOS transistor in which region the current decreases as the gate potential remains constant.

2. The delay time estimation method according to claim 1 adapted for a circuit in which a plurality of logic circuits that includes MOS transistors, comprising the steps of: segmenting an operating characteristic of last-stage MOS transistor constituting a logic circuit of a last stage into a first region in which a current increases as a gate potential varies, a second region corresponding to a saturation region of the last-stage MOS transistor in which region the current gradually decreases as a gate potential remains constant and a third region corresponding to a linearity region of the last-stage MOS transistor in which region the current decreases as the gate potential remains constant.

3. The delay time estimation method according to claim 1, wherein

4. The delay time estimation method according to claim 1 which employs a delay library including function information for specifying polygonal lines that provide a model of an Ids-Vds characteristic at a given potential and also including function information related to a slew rate specifying a fixed delay.

5. A recording medium storing a computer program that allows a computer to perform the delay time computation method according to claim 1.