DELAY UNIT OF VOLTAGE CONTROL OSCILLATOR

Abstract

A delay unit having a complementary architecture for use in a voltage control oscillator includes a first voltage control oscillating circuit and a second voltage control oscillating circuit. The first voltage control oscillating circuit includes a first gain circuit, a first current-source circuit coupled to the first gain circuit, and a first load circuit. The second voltage control oscillator circuit includes a second gain circuit, a second current-source circuit coupled to the second gain circuit, and a second load circuit. At least one pair of the first and second gain circuits, the first and second current-source circuits and the first and second load circuits are implemented with complementary integrated circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

FIG. 1 is a functional block diagram schematically showing a conventional three-stage ring oscillator;

FIG. 2 is a circuit diagram of a conventional delay unit;

FIG. 3 is a circuit diagram of another conventional delay unit;

FIG. 4 is a circuit diagram of still another conventional delay unit;

FIG. 5 is a circuit diagram of an embodiment of a delay unit according to the invention;

FIG. 6 is a circuit diagram of a delay unit implemented with a NMOS voltage control oscillating circuit;

FIG. 7 is a circuit diagram of a delay unit implemented with a PMOS voltage control oscillating circuit;

FIG. 8 is a circuit diagram of a delay unit implemented with a complementary voltage control oscillating circuit according to the invention;

FIG. 9A is a waveform diagram of a clock signal generated by a four-stage ring voltage control oscillator implemented with the NMOS-based delay unit of FIG. 6;

FIG. 9B is a waveform diagram of a clock signal generated by a four-stage ring voltage control oscillator implemented with the PMOS-based delay unit of FIG. 7;

FIG. 9C is a waveform diagram of a clock signal generated by a four-stage ring voltage control oscillator implemented with the delay unit of FIG. 8 with a complementary architecture;

FIG. 10 is a frequency vs. voltage plot of a voltage control oscillator according to an embodiment of the present invention, which is obtained as a result of corner simulation;

FIG. 11A is a circuit diagram of a first alternative load circuit adapted to be used in the delay unit of FIG. 5;

FIG. 11B is a circuit diagram of a second alternative load circuit adapted to be used in the delay unit of FIG. 5;

FIG. 11C is a circuit diagram of a third alternative load circuit adapted to be used in the delay unit of FIG. 5;

FIG. 11D is a circuit diagram of a fourth alternative load circuit adapted to be used in the delay unit of FIG. 5;

FIG. 12A is a circuit diagram of a mirror circuit of a single ended type voltage control oscillator where the delay unit according to the invention can be applied; and

FIG. 12B is a circuit diagram of an alternative mirror circuit of a single ended type voltage control oscillator where the delay unit according to the invention can be applied.

Claims

1. A delay unit for use in a voltage control oscillator, comprising: a first voltage control oscillating circuit, comprising: a first gain circuit having a first input end, a second input end, a first output end and a second output end;a first current-source circuit coupled to the first gain circuit; anda first load circuit coupled to the first output end and the second output end; anda second voltage control oscillator circuit, comprising: a second gain circuit having a third input end, a fourth input end, a third output end and a fourth output end, the third input end, the fourth input end, the third output end and the fourth output end being coupled to the first input end, the second input end, the first output end and the second output end, respectively;a second current-source circuit coupled to the second gain circuit; anda second load circuit coupled to the third output end and the fourth output end;wherein at least one pair of the first and second gain circuits, the first and second current-source circuits and the first and second load circuits are implemented with complementary integrated circuits.

2. The delay unit according to claim 1 wherein the first and second gain circuits are complementary to each other, the first gain circuit comprises: a first NMOS transistor having a gate electrode and a drain electrode serving as the first input end and the second output end, respectively, and a source electrode coupled to the first current-source circuit; anda second NMOS transistor having a gate electrode and a drain electrode serving as the second input end and the first output end, respectively, and a source electrode coupled to the first current-source circuit; andthe second gain circuit comprises: a first PMOS transistor having a gate electrode and a drain electrode serving as the third input end and the fourth output end, respectively, and a source electrode coupled to the second current-source circuit; anda second PMOS transistor having a gate electrode and a drain electrode serving as the fourth input end and the third output end, respectively, and a source electrode coupled to the second current-source circuit.

3. The delay unit according to claim 1 wherein the first and second current-source circuits are complementary to each other, the first current-source circuit comprises: a third NMOS transistor having a gate electrode coupled to a first control voltage, a source electrode coupled to ground, and a drain electrode coupled to the first gain circuit; andthe second current-source circuit comprises: a third PMOS transistor having a gate electrode receiving a second control voltage, a source electrode coupled to a voltage source, and a drain electrode coupled to the second gain circuit.

4. The delay unit according to claim 1 wherein the first and second load circuits are selected from diode load circuits, resistor load circuits, symmetric load circuits, voltage control resistor load circuits or cross-coupled circuits.

5. The delay unit according to claim 1 wherein the first and second load circuits are complementary to each other, the first load circuit comprises: a fourth PMOS transistor having a drain electrode coupled to the second output end and a source electrode coupled to a voltage source; anda fifth PMOS transistor having a drain electrode coupled to the first output end and a gate electrode of the fourth PMOS transistor, a source electrode coupled to the voltage source, and a gate electrode coupled to the drain electrode of the fourth PMOS transistor; andthe second load circuit comprises: a fourth NMOS transistor having a drain electrode coupled to the fourth output end and a source electrode coupled to ground; anda fifth NMOS transistor having a drain electrode coupled to the third output end and a gate electrode of the fourth NMOS transistor, a source electrode coupled to ground, and a gate electrode coupled to the drain electrode of the fourth NMOS transistor.

6. A delay unit for use in a voltage control oscillator, comprising: a NMOS voltage control oscillating circuit having a first input end, a second input end, a first output end and a second output end; anda PMOS voltage control oscillating circuit having a third input end coupled to the first input end, a fourth input end coupled to the second input end, a third output end coupled to the first output end, and a fourth output end coupled to the second output end.

7. The delay unit according to claim 6 wherein the NMOS voltage control oscillating circuit comprises: a first gain circuit coupled to the first input end, the second input end, the first output end and the second output end;a first current-source circuit coupled to the first gain circuit; anda first load circuit coupled to the first output end and the second output end; and

8. The delay unit according to claim 6 wherein the first and second gain circuits are complementary to each other, the first gain circuit comprises: a first NMOS transistor having a gate electrode and a drain electrode serving as the first input end and the second output end, respectively, and a source electrode coupled to the first current-source circuit; anda second NMOS transistor having a gate electrode and a drain electrode serving as the second input end and the first output end, respectively, and a source electrode coupled to the first current-source circuit; andthe second gain circuit comprises: a first PMOS transistor having a gate electrode and a drain electrode serving as the third input end and the fourth output end, respectively, and a source electrode coupled to the second current-source circuit; anda second PMOS transistor having a gate electrode and a drain electrode serving as the fourth input end and the third output end, respectively, and a source electrode coupled to the second current-source circuit.

9. The delay unit according to claim 6 wherein the first and second current-source circuits are complementary to each other, the first current-source circuit comprises: a third NMOS transistor having a gate electrode coupled to a first control voltage, a source electrode coupled to ground, and a drain electrode coupled to the first gain circuit; andthe second current-source circuit comprises: a third PMOS transistor having a gate electrode receiving a second control voltage, a source electrode coupled to a voltage source, and a drain electrode coupled to the second gain circuit.

10. The delay unit according to claim 6 wherein the first and second load circuits are selected from diode load circuits, resistor load circuits, symmetric load circuits, voltage control resistor load circuits or cross-coupled circuits.

11. The delay unit according to claim 6 wherein the first and second load circuits are complementary to each other, the first loading circuit comprises: a fourth PMOS transistor having a drain electrode coupled to the second output end and a source electrode coupled to a voltage source; anda fifth PMOS transistor having a drain electrode coupled to the first output end and a gate electrode of the fourth PMOS transistor, a source electrode coupled to the voltage source, and a gate electrode coupled to the drain electrode of the fourth PMOS transistor; andthe second loading circuit comprises: a fourth NMOS transistor having a drain electrode coupled to the fourth output end and a source electrode coupled to ground; anda fifth NMOS transistor having a drain electrode coupled to the third output end and a gate electrode of the fourth NMOS transistor, a source electrode coupled to ground, and a gate electrode coupled to the drain electrode of the fourth NMOS transistor.

12. A delay unit for use in a voltage control oscillator, comprising: a first voltage control oscillating circuit; anda second voltage control oscillating circuit coupled to the first voltage control oscillating circuit and complementary to the first voltage control oscillating circuit.

13. The delay unit according to claim 12 wherein the first voltage control oscillating circuit comprises: a first gain circuit coupled to a first input end, a second input end, a first output end and a second output end; a first current-source circuit coupled to the first gain circuit; anda first load circuit coupled to the first output end and the second output end; anda second voltage control oscillator circuit, comprising: a second gain circuit coupled to a third input end, a fourth input end, a third output end and a fourth output end, the third input end, the fourth input end, the third output end and the fourth output end being coupled to the first input end, the second input end, the first output end and the second output end, respectively;a second current-source circuit coupled to the second gain circuit; anda second load circuit coupled to the third output end and the fourth output end;wherein each pair of the first and second gain circuits, the first and second current-source circuits and the first and second load circuits are implemented with complementary integrated circuits.

14. The delay unit according to claim 12 wherein the first and second gain circuits are coupled to each other.

15. The delay unit according to claim 12 wherein the first and second load circuits are coupled to each other, and selected from cross-coupled load circuits, diode load circuits, symmetric load circuits or voltage control resistor load circuits.