Patent Application
20070238437
The drawing includes the following Figures, which are not necessarily drawn to scale:
a and 2b show diagrams of the Universal Mobile Telecommunications System (UMTS) packet network architecture, which is also known in the art.
In particular, the overall technique according to the present invention may be implemented, by way of example, as follows:
The host processor 14 may have a clock request pin to indicate when it is in the deep-sleep (i.e. the main clock is not running).
Similarly, the WLAN chipset 12 may have a corresponding pin that is connected to and receives a deep-sleep signal from the host processor 14 so that the WLAN chipset 12 knows when it can wake up the host processor 14 or not. The clock request pin of the host processor 14 and the corresponding pin of the WLAN chipset 12 may form part of the coupling of these elements by the line 13. The WLAN chipset 12 may also have an internal threshold timer, such as element 22 in
In operation, the present invention would operate as follows:
If the WLAN chipset 12 detects via, for example, a wired connector (e.g. the line 13) that the host processor 14 is in a deep-sleep, then the WLAN chipset 12 will not deliver any packets to the host processor 14 until one of the following conditions is met:
a) the receive RX delay timer, such as element 22 has expired,
b) the buffer module 20 of the WLAN chipset 12 starts to run out of memory or its buffering threshold, or
c) the host processor 14 happens to wake-up before the RX delay timer, such as 22, has been expired.
The WLAN host processor may also have provisions to allow some type of API for controlling the time-out values and an ability to turn the feature off if needed.
In effect, the basic idea is to delay a packet received via the WLAN for a certain amount of time or until the host processor is woken up as in most cases (pretty much in all cases) packets sent in an idle mode don't have small latency requirements.
The following are two examples of the basic implementation:
Time 0 ms: The WLAN chipset 12 may receive a broadcast packet from the network or other device (not shown), but it also detects that the host processor 14 is in a deep-sleep so it decides not to pass the packet up just yet.
Time 300 ms: The WLAN chipset receives another broadcast packet, but as the host processor 14 is still in the deep sleep it decides to buffer this packet as well.
Time 800 ms: The WLAN chipset internal timer 22 has been fired and it decides to wake up the host processor 14 by raising an interrupt pin and thus it gets to deliver the packet to the host processor 14.
Time 0 ms: The WLAN chipset 12 receives a broadcast packet from the network or other device (not shown) but it also detects that the host processor 14 is in a deep-sleep so it decides not to pass the packet up just yet.
Time 200 ms: The host processor 14 is woken up by some internal timer, such as that shown in
Time 200.001 ms: The WLAN chipset 12 has detected that the host processor 14 has woken up (e.g. via the signal exchange along line 13) and it raises a receive (RX) interrupt and thus delivers the packet to the host processor 14.
By way of example, and consistent with that described herein, the functionality of the modules 24 may be implemented using hardware, software, firmware, or a combination thereof, although the scope of the invention is not intended to be limited to any particular embodiment thereof. In a typical software implementation, the module 12 and 22 would be one or more microprocessor-based architectures having a microprocessor, a random access memory (RAM), a read only memory (ROM), input/output devices and control, data and address buses connecting the same. A person skilled in the art would be able to program such a microprocessor-based implementation to perform the functionality described herein without undue experimentation. The scope of the invention is not intended to be limited to any particular implementation using technology now known or later developed in the future. Moreover, the scope of the invention is intended to include the module 24 being a stand alone module, as shown, or in the combination with other circuitry for implementing another module.
The other chipset modules 26 may also include other modules, circuits, devices that do not form part of the underlying invention per se. The functionality of the other modules, circuits, device that do not form part of the underlying invention are known in the art and are not described in detail herein.
Alternatively,
The present invention allows significant power-savings in a mobile device using WLAN by providing a technique for the WLAN subsystem to optimize how it wakes up a sleeping host processor or system. The technique is particularly aimed at reducing the penalty that processing the broadcast/multicast and keep-alive traffic causes in the host processor by forcing the host processor to wake up from a deep-sleep. The optimization is carried out by delaying the wake-up until the host processor needs to do so for some other event and thus allowing synchronization of the two different events into single wake-up and that way allowing the host processor to have no penalty of stochastic and keep-alive receive events.
The present invention may also take the form of the WLAN chipset 12 for a node, point, terminal or device in a wireless local area network (WLAN) or other suitable network, that may include a number of integrated circuits designed to perform one or more related functions. For example, one chipset may provide the basic functions of a modem while another provides the CPU functions for a computer. Newer chipsets generally include functions provided by two or more older chipsets. In some cases, older chipsets that required two or more physical chips can be replaced with a chipset on one chip. The term “chipset” is also intended to include the core functionality of a motherboard in such a node, point, terminal or device.
One advantage of the present invention is that it allows the overall system of the WLAN enable device 10 to save power by synchronizing the wake-up of the host processor with the rest of the overall system. By way of example, the power-saving impact may be quantified as following:
In the basic mobile application processor platform, the host processor such as 14 consumes around 40-80 mA of current when being not idled. When it goes into a deep-sleep, the current consumption is minimal (say, for example, about 0.2 mA).
When the host processor wakes up to do something, it typically goes back to sleep in around 50-200 ms. So one event every second would cause between 2-16 mA of base current consumption. If the WLAN network sends broadcast/multicast data in enterprise (or home environment having UPnP) environment (PCs to a lot of this) twice in every second and on top of this various applications are receiving keep-alive messages, then one could assume that the host processor gets woken up around every 300-400 ms, resulting in about 6-48 mA of base current consumption.
Being able to wake up only once a second for all the received packets would drop the power-consumption down to about 2-16 mA and if one assumes that that something else wakes up the system every few seconds, then the penalty of WLAN power-consumption can be even less as the WLAN packets can be processed when the host processor is up for some other activities. The average current (assuming other background activity) would probably be around 6 mA with the mentioned network traffic. A saving of about 14 mA would result in normal phone around 150 extra standby hours.
This feature provides good power-saving capabilities in the current processor architecture.
Accordingly, the invention comprises the features of construction, combination of elements, and arrangement of parts which will be exemplified in the construction hereinafter set forth.
It will thus be seen that the objects set forth above, and those made apparent from the preceding description, are efficiently attained and, since certain changes may be made in the above construction without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawing shall be interpreted as illustrative and not in a limiting sense.
