Dj. Zrilic, U.S. Pat. No. 5,349,353, Date of patent: Sep. 20, 1994
Dj. Zrilic, U.S. Pat. No. 6,285,306 B1, Date of Patent: Sep. 4, 2001
These research results are not sponsored by Government grants.
Individual project of Dr. Djuro G. Zrilic
1. Field of the Invention
The present invention relates to the direct processing of delta sigma modulated (DSM) and linear delta modulated (LDM) pulse streams. The sensing signal (analog input signal) is first converted into a one-bit high density (oversampled) pulse stream using DSM or LDM oversampled analog-to-digital converter. To implement a particular linear or nonlinear function, dedicated circuits have to be developed. Thus, the field of this invention is a pulse signal processing of one-bit non-positional delta modulated stream. It belongs to a wider class of digital signal processing (DSP) in the electrical engineering field.
2. Description of the Prior Art
The conventional method of DSP of a DSM pulse stream is achieved by using a decimation technique to interface with existing n-bit DSP hardware. Existing n-bit DSP hardware is bulky, power consuming, and prone to errors. Typical DSP hardware consists of a micro-processor and supporting n-bit communication lines with centralized control and synchronization. This hardware is not suitable for sub-micron technology because n-bit processors are hierarchical systems (every bit is weighted), and when the most significant bit (MSB), or sign bit is in error, a catastrophic malfunction can happen. To take advantage of the non-positional nature of a DSM pulse stream, there were several attempts to develop circuits for linear processing of a DSM pulse stream.
The earliest publications on the use of DSM in signal processing comes from Lockhart [1]. Digital filter coefficients are made of resistive networks. A similar idea is used by Lockhart and Babary [2] to implement an infinite impulse response (IIR) filter using a recalculating shift register. In both publications resistors are used to add filter coefficients.
Publications of Peled and Liu [3], [4] use ordinary DSP hardware to implement delta-modulated based digital filters. The implementation of filter coefficients is achieved using read-only memory (ROM).
In 1978 Lagoyannis [5] proposed a new method for multiplying delta-modulated signals by a constant. He implemented a digital circuit for direct multiplication of a delta modulated sequence.
In 1978, Locicero et al. [6] proposed a method for direct processing of adaptive delta-modulated (ADM) signals. By operating on the serial DM bit streams, sum, difference and product can be obtained in PCM and DM format. An arithmetic processor uses ordinary DSP hardware.
In the period 1978-1985 Kouvaras published number of papers related to linear processing of a delta-modulated stream. In reference [7] Kouvaras proposed a new method with which is possible to find a delta-modulated signal of the half sum of two analog signals through direct operation of their delta-modulated form. He proposed hardware implementation of a delta adder and did error analysis of the proposed circuit. In reference [8] Kouvaras proposes a digital circuit for doubling the amplitude of a delta modulated signal. In fact, by using a delta doubler, it is possible to overcome the problem of attenuation of one-half which the delta adder introduces [7]. In reference [9] Kouvaras proposed several circuits for the direct multiplication of delta-modulated signals by constants. In addition to a non-recursive form, Kouvaras proposed a recursive form of multiplier. In reference [10] Kouvaras proposed a new modular multi-input network for direct arithmetic operation on DM signals. In reference [11] Kouvaras proposed a technique for the reduction of the quantization noise in the direct processing of a DM pulse stream. In reference [12] Kouvaras proposed the modular network for the direct addition of DM signals with minimum quantization noise.
Lagoyannis and Pekmestzi proposed multipliers of two DM sequences [13]. These multipliers provide the product in DM sequence form. These multipliers were used in the implementation of a parallel type of digital correlator.
In reference [14] Zrilic et al. proposed the implementation of a ternary delta adder and ternary delta multiplier for the implementation of digital filters. In reference [15] Freedman and Zrilic proposed a new algorithm for linear and non-linear processing of a DM pulse stream. In reference [16] Zrilic proposed a number of circuits for linear, nonlinear and direct processing of a DM pulse stream. In his patents (U.S. Pat. No. 5,349,353 and U.S. Pat. No. 6,285,306 B1), Zrilic disclosed the number of circuits for linear, nonlinear and mixed processing of a DSM pulse stream.
In reference [17] Wong and Gray present two methods for building FIR filters based on single-loop and two-stage DSM encoding. These filters do not require multipliers.
Horianoupulos et al. [18] proposed a design technique for hardware reduction in delta modulated FIR filters. This method takes advantage of the special characteristics of DM filters in order to reduce noise.
Johns and Lewis [19] designed and analyzed delta-sigma filters by eliminating all multi-bit multipliers through the use of re-modulating internal filter states.
The present invention introduces a number of novel circuits for direct processing of DSM pulse stream. It is based on linear, nonlinear and mixed analog/digital processing using mainly digital circuitry. The present invention includes:
It is therefore a primary objective of the present invention to provide a number of circuits necessary for DSP of DSM pulse streams.
It is another objective of the present invention to provide simple and reliable circuits which will significantly enhance applications of DSM signal processing in different application areas.
It is still another objective of the present invention to reduce power consumption of DSM processing elements in applications where power consumption is a critical factor.
It is still a future objective of the present invention to provide a simple and inexpensive VLSI design.
It is still a future objective to design the system on a chip (SoC) which includes multiplexed sensors array, DSM ADC and newly proposed circuitry for functional processing of DSM pulse stream.
Linear circuit networks are networks where linear network laws can be applied (addition, subtraction, multiplication by a constant, superposition, etc.). Nonlinear circuits are theoretical and implementation-specific and one is not able to apply linear network theory to these circuits; the same holds for mixed circuits.
Ten block diagrams of circuits are presented; herein shall be presented the best mode contemplated by the inventor.
As can be amply seen from the drawings, every circuit presents an independent invention. Thus, it is necessary to describe every invention separately.
A full embodiment of the circuit for squaring a DSM pulse stream Xn is shown in
Input analog signal x(t) is converted by means of DSM (1) into digital pulse stream Xn and fed directly into an XOR gate (3). Signal Xn is delayed by one clock period of DSM, Xn-1, and delivered to the second input of XOR gate (3). After demodulation (4, LPF) a squared input waveform is obtained. Relevant waveforms of operations are shown in
In
The invention in
When DSM is used as an A/D converter, then any of the circuits for direct processing of DSM pulse stream can be used if needed. In particular, in low frequency applications such as environmental monitoring, seismic, bio-medical applications, control, instrumentation, etc., low-pass DSM is a well established A/D conversion procedure. Furthermore, DSM is low power consuming and dedicated circuits operate directly on a serial pulse stream. Only one wire is needed for internal and external connections and the use of one bit communication lines increases readability and reduces cost of the system. This is a significant advantage compared to existing 8 or 16 bit DSP hardware. Hardware and operation of circuitry are very simple and special manuals or software is not needed to operate circuits. Only data sheets with operating conditions and pin-out are needed. Eventual debugging is much simpler and faster compared to n-bit DSP hardware. VLSI is not a problem because of digital circuits' simplicity and the wide tolerance of DSM to component imperfections (±5%). In addition, because of the one bit (non-weighted) nature of the DSM stream, DSM DSP is not sensitive to catastrophic malfunctions as ordinary DSP. For example, if errors happen at the most significant or sign bit in an ordinary DSP system, then the system is out of order. This is not the case with a one bit processor because demodulation (DAC) is performed by a moving average filter. The main attributes of a DSM DSP system are high resolution of DSM ADC (24-bit), high signal-to-noise ratio and dynamic range (over 100 dB), low power consumption and the possibility of direct arithmetic operation on a DSM pulse stream. Thus, it will be appreciated by those skilled in the art that the present invention is not restricted to the particular preferred embodiments described with reference to the drawings, and that variations may be made therein without departing from the scope of the present invention as defined in the appended claims and equivalents thereof. The same circuitry can be employed for the direct processing of band-pass DSM (BPDSM).
1. GORGON B. LOCHART, Digital Encoding and Filtering Using Delta Modulation, The Radio and Electronic Engineer, Vol. 42, No. 12, December 1972, pp. 547-551.
2. G. B. LOCHART, S. P. BABARY, Binary Transversal Filters Using Recirculating Shift Registers, The Radio and Electronic Engineer, Vol. 43, No. 3, March 1873, pp. 224-226.
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6. JOSEPH L. LOCICERO, DONALD L. SCHILING, JOSEPH GARODNICK, Realization of ADM Arithmetic Signal Processors, IEEE Transaction on Communications, Vol. COM-27, No. 8, August 1979, pp. 1247-1254.
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13. D. LAGOYANNIS, K. PEKMETZI, Multipliers of Delta-Sigma Sequences, The Radio and Electronic Engineer, Vol. 51, No. 6, June 1981, pp. 281-286.
14. DJ. ZRILIC, K. ZANGI, A. MAVRETIC, M. FREEDMAN, Realization of Digital Filters for Delta-Modulated Signals, 30th Midwest Symposium on Circuits and Systems, Syracuse University, Aug. 16-18, 1987.
15. M. FREEDMAN, DJ. ZRILIC, Nonlinear Arithmetic Operations on the Delta Sigma Pulse Stream, Signal Processing, Vol. 21, 1990, pp. 25-35.
16. D. G. ZRILIC, Circuits and Systems Based on Delta Modulation (Book), Springer, 2005, ISBN 3-540-23751-8.
17. PING WAH WONG, ROBERT M. GRAY, FIR Filters with Sigma-Delta Modulation Encoding, IEEE Transaction on Acoustic Speech and Signal Processing, Vol. 18, No. 6, June 1990, pp. 979-990.
18. S. HORIANOPOULOS, V. ANASRASSOPOULOS, T. DELIYANNIS, Design Technique for Hardware Reduction in Delta Modulation FIR filters, Int. J. Electronics, 1991, Vol. 71, No. 1, pp. 93-106.
19. DAVID A. JOHNS, DAVID M. LEWIS, Design and Analysis of Delta-Sigma Based IIR Filters, IEEE Transaction on Circuits and Systems-II Analog and Digital Signal Processing, Vol. 40, No. 4, April 1993.