Patent Application
20100073207
This disclosure relates generally to signal processing and, more particularly, to delta-sigma analog-to-digital converters and methods to calibrate delta-sigma analog-to-digital converters.
There are many types of analog-to-digital converters (ADC) that convert a continuous time signal (i.e., an analog signal) into a digital signal (i.e., a representation of a signal using discrete numbers). One type of ADC is a delta-sigma ADC, which generally oversamples the continuous signal by an oversampling ratio. The delta-sigma ADC implements a negative feedback path using a digital-to-analog converter (DAC), which together with a high gain in forward path shapes quantization noise out of the baseband. Then, a digital filter following the delta-sigma ADC removes the undesired higher frequencies, thereby substantially reducing the quantization noise. However, the overall linearity of a delta-sigma ADC directly depends on the linearity of the DAC in the feedback loop, since the output of the DAC feeds back right at the input of the overall loop.
Delta-sigma analog-to-digital converters (ADCs) and methods to calibrate delta-sigma ADCs are disclosed. In one particular example, a delta-sigma ADC is described, including an n-bit feedback digital-to-analog converter (DAC) having a number of unit elements, is configured to provide a feedback signal to a summing device, which is configured to generate a difference signal based on an analog input signal and the feedback signal. An n-bit ADC is also included to generate an n-bit digital signal based on the difference signal. A dynamic element matching device selects one or more unit elements in the DAC based on the n-bit digital signal. A storage device, such as a memory, stores error coefficients corresponding to the plurality of unit elements. Finally, a digital corrector is included to receive the selection of unit elements, to receive the error coefficients corresponding to the selected unit elements, and to adjust the n-bit digital signal based on the received error coefficients.
Delta-sigma analog-to-digital converters (ADC) and methods to calibrate the same are disclosed herein. In some examples, a high-resolution delta-sigma ADC implements dynamic element matching techniques and digital correction for low power, broadband operation. Although the example methods and apparatus described herein generally relate to high-resolution broadband ADCs, the disclosure is not limited to such. On the contrary, the teachings of this disclosure may be applied in any electronics device that would benefit from noise correction.
Example delta-sigma ADCs and methods to calibrate the same are disclosed. As described herein, the example low power delta-sigma ADCs having a low oversampling ratio, generally eight or less, and implements both dynamic element matching techniques and digital correction. Prior to this disclosure, it was impractical to implement dynamic element techniques into delta-sigma ADCs that have an oversampling ratio of eight or less without sacrificing noise performance. In addition, the digital correction implements an error correction technique that has a resolution lower than the resolution of the example delta-sigma ADC, thereby requiring significantly less time to calibrate. Prior to this disclosure, digital correction required a high-resolution calibration that was impractical to implement in high volume manufacturing processes. The disclosed example calibration technique has a lower resolution than the delta-sigma ADC, thereby making such a calibration simple to implement in high volume testing processes of the example delta-sigma ADCs.
However, the DAC 102 generally has errors associated with its operation. In the n-bit DAC 102, the unit elements 104 are generally implemented by capacitors or current sources associated with each code of the n-bit DAC 102. The unit elements 104 are implemented to convert a digital signal into an analog signal that substantially represents the digital signal. Thus, the n-bit DAC has 2n unit elements 104 to allow the n-bit DAC 102 to represent 2n different voltage levels representative of the 2n codes. Generally, the n-bit DAC 102 receives an n-bit digital signal and actuates the appropriate unit elements 104, which generates the correct output voltage. The output of the n-bit DAC 102 is the sum of the voltages of the actuated unit elements 104, which forms the feedback analog signal that substantially represents the n-bit digital signal.
In semiconductor processes to manufacture integrated circuits, such as the delta-sigma ADC 100, the unit elements 104 may vary slightly in value (e.g., capacitance, current). As a result, the output voltage of the DAC unit elements 104 may vary due to the unit element mismatches. This leads to non-linearity in the feedback n-bit DAC 102 which directly translates as non-linearity of delta-sigma ADC 100. In
One method to improve the performance of the feedback path of a delta-sigma ADC is to use dynamic element matching techniques, which improve the linearity performance of the ADC at the cost of increased noise.
There are different techniques to implement DEM logic. DEM techniques will always increase the noise in the device due to mismatches in unit elements, which are caused by limits in unit element matching that can be achieved in integrated circuit processes. The amount of noise degradation depends on the DEM technique used, as well as the level of unit element matching achieved. Techniques differ on how to select DAC elements 206 for a given code from the n-bit ADC 210. Random selection of unit elements 206 provides the best linearity but results in poorer noise performance. Tones in the spectrum are converted to white noise, which is directly proportional to mismatch in the unit elements 206. A technique called data weighted averaging (DWA) provides a first-order shaping of mismatch noise, thus improving noise performance. Noise introduced by DWA algorithms is also directly proportional to mismatch in the unit elements 206 to an extent that reducing unit element 206 mismatch by 50% provides a 6 dB reduction in noise. The DWA technique works very well for high oversampling ratios (e.g., >8), but when using low oversampling ratios (e.g., 4-8) the noise performance of the ADC 200 is limited by mismatch-induced noise.
Another method of improving the DAC in the feedback path of a delta-sigma ADC is to digitally correct for errors introduced by the DAC.
The error coefficients measured by the calibration ADC 306 and stored in the digital corrector 308 must have a resolution of at least the overall resolution of the delta-sigma ADC 300. This leads to a significant increase in word length of the signal feeding a digital decimation filter 312 and, thus, increasing the complexity of the delta-sigma ADC 300. Further, calibrating to the resolution of the delta-sigma ADC 300 may need a long calibration time. The calibrating ADC 306 must have a linearity of at least the overall delta-sigma ADC 300 linearity. For example, if the calibrating ADC 306 has a resolution of k bits, the calibrating ADC 306 calibrates to a resolution of m bits by taking an average of 22(m-k) measurements of the n-bit DAC 302 output voltages and using the average to calculate the error coefficients. Thus, calibration time is exponentially related to the calibration accuracy. If the calibration is done one time during manufacturing, increased accuracy will lead to significantly increased test times. To set up calibration, the n-bit DAC 302 is disconnected from the n-bit sub ADC 310 and a subtractor 314 by opening switches 316 and 318, and connected to the k-bit ADC 306 and the n-bit counter 309 by closing switches 320 and 322.
As discussed in connection with
In the illustrated example, the delta-sigma ADC 400 is calibrated during, for example, manufacturing. An example calibration system 450 is coupled to the example delta-sigma ADC 400 to calibrate the same. The example calibration system 450 includes a control device 452 that is coupled to the n-bit DAC 406. The n-bit DAC 406 is also coupled to a buffer 454, which is further coupled to a k-bit calibration ADC 456. The calibration ADC 456 is coupled to the memory device 416 to store error coefficients therein. During calibration, the n-bit DAC 406 is decoupled from the remainder of the delta-sigma ADC 400 as shown via switches 458 and 460, the n-bit DAC 406 is coupled to the buffer 454 via a switch 462, and the unit selector 452 is coupled to the n-bit DAC 406 via a switch 464. In contrast, during normal operation (as shown below in
During manufacturing, the example calibration system 450 measures the error coefficients of the unit elements 407 and stores the results in the memory 416.
After measuring the value di of each unit element 407 at block 502, the example process 500 determines the mean value u of the unit elements 407 (block 504). In the illustrated example, because the actual value of the each unit element 407 is not known, the error is thus determined by the difference the mean value u and measured values di. Thus, after determining the mean value u of the unit elements 407, the example process 500 calculates the error of each of the unit elements 407 based on the mean value of the unit elements (block 506). The error coefficient Ei for each unit element 407 is obtained by dividing the error value by the mean value u as shown in Equation 1:
After computing the error coefficients Ei of the unit elements 407, the example process 500 stores the resulting error coefficients Ei in the memory device 416, for example (block 508). The example process 500 ends after the error coefficients Ei are stored in the memory device 416.
In the example of
The resulting analog signal is conveyed to a loop filter 408 which amplifies and integrates the analog signal, thereby shifting noise from lower frequencies to higher frequencies. The loop filter 408 conveys the integrated analog signal to an n-bit sub ADC 410, which generates a digital signal having n-bits of resolution (e.g., 3-5 bits). Traditionally, the delta-sigma ADC 400 samples the analog signal at a rate much greater than the highest frequency of interest (e.g., an OSR of 8). In the illustrated example, the delta-sigma ADC 400 is generally configured to have a large bandwidth (e.g., 5 megahertz) and an oversampling ratio of eight. Due to the large bandwidth of the delta-sigma ADC 400, the example delta-sigma ADC 410 typically has an oversampling ratio of eight or less.
The n-bit digital signal is conveyed from the ADC 410 to a dynamic element matching (DEM) device 412 to form a negative feedback path. The DEM device 412 is coupled to the n-bit DAC 406 and shapes the unit element mismatch noise to higher frequencies outside the frequency band of interest. That is, the n-bit DAC 406 receives the digital signal from the DEM device 412 and, in response, forms the second analog signal. However, the DEM device 412 selects the unit elements 407 of the n-bit DAC 406 to be actuated according to DEM techniques (e.g., DWA), which thereby transfers noise introduced by the n-bit DAC 406 from lower frequencies to higher frequencies.
More particularly, the DEM device 412 is configured to shape the mismatch noise associated with the unit elements 407 of the n-bit DAC 406. As described above, one method to remove errors associated with the unit elements 407 of the n-bit DAC 406 is to perform dynamic element matching techniques using data weighted averaging, for example. Data weighted averaging generally implements a high pass transfer function that shifts the noise introduced by the unit elements 407 of the n-bit DAC 406 from lower to higher frequencies. The noise is shifted to higher out-of-band frequencies that are removed by the digital decimation filter 418. To perform data weighted averaging, the DEM device 412 is configured to cause the n-bit DAC 406 to rotate through its unit elements 407 (i.e., the capacitors in the n-bit DAC 406) such that each unit element 407 is used substantially the same number of times. In other words, the DEM device 412 configures the n-bit DAC 406 so that each unit element 407 is used substantially equally, thereby averaging the errors of the unit elements 407.
At the outset, the example DEM 412 receives a first code 702, which is three. In response, the example DEM 412 actuates the corresponding unit elements 407 of the n-bit DAC 406 to output a voltage that is substantially representative of three. Of course, the unit elements 407 may have mismatch errors and, as a result, the voltage output by the n-bit DAC 406 may vary for each selected unit element 407. Initially, there the example DEM 412 has a pointer of zero and, thus, the example DEM 412 selects and actuates the first, second, and third unit elements 407. In addition, the example DEM 412 determines the pointer is three.
In response a second code 704, which is four, the example DEM 412 selects the fourth, fifth, sixth, and seventh unit elements 407 and determines the pointer to be seven. In response to a third code 706, which is six, the example DEM 412 selects the eighth unit element 407. Of course, to output a voltage substantially representative of six, the example DEM 412 rotates back to the first unit element, thereby selecting the first through the fifth unit elements 407. In the example of
As described above, the n-bit sub ADC 410 also conveys the digital signal to a digital corrector 414 coupled to a memory device 416. As described above, the unit elements 407 of the n-bit DAC 406 are not precisely equal to each other. As a result, the voltage output by the unit elements 407 may differ, thereby causing the feedback analog signal formed by the n-bit DAC 406 to have both distortion and noise. The digital corrector 414 corrects for the mismatch errors in the unit elements 407 by, for example, subtracting error coefficients that are stored in the memory 416 from the digital signal. However, as described above, the DEM device 412 causes the n-bit DAC 406 to rotate through its different unit elements 407 and the digital corrector 414 itself is unable to determine which of the unit elements 407 are selected in the n-bit DAC 406. Thus, to determine the errors of the selected unit elements 407, the digital corrector 414 receives an information signal (e.g., a pointer P) from the DEM device 412 indicative of the offset to determine the selected unit elements 407 in combination with the digital code C.
Thus, in the illustrated example, the digital corrector 414 thereby corrects for errors as a result of unit element 407 mismatches within the n-bit DAC 406. However, at the same time, the digital corrector 414 also corrects for mismatch noise introduced by the unit elements 407. In particular, the mismatches of the unit elements 407 cause mismatch noise, which are introduced during dynamic element matching and the digital corrector 414 calibrates out (i.e., removes) the mismatch noise by correcting for the mismatches in the unit elements 407.
The digital corrector 414 conveys the resulting discrete signal to a digital decimation filter 418 that filters out high frequency content of the discrete signal by any suitable method. In the illustrated example, the digital decimation filter 418 reduces the number of samples, thereby removing high frequency content from the discrete signal. As a result, the combined operation of the loop filter 408 and the n-bit DAC 406 shape the quantization noise generated by the n-bit sub ADC 410 out of the baseband. The DEM device 412 improves the linearity performance of the n-bit DAC 406 while utilizing data weighted averaging techniques to shape mismatch noise out of the baseband. Finally, the digital decimation filter 418 removes quantization and mismatch noise from the out-of-band frequencies of the discrete signal. The output of the digital decimation filter 418 is conveyed to an m-bit output 420 of the delta-sigma ADC 400 to interface with other devices and/or circuits.
Although certain example methods and apparatus are described herein, other implementations are possible. The scope of coverage of this patent is not limited to the specific examples described herein. On the contrary, this patent covers all methods and apparatus falling within the scope of the invention.
