Delta V.sub.BE bias current reference circuit

Abstract

A bias current reference circuit is disclosed having a first diode-connected bipolar device connected in series with an MOS device to develop a reference voltage which is proportional to a bias current. The reference voltage is used by an MOS device connected in series with a resistor which is connected in series with a second diode-connected bipolar device to develop a reference current which is proportional to the difference in the base to emitter voltages of the two bipolar devices. The reference current is used by a diode-connected MOS device to develop a bias voltage which is proportional to the reference current. The bias voltage in turn is used by another MOS device to develop the bias current in proportion to the bias voltage. The bias voltage is also used by other MOS devices to provide similar bias currents. In the disclosed embodiment, such a bias current can be used by a diode-connected CMOS device to develop a complementary bias voltage.

Description

TECHNICAL FIELD

This invention relates generally to reference circuits and, more particularly, to a circuit which provides reference voltages for .DELTA.V.sub.BE bias current generators and the like.

BACKGROUND ART

A convenient voltage reference standard by which bias currents may be established is the V.sub.BE of a transistor as noted in U.S. Pat. No. 4,342,926 entitled "Bias Current Reference Circuit". In such circuits, the base-emitter voltage V.sub.BE of a transistor is reflected across a resistor, R, to provide a reference current. However, reference circuits which provide a current that is proportional to the ratio of V.sub.BE /R are susceptible to process and temperature variations. The voltage V.sub.BE has a negative temperature coefficient and the resistance R has a positive temperature coefficient. Therefore, as the temperature rises, V.sub.BE decreases and R increases thereby causing the reference current to have a relatively strong temperature dependence.

BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved bias current reference circuit.

Another object of the present invention is to provide an MOS bias current reference circuit which generates a bias voltage which is substantially supply voltage and process independent, using the .DELTA.V.sub.BE of two bipolar transistors.

Yet another object of the present invention is to provide an improved .DELTA.V.sub.BE bias current reference circuit which is substantially less sensitive to temperature variation than circuits of the prior art.

In carrying out the above and other objects and advantages of the present invention, there is provided, in one form, a voltage reference device which establishes a reference voltage in response to a control current directed therethrough. A voltage mirror coupled to the voltage reference device reflects the reference voltage as a control voltage coupled to a current reference portion comprising a current reference device and a resistor. The current reference portion provides a reference current which is proportional to the .DELTA.V.sub.BE of the voltage reference and current reference devices. A current mirror coupled to the current reference device directs a control current proportional to the reference current through the voltage reference device.

The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING

The single FIGURE illustrates in schematic form a bias current reference circuit constructed in accordance with the preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Shown in the single drawing is a bias current reference circuit 10 constructed in accordance with the preferred embodiment of the present invention. Reference circuit 10 is comprised generally of a reference voltage portion 12, a reference current portion 14, a bias voltage portion16 and a bias current portion 18. In reference voltage portion 12, an NPN bipolar transistor 20 has the base and collector thereof connected to a positive supply voltage, V.sub.DD, and the emitter thereof connected to the source of a P-channel MOS transistor 22. Transistor 22 has the gate and drain thereof connected together and to reference current portion 14 and bias current portion 18. In this configuration, a reference voltage, V.sub.REF, with respect to positive supply voltage V.sub.DD, is developed on the gate of transistor 22. Reference voltage, V.sub.REF, is the sum of the base-emitter voltage, V.sub.BE, of diode-connected transistor 20 and the gate-source voltage, V.sub.GS, of diode-connected transistor 22. The V.sub.GS of transistor 22 is proportional to a bias current I.sub.1 directed therethrough by bias current portion 18.

In reference current portion 14, an NPN bipolar transistor 24 has the base and collector thereof connected to positive supply voltage, V.sub.DD, and the emitter thereof connected to a first terminal of a resistor 26. A second terminal of resistor 26 is connected to the source of a P-channel MOS transistor 28 which has the gate thereof connected to the gate and drain of transistor 22, and the drain thereof connected to bias voltage portion 16. Transistor 28 is constructed with a channel width to channel length ratio such that transistors 22 and 28 have the same channel currentdensity. Therefore, the gate-source voltage V.sub.GS of transistor 28 is substantially the same as that of transistor 22. Applying Kirchoff's voltage law to the loop comprising transistors 20, 22, 24 and 28 and resistor 26, results in the equation:

V.sub.BE20 -V.sub.BE24 -.DELTA.V.sub.BE =0. Thus the difference in the base-emitter voltages, .DELTA.V.sub.BE, will be reflected across resistor 26. Reference current portion 14 therefore provides a reference current I.sub.2 which is proportional to reference voltage V.sub.REF provided by reference voltage portion 12.

In bias voltage portion 16, an N-channel MOS transistor 30 has the source thereof connected to a negative supply voltage, V.sub.SS, and the gate anddrain thereof connected to the drain of transistor 28 of reference current portion 14. In this configuration, the diode-connected transistor 30 will develop a gate-source voltage, V.sub.GS, which is proportional to the reference current, I.sub.2. The voltage at the gate of transistor 30 is suitable for biasing other N-channel MOS transistors used as constant biascurrent sinks.

In bias current portion 18, an N-channel MOS transistor 32 has the source thereof connected to negative supply voltage V.sub.SS, the gate thereof connected to the gate and drain of transistor 30, and the drain thereof connected to the gate and drain of transistor 22. In this configuration, transistor 32 will allow a bias current I.sub.1, proportional to a bias voltage which is the V.sub.GS of transistor 30, to flow through transistors 20 and 22 of reference voltage portion 12.

In operation, a shift at the emitters of transistors 20 and 24 caused by a shift in positive supply voltage V.sub.DD relative to negative supply voltage V.sub.SS, will be reflected by transistors 22 and 28 as a corresponding shift in the voltage at each terminal of resistor 26. However, the voltage across resistor 26 remains constant. Therefore, the current provided by resistor 26 will remain constant even when V.sub.DD shifts, provided the temperature is constant. So long as the current provided by resistor 26 is constant, the V.sub.GS of transistor 30 tends to remain constant relative to V.sub.SS, even in the presence of significant shifts in V.sub.SS, provided the temperature is constant. Thusthe bias voltage V.sub.GS, of transistor 30, although referenced to the .DELTA.V.sub.BE of transistors 20 and 24, remains substantially independent of shifts in supply voltages V.sub.DD and V.sub.SS.

A shift in temperature will similarly have substantially little effect on bias current I.sub.2. Bias current I.sub.2 can be expressed as:

I.sub.2 =(.DELTA.V.sub.BE)/(R.sub.26) where it can be readily shown that .DELTA.V.sub.BE =[(kT)/(q)].times.ln [(I.sub.20 /I.sub.24).times.(A.sub.24 /A.sub.20)] where, k=Boltzman's constant; q=electrical charge in Coulombs; T=temperature in degrees Centigrade; A.sub.20 =the emitter junction area of transistor 20; A.sub.24 =the emitter junction area of transistor 24; I.sub.20 =the current through transistor 20; and I.sub.24 =the current through transistor 24. The conventionally known temperature coefficient of .DELTA.V.sub.BE is approximately +3400 ppm/.degree.C. and the temperature coefficient of resistor 26 is approximately +1300 ppm/.degree.C. Therefore, the temperature coefficient of reference current I.sub.2 is approximately +2100 ppm/.degree.C. or 0.0021%/.degree.C. This temperature coefficient compares to approximately 0.0047%/.degree.C. for a V.sub.BE bias current reference. A V.sub.BE reference generator has poorer temperature stabilitybecause the temperature coefficient of V.sub.BE is approximately -3400 ppm/.degree.C., and as temperature increases, V.sub.BE decreases and R increases causing the reference current to change noticeably. However, fora .DELTA.V.sub.BE reference, .DELTA.V.sub.BE increases and R increases so that the variation of reference current is much less.

In some applications, it may be desirable to provide a P-channel bias voltage V.sub.PB, as a counterpart for the N-channel bias voltage V.sub.NB. In the illustrated embodiment, this is accomplished using a second bias current portion 18' and a second bias voltage portion 16'. In second bias current portion 18', an N-channel MOS transistor 34 has the source thereof connected to negative supply voltage V.sub.SS, the gate thereof connected to the gate and drain of the transistor 30 of the bias voltage portion 16 and to the drain of transistor 28, and the drain thereof connected to second bias voltage portion 16'. In second bias voltage portion 16', a P-channel MOS transistor 36 has the gate and drain thereof connected to the drain of transistor 34, and the source thereof connected to positive supply voltage V.sub.DD. In this configuration, transistor 34 will allow a bias current I.sub.3, proportional to the N-channel bias voltage V.sub.NB, to flow through transistor 36. In response to bias current I.sub.3, diode-connected transistor 36 develops agate-source voltage V.sub.GS which is proportional to bias current I.sub.3,but referenced to the positive supply voltage V.sub.DD rather than the negative supply voltage V.sub. SS. This voltage, indicated as V.sub.PB, issuitable for biasing other P-channel MOS transistors used as constant current sources. If reference circuit 10 is embodied in an integrated form, transistors 20 and 24 may be readily fabricated using conventional MOS fabrication processes.

Upon initial application of power, bias current reference circuit 10 may assume either an inactive or an active state. For example, if no current flows through reference voltage portion 12 during power up, no reference voltage will be developed for application to reference current portion 14.Thus, no reference current will be provided by reference current portion 14. Without reference current, bias voltage portion 16 will be unable to establish bias voltage V.sub.NB and enable bias current portion 18 to direct bias current through reference voltage portion 12. Therefore, bias current reference circuit 10 will remain in an inactive state. To prevent the possibility of an inactive state, a conventional start-up circuit (notshown) is required to allow start-up current to flow through reference voltage portion 12 when P-channel bias voltage V.sub.PB is less than a predetermined threshold.

While specific N-channel and P-channel MOS devices are shown, it should be clear that bias current reference circuit 10 could be implemented by completely reversing the processing techniques (e.g. P-channel to N-channel) or by using other types of transistors. Further, while the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.

Claims

1. A .DELTA.V.sub.BE bias current reference circuit comprising:

reference voltage means comprising a first bipolar transistor, for providing a reference voltage proportional to a bias current;

reference current means coupled to the reference voltage means comprising a second bipolar transistor coupled in series with a resistor, for providing a reference current proportional to the ratio of the difference in the base to emitter voltages, .DELTA.V.sub.BE, of said first and second bipolar transistors and the resistance of said resistor;

bias voltage means coupled to the reference current means, for providing a bias voltage proportional to said reference current; and

bias current means coupled to both the reference voltage means and the bias voltage means, for providing the bias current proportional to the bias voltage for said reference voltage means.

2. The .DELTA.V.sub.BE bias current reference circuit of claim 1 wherein the first bipolar transistor is diode-connected and coupled in series with a diode-connected first MOS transistor, said first MOS transistor developing said reference voltage on the gate thereof.

3. The .DELTA.V.sub.BE bias current reference circuit of claim 1 or 2 wherein said second bipolar transistor is diode-connected, and said resistor is coupled in series with a second MOS transistor having said reference voltage coupled to the gate thereof.

4. The .DELTA.V.sub.BE bias current reference circuit of claim 1 or 2 wherein the bias voltage means comprises a diode-connected third MOS transistor having said reference current coupled thereto, said third MOS transistor developing the bias voltage on the gate thereof.

5. The .DELTA.V.sub.BE bias current reference circuit of claim 1 or 2 wherein the bias current means comprises a fourth MOS transistor having the bias voltage coupled to the gate thereof, said fourth MOS transistor providing the bias current for the reference voltage means.

6. The .DELTA.V.sub.BE bias current reference circuit of claim 1 or 2 further comprising:

second bias current means coupled to the bias voltage means, for providing a second bias current which is proportional to the bias voltage.

7. The .DELTA.V.sub.BE bias current reference circuit of claim 6 wherein the second bias current means comprises a fifth MOS transistor having the bias voltage coupled to the gate thereof, said fifth MOS transistor providing said second bias current.

8. The .DELTA.V.sub.BE bias current reference circuit of claim 6 further comprising:

second bias voltage means coupled to said second bias current means, for providing a second bias voltage proportional to the second bias current.

9. The .DELTA.V.sub.BE bias current reference circuit of claim 8 wherein said second bias voltage means comprises a diode-connected sixth MOS transistor having the second bias current coupled thereto, said sixth MOS transistor developing the second bias voltage on the gate thereof.

10. A CMOS .DELTA.V.sub.BE bias current reference circuit comprising:

a first bipolar transistor having the base and collector thereof coupled to a supply voltage of a first polarity;

a first MOS transistor of a first conductivity type having the source thereof coupled to the emitter of the first bipolar transistor;

a second MOS transistor of said first conductivity type having the gate thereof coupled to the gate of said first MOS transistor;

a resistor having a first terminal, and a second terminal coupled to the source of said second MOS transistor;

a second bipolar transistor having the emitter thereof coupled to the first terminal of said resistor, and the base and collector thereof coupled to said supply voltage of the first polarity;

a third MOS transistor of a second conductivity type having the source thereof coupled to a supply voltage of a second polarity, and the gate and drain thereof coupled to the drain of the second MOS transistor; and

a fourth MOS transistor of said second conductivity type having the source thereof coupled to said supply voltage of the second polarity, the gate thereof coupled to the gate and drain of said third MOS transistor, and the drain thereof coupled to the gate and drain of said first MOS transistor.

11. The CMOS .DELTA.V .sub.BE bias current reference circuit of claim 10 further comprising:

a fifth MOS transistor of said second conductivity type having the source thereof coupled to said supply voltage of the second polarity, and the gate thereof coupled to the gate and drain of said third MOS transistor; and

a sixth MOS transistor of said first conductivity type having the source thereof coupled to said supply voltage of the first polarity, and the gate and drain thereof coupled to the drain of said fifth MOS transistor.