Demodulation circuit and demodulating method

Abstract

A demodulation circuit can perform a capturing operation although afrequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is ablock diagram of the QPSK demodulation circuit;

FIG. 2 shows the configuration of a timing recovery loop;

FIGS. 3A and 3B are explanatory views of the operation of the phase comparator;

FIGS. 4A and 4B show the output of the loop filter;

FIG. 5 shows the value of a limiter;

FIG. 6 shows the configuration of a carrier recovery loop;

FIG. 7 shows signal points of an I and Q phase plane;

FIG. 8 shows the configuration of the carrier recovery loop according to the first embodiment of the present invention;

FIG. 9 shows the configuration of a phase comparator according to the first embodiment of the present invention;

FIG. 10 shows the configuration of a limiter;

FIG. 11 is a flowchart for explanation of the capturing operation;

FIGS. 12A and 12B show a change in value of an integrator;

FIGS. 13A and 13B are explanatory views of the capturing operation;

FIG. 14 shows the configuration of the timing recovery loop according to the second embodiment of the present invention; and

FIG. 15 shows the configuration of the phase comparator according to the second embodiment of the present invention.

Claims

1. A demodulation circuit which demodulates a received signal, comprising: a carrier wave regeneration loop performing control such that a phase error for a carrier wave can be minimized in tracing the carrier wave;a phase error determination circuit which is included in the carrier wave regeneration loop, determines advance or delay of a phase relative to the carrier wave, and determines as a phase advance when a phase advance or delay cannot be discriminated; anda loop filter, which is included in the carrier wave regeneration loop, integrates the determination result of the phase advance or delay, and shifts the integrated value to a maximum integrated value on a phase-delay determined side when the integrated value reaches a maximum integrated value on a phase-advance determined side.

2. The circuit according to claim 1, wherein the loop filter includes a limiter for outputting a maximum integrated value on the phase-delay determined side as the integrated value when the integrated value of a determination result of the phase error determination circuit reaches the maximum integrated value on the phase-advance determined side.

3. The circuit according to claim 1, wherein the phase error determination circuit outputs a predetermined value other than 0 when a signal point on the I and Q phase plane of the carrier wave is on a predetermined line or in a predetermined area.

4. The circuit according to claim 1, wherein the phase error determination circuit outputs a predetermined value other than 0 when a signal point on the I and Q phase plane of the carrier wave is on a line of Q=1 or Q=−I.

5. A demodulation circuit which demodulates a received signal, comprising: a carrier wave regeneration loop performing control such that a phase error for a carrier wave can be minimized in tracing the carrier wave;a phase error determination circuit which is included in the carrier wave regeneration loop and determines advance or delay of a phase relative to the carrier wave, and determines as a phase delay when a phase advance or delay cannot be discriminated; anda loop filter, which is included in the carrier wave regeneration loop, integrates the determination result of the phase advance or delay, and shifts the integrated value to a maximum integrated value on a phase-advance determined side when the integrated value reaches a maximum integrated value on a phase-delay determined side.

6. The circuit according to claim 5, wherein the loop filter includes a limiter for outputting a maximum integrated value on the phase-advance determined side as the integrated value when the integrated value of a determination result of the phase error determination circuit reaches the maximum integrated value on the phase-delay determined side.

7. The circuit according to claim 5, wherein the phase error determination circuit outputs a predetermined value other than 0 when a signal point on the I and Q phase plane of the carrier wave is on a predetermined line or in a predetermined area.

8. A demodulation circuit which demodulates a received signal, comprising: a clock regeneration loop performing control such that a phase error for a symbol timing can be minimized in allowing a clock to trace the symbol timing of a received signal;a phase error determination circuit which is included in the clock regeneration loop, determines advance or delay of a phase relative to the symbol timing, and determines as a phase advance when a phase advance or delay cannot be discriminated; anda loop filter, which is included in the clock regeneration loop, integrates the determination result of the phase advance or delay, and shifts the integrated value to a maximum integrated value on a phase-delay determined side when the integrated value reaches a maximum integrated value on a phase-advance determined side.

9. The circuit according to claim 8, wherein the loop filter includes a limiter for outputting a maximum integrated value on the phase-delay determined side as the integrated value when the integrated value of a determination result of the phase error determination circuit reaches the maximum integrated value on the phase-advance determined side.

10. The circuit according to claim 8, wherein when the carrier wave is sampled using a predetermined sampling clock, the phase error determination circuit determines whether a value of each sampling point indicates a monotonous increase or a monotonous decrease, and outputs a predetermined value other than 0 when the value does not indicate a monotonous increase or a monotonous decrease.

11. A demodulation circuit which demodulates a received signal, comprising: a clock regeneration loop performing control such that a phase error for a symbol timing can be minimized in allowing a clock to trace the symbol timing of a received signal;a phase error determination circuit which is included in the clock regeneration loop, determines advance or delay of a phase relative to the symbol timing, and determines as a phase delay when a phase advance or delay cannot be discriminated; anda loop filter, which is included in the clock regeneration loop, integrates the determination result of the phase advance or delay, and shifts the integrated value to a maximum integrated value on a phase-advance determined side when the integrated value reaches a maximum integrated value on a phase-delay determined side.

12. The circuit according to claim 11, wherein the loop filter includes a limiter for outputting a maximum integrated value on the phase-advance determined side as the integrated value when the integrated value of a determination result of the phase error determination circuit reaches the maximum integrated value on the phase-delay determined side.

13. The circuit according to claim 11, wherein when the carrier wave is sampled using a predetermined sampling clock, the phase error determination circuit determines whether a value of each sampling point indicates a monotonous increase or a monotonous decrease, and outputs a predetermined value other than 0 when the value does not indicate a monotonous increase or a monotonous decrease.

14. The circuit according to claim 13, wherein the phase error determination circuit comprises: a tilt determination circuit for determining whether values of at least three sampling points indicate monotonous increase or monotonous decrease when the carrier wave is sampled at a predetermined sampling clock; and a selection circuit for outputting a predetermined value other than 0 when the tilt determination circuit determines that monotonous increase or monotonous decrease is not indicated, and outputting a value obtained from the values of the three sampling points as a determination result of a phase error when monotonous increase or monotonous decrease is determined.

15. A method for demodulating a received signal, comprising: determining a phase advance or delay for a carrier wave, and determining as a phase advance when a phase advance or delay cannot be discriminated;integrating a determination result of a phase advance or delay, and shifting the integrated value to amaximum integrated value on a phase-delay determined side when the integrated value reaches a maximum integrated value on a phase-advance determined side; andperforming carrier wave regeneration control such that a phase error for the carrier wave can be minimized based on the integrated value.

16. The method according to claim 15, wherein when the carrier wave is sampled using a predetermined sampling clock, it is determined whether a value of each sampling point indicates a monotonous increase or a monotonous decrease, and a predetermined value other than 0 is output when the value does not indicate a monotonous increase or a monotonous decrease.

17. A method for demodulating a received signal, comprising: determining a phase advance or delay for a carrier wave, and determining as a phase delay when a phase advance or delay cannot be discriminated;integrating a determination result of a phase advance or delay, and shifting the integrated value to amaximum integrated value on a phase-advance determined side when the integrated value reaches a maximum integrated value on a phase-delay determined side; andperforming carrier wave regeneration control such that a phase error for the carrier wave can be minimized based on the integrated value.