Demodulation method and apparatus

Abstract
A demodulation circuit and method are provided. The demodulation circuit includes a transformation circuit which is configured to transform the received signal into a modified signal representation in which both amplitude-varying information and frequency-varying information are converted to a uniform representation; and a processing circuit which is configured to process the modified signal representation to demodulate the received signal based on the uniform representation. The method includes transforming the signal into a modified signal representation in which both amplitude-varying information and frequency-varying information are converted to a uniform representation; and processing the modified signal representation to demodulate the signal based on the uniform representation.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawing figures, wherein:



FIG. 1 is a schematic block diagram of a receiver for receiving a wireless communications signal according to an exemplary embodiment of the present invention;



FIGS. 2A-2C are schematic illustrations of FSK, ASK and poor quality FSK signals, respectively, in a complex baseband coordinate space;



FIGS. 3A-3C are schematic illustrations showing use of an offset reference origin to represent the signal components of FIGS. 2A-2C, respectively in a uniform representation;



FIGS. 4A-4C are schematic illustrations showing use of a threshold to discriminate between the different signal components using the uniform signal representations of FIGS. 3A-3C, respectively;



FIG. 5 is a block diagram of the initialisation section of the demodulator of the receiver of FIG. 1;



FIG. 6 is a schematic illustration showing a basis on which an initial value of the threshold of FIGS. 4A-4C may be calculated;



FIG. 7 is a schematic block diagram of a decision making section of the demodulator of the receiver of FIG. 1; and



FIGS. 8A-8C are schematic illustrations showing generation of the demodulated output signals based on the threshold illustrated in FIGS. 4A-4C, respectively.


Claims
  • 1. A demodulator circuit for demodulating a received signal, the demodulator circuit comprising: a transformation circuit which is configured to transform the received signal into a modified signal representation in which both amplitude-varying information and frequency-varying information are converted to a uniform representation; anda processing circuit which is configured to process the modified signal representation to demodulate the received signal based on the uniform representation.
  • 2. The demodulator circuit according to claim 1, wherein the received signal comprises a complex baseband representation of the received signal, and the transformation circuit is configured to apply a transform such that the amplitude-varying information and the frequency-varying information are converted into a uniform representation in complex baseband space.
  • 3. The demodulator circuit according to claim 2, wherein the transform comprises a shift transform to shift a signal value with respect to an offset reference origin.
  • 4. The demodulator circuit according to claim 3, further comprising a basis-shift calculation circuit which is configured to calculate a basis-shift parameter representing the shift transform from an original origin to the offset reference origin.
  • 5. The demodulator circuit according to claim 4, wherein the basis-shift parameter is a shift vector in complex baseband space.
  • 6. The demodulator circuit according to claim 4, wherein the basis-shift calculation circuit is configured to calculate the basis-shift parameter such that the offset reference origin is proximate to a signal component of the received signal.
  • 7. The demodulator circuit according to claim 6, wherein the offset reference origin is determined to substantially coincide with said signal component of the received signal.
  • 8. The demodulator circuit according to claim 6, wherein said signal component is a first signal component of a message represented as a plurality of alternately changing signal components.
  • 9. The demodulator circuit according to claim 4, wherein the basis-shift calculation circuit is configured to update the basis-shift parameter to match changes in said signal component, and to suspend updating when another signal component is present.
  • 10. The demodulator circuit according to claim 1, further comprising a signal conditioning circuit positioned upstream of the transformation circuit, the signal conditioning circuit being configured to convert the received signal into a complex baseband representation.
  • 11. The demodulator circuit according to claim 3, wherein the processing circuit is configured to discriminate a plurality of signal components according to a relative proximity of the signal components to the offset reference origin.
  • 12. The demodulator circuit according to claim 11, wherein the processing circuit further comprises: a modulus calculation circuit which is configured to calculate a vector length of the signal value with respect to the offset reference origin in complex baseband space; anda comparator circuit which is configured to compare the vector length with a proximity threshold.
  • 13. The demodulator circuit according to claim 12, further comprising a proximity threshold calculation circuit which is configured to perform an adaptive calculation of the proximity threshold based on a weighted average of signal component values.
  • 14. The demodulator circuit according to claim 13, further comprising an initial value calculation circuit which is configured to calculate an initial value of the proximity threshold.
  • 15. The demodulator circuit according to claim 14, wherein the initial value calculation circuit calculates the initial value of the proximity threshold according to an equation: sin(π*Δf/band)*(modulus(basis-shift))wherein Δf denotes a frequency shift of FSK frequency components on either side of a carrier frequency, and band denotes a parameter based on a sampling frequency.
  • 16. A demodulator circuit for demodulating a received signal, the demodulator circuit comprising: a complex baseband processing circuit which is configured to process the received signal in a complex baseband representation; anda discrimination circuit which is configured to process the complex baseband representation of the received signal to discriminate a plurality of signal components therein according to a amplitude and frequency variation of the signal components.
  • 17. A receiver for receiving a signal, the receiver comprising the demodulator circuit as defined in claim 1.
  • 18. A receiver for receiving a signal, the receiver comprising a demodulator circuit as defined in claim 16.
  • 19. A method of demodulating a signal, the method comprising: transforming the signal into a modified signal representation in which both amplitude-varying information and frequency-varying information are converted to a uniform representation; andprocessing the modified signal representation to demodulate the signal based on the uniform representation.
  • 20. The method according to claim 19, further comprising storing the demodulated signal in a storage medium.
  • 21. A method of demodulating a signal, the method comprising: processing the signal in a complex baseband representation; andprocessing the complex baseband representation of the signal to discriminate a plurality of signal components according to a combination of amplitude and frequency variation.
  • 22. The method according to claim 21, further comprising storing the discriminated signal in a storage medium.
  • 23. A computer readable storage medium storing an executable algorithm, which when executed on a processor performs the method as defined by claim 19.
  • 24. A computer readable storage medium storing an executable algorithm, which when executed on a processor performs the method as defined by claim 21.
  • 25. The computer readable storage medium according to claim 23, wherein the computer readable storage medium comprises a semiconductor memory.
  • 26. The computer readable storage medium according to claim 24, wherein the computer readable storage medium comprises a semiconductor memory.
Priority Claims (1)
Number Date Country Kind
0602852 Mar 2006 FR national