Patent Application
20230320223
Embodiments of the present disclosure generally relate to piezoelectric devices. More specifically, embodiments disclosed herein relate to piezoelectric devices and methods of depositing films for piezoelectric devices.
In semiconductor processing, physical vapor deposition (PVD) (e.g., sputtering) is used for transfer of material at the atomic level to deposit thin films or coatings on a substrate. During PVD, a target having a source material is bombarded with ions generated from a plasma within a processing chamber. The bombardment of the target causes the source material to be sputtered (e.g., ejected) from the target towards the substrate being processed. In some examples, the sputtered source material may be accelerated towards the substrate by application of a voltage bias. Upon reaching the surface of the substrate, the source material may react with another material of the substrate to form a thin film or coating thereon.
PVD processes can be utilized to form thin film piezoelectric materials, which are materials that accumulate electric charge upon application of mechanical stress. Piezoelectric materials are frequently used in sensors and transducers for devices such as gyro-sensors, ink-jet printer heads, and other microelectromechanical systems (MEMS) devices, including acoustic resonators for mobile phones and other wireless electronics. Relaxor ferroelectrics, and particularly, relaxor-PT materials, are a type of piezoelectric material exhibiting exceptionally high piezoelectricity due to their unique free energy landscape. In order to realize these exceptional piezoelectric properties, relaxor-PT films must be grown with a uniform perovskite phase structure and <001> crystal orientation (e.g., (001) or (002) orientation). However, growing such relaxor-PT type materials with conventional PVD processes is extremely complex due to the narrow growth window associated with the <001> orientation, as well as the material undergoing various phase transformations with even the slightest change in stoichiometry and/or temperature.
Accordingly, what is needed in the art are improved piezoelectric device stacks and methods of forming piezoelectric device stacks via PVD.
The present disclosure generally relates to piezoelectric devices. More specifically, embodiments disclosed herein relate to piezoelectric devices and methods of depositing films for piezoelectric devices.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the Figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
The present disclosure generally relates to piezoelectric devices. More specifically, embodiments disclosed herein relate to piezoelectric devices and methods of depositing films for piezoelectric devices.
Conventionally, large-scale deposition of thin metal films has been challenging due to non-uniformities of the thin metal films from center to edge thereof. During deposition processes involving sputtering (e.g., physical vapor deposition or “PVD”), differences in the arrangement of atoms in the film layers on the substrate may result in cone defects, stacking defects, and other surface defects being formed in subsequently deposited film layers. For piezoelectric device stacks, such defects may result in weakened piezoelectric coupling and suboptimal piezoelectric properties of the resulting device.
An improvement in deposited thin film properties can be achieved in various types of deposited films, such as piezoelectric materials, through the methods disclosed herein. The methods disclosed herein enable deposition of seed and template film layers having improved thickness and crystal orientation uniformity, which may be studied using X-ray diffraction (XRD) techniques. In certain examples, an ultra-thin seed layer having a uniform thickness from center to edge thereof is deposited on a substrate. In certain examples, a template layer closely matching the crystal structure of a subsequently formed piezoelectric material layer is deposited on a substrate. The improved uniformity in orientation and thickness for these layers, in turn, facilitates the growth of piezoelectric materials thereon with improved crystallinity and hence, excellent piezoelectric properties.
The cluster tool 100 includes a factory interface 104, loading dock 140, first transfer chamber 124, and second transfer chamber 128. A plurality of cassettes 112, or front opening unified pods (“FOUPs”), are disposed on the factory interface 104 and are configured to receive a plurality of substrates (shown in
The first transfer chamber 124 is part of a main frame 172 and houses a centrally disposed first transfer robot 132. The first transfer robot 132 is configured to move the substrates 201 between the loading dock 140 and a plurality of first processing chambers 160 (160a-d are shown in
Each loading dock 140 is selectively isolated from the first transfer chamber 124 by slit valves and from the interior region 116 of the factory interface 104 by vacuum doors (not shown). In this configuration, the factory interface robots 120 in the factory interface 104 are configured to move a substrate 201 from a cassette 112 to the loading dock 140, which may be sealed and pumped down to a desired pressure for transfer of the substrates 201 to the first transfer chamber 124. Upon reaching a desired pressure, the substrate 201 can then be accessed by the first transfer robot 132 through a slit valve opening (not shown) formed between the first transfer chamber 124 and the loading dock 140.
The first processing chambers 160 may include any suitable type of processing chambers for forming thin layer film stacks on the substrates 201. In certain embodiments, one or more of the first processing chambers 160 include orient chambers disposed proximate the loading dock 140 and used to align the substrates 201 in a desired rotational orientation within the cluster tool 100. In some embodiments, the orient chambers may include a heat source, such as lamps or infrared generating radiant heaters, adapted to heat the substrate 201 to a desired temperature. The orient chambers can further be pressurized under a vacuum condition to ensure that any undesirable water or other contamination is removed from the surface of the substrates 201 prior to processing in other downstream chambers.
In some embodiments, the first processing chambers 160 further include one or more pre-clean chambers that are adapted to clean the surfaces of the substrates 201. The pre-clean chambers may clean the surfaces of the substrates 201 by use of a cleaning process that includes exposing the surfaces of the substrates 201 to a radio frequency (RF) generated plasma and/or one or more pre-cleaning gas compositions that includes a carrier gas (e.g., Ar, He, Kr) and/or a reactive gas (e.g., hydrogen). In some embodiments, the pre-clean chambers are adapted to perform a process that may include a non-selective sputter etching process.
In certain embodiments, one or more of the first processing chambers 160 are configured to process substrates 201 therein by cooling the substrates 201, heating the substrates 201, etching the substrates 201, and/or depositing one or more layers on surfaces of the substrates 201. In certain embodiments, the deposition processes may include a sputter deposition process (i.e., PVD deposition process). In certain configurations, one or more of the processing chambers 160 are further configured to anneal the substrates 201.
The first transfer chamber 124 and the second transfer chamber 128 are coupled to each other via the pass-through chambers 162. In some configurations, the first transfer chamber 124 may be vacuum pumped to a moderately low pressure, for example, less than about 1 milliTorr (mTorr). The second transfer chamber 128 may be pumped to a lower pressure, for example, 1 microTorr or less. Accordingly, the first and second transfer chambers 124, 128 are maintained at least at a moderate vacuum level to prevent the transfer of contamination between the transfer chambers 124, 128 and other modules of the cluster tool 100.
Similar to the first transfer chamber 124, the second transfer chamber 128 is part of the main frame 172 and houses a centrally disposed second transfer robot 136. The second transfer robot 136 is configured to move the substrates 201 between each of a plurality of second processing chambers 170 and/or the pass-through chambers 162. The second transfer chamber 128 can be selectively isolated from each of the second processing chambers 170 and the pass-through chambers 162 by use of slit valves (not shown) that are disposed between each second processing chamber 170 and pass-through chamber 162 and the second transfer chamber 128.
In certain embodiments, one or more of the second processing chambers 170 are configured to process substrates 201 therein by cooling the substrates 201, heating the substrates 201, etching the substrates 201, and/or depositing one or more layers on surfaces of the substrates 201. In certain embodiments, the deposition processes may include a sputter deposition process (i.e., PVD deposition process). In certain configurations, one or more of the second processing chambers 170 are further configured to anneal the substrates 201.
As shown in
The target 210 is connected to a power supply 212, such as a DC power supply, a RF power supply, an AC power supply, a pulsed DC power supply, or a pulsed RF power supply, via a target switch 226. During deposition processes, the target 210 may be negatively biased via the pulsed DC power supply providing a pulsed DC power. A sputter gas flow controller 218, such as a mass flow control (MFC) device, is disposed between a sputter gas source 214 and the process volume 202 to control a flow of the sputter gas from the sputter gas source 214 to the process volume 202. A reactive gas flow controller 220, such as an MFC device, is disposed between a reactive gas source 216 and the process volume 202 to control a flow of the reactive gas from the reactive gas source 216 to the process volume 202.
The pedestal 204 is connected to a pedestal switch 230 that when engaged connects the pedestal 204 to a power supply 234, such as a DC power supply, a RF power supply, an AC power supply, a pulsed DC power supply, and a pulsed RF power supply. During deposition processes, the pedestal 204 may be negatively biased via the power supply 234 providing a RF power. In certain embodiments, the processing chamber 200 is operable to independently bias the target 210 and the pedestal 204. A controller 207 is coupled to the processing chamber 200 and is configured to control aspects of the processing chamber 200, for example connecting the target switch 226 and connecting the pedestal switch 230, during processing.
The substrate 201, in some examples, is a 200 mm silicon (Si) substrate having a crystal orientation of <001> (e.g., (001) or (002)). The substrate 201 may be formed from other metals having an appropriate lattice structure, including but not limited to a polycrystalline molybdenum (Mo), strontium ruthenium oxide (SrRuO3, SRO), lanthanum nickel oxide (LaNiO3, LNO), lanthanum strontium manganite (LaSrMnO3, LSMO), and calcium ruthenate (CaRuO3). In certain embodiments, a thermal oxide layer 302 is grown on a surface of the substrate 201, such as a Si or silicon oxide (SiOx) layer. For example, the thermal oxide layer 302 may be formed of silicon dioxide (SiO2). The thermal oxide layer 302 may have a thickness between about 10 nm and about 1000 nm, such as between about 15 nm and about 750 nm, for example, between about 20 nm and about 500 nm. In certain embodiments, the thermal oxide layer 302 has a thickness between about 25 nm and about 200 nm, such between about 50 nm and about 150 nm. For example, the thermal oxide layer 302 may have a thickness of between about 75 nm and about 125 nm, such as about 100 nm.
The first seed layer 304 may be formed directly on the surface of the substrate 201 or on a surface of the thermal oxide layer 302. The first seed layer 304 supports growth of the bottom electrode layer 306, which is deposited on a surface of the first seed layer 304 and may act as a bottom electrode for devices. Examples of suitable materials for the bottom electrode layer 306 include platinum (Pt), SrRuO3, LaNiO3, CaRuO3, LaSrMnO3, and the like. In certain examples, the first seed layer 304 is formed of a titanium oxide (TiOx) having an orientation of <001>(e.g., (001) or (002)), such as titanium dioxide (TiO2), and the bottom electrode layer 306 is formed of Pt having an orientation of <111>. A highly oriented Pt <111> layer is essential for forming a uniform second seed layer 308, which in turn supports formation of the piezoelectric material layer 312 with high orientation control. Accordingly, forming the first seed layer 304 of TiO2 may support the growth of a Pt bottom electrode layer 306 with exclusively <111> orientation.
Please note that the orientation of the bottom electrode layer 306, as well as seed layers 304, 308, can be detected and confirmed by X-ray diffraction (XRD) analysis, such as 2theta-omega scans, as well as cross-sectional high-resolution transmission electron microscopy (HRTEM). The inventors of the present disclosure have found that by utilizing the methods described herein, only peaks corresponding to the <111> orientation for the bottom electrode layer 306 can be detected with 2theta-omega scanning, and these peaks exhibit high intensities over 10,000 counts per second (cps). The results indicate that the bottom electrode layer 306, as well as the first seed layer 304, are highly oriented.
In certain embodiments, the first seed layer 304 has a thickness between about 10 nm and about 50 nm, such as between about 20 nm and about 30 nm, such as about 25 nm. In certain embodiments, the bottom electrode layer 306 has a thickness between about 50 nm and about 200 nm, such as between about 75 nm and about 175 nm, such as between about 100 nm and about 150 nm, for example, about 125 nm.
The second seed layer 308 is deposited upon the bottom electrode layer 306 and may be formed of any suitable ultra-thin metal film. In certain embodiments, the second seed layer 308 is formed of Pt or titanium (Ti). In certain embodiments, the second seed layer 308 is formed of the same or different material than the first seed layer 304. The second seed layer 308 has a uniform thickness between about 0.5 nm and about 5 nm, such as between about 1 nm and about 3 nm, which is confirmed by cross-sectional HRTEM. For example, the second seed layer 308 has a uniform thickness between about 1.5 nm and about 2.5 nm, such as about 2 nm. As described above, a thin and highly uniform seed layer enables uniformity in subsequent device layers and allows improved process integration.
The piezoelectric material layer 312 is deposited over the second seed layer 308 and is formed of any suitable piezoelectric materials. In certain embodiments, the piezoelectric material layer 312 is formed of one or more layers containing scandium-doped aluminum nitride (ScAIN) or AIN. In certain embodiments, the piezoelectric material layer 312 is formed of one or more layers containing any one of or a combination of titanium nitride (TiN), hafnium nitride (HfN), or silicon nitride (SixNy). In some examples, the piezoelectric material layer 312 is formed of a relaxor-lead titanate (PT) type material, such as lead magnesium niobate-lead titanate (PMN-PT) and lead indium niobate-lead magnesium niobate-lead titanate (PIN-PMN-PT). The piezoelectric material layer 312 may have a thickness between about 500 nm and about 2000 nm, such as between about 750 nm and about 1500 nm, such as about 1000 nm.
The top electrode layer 314 is deposited upon the piezoelectric material layer 312 and may act as a top electrode for finished devices. In certain examples, the top electrode layer 314 is formed of the same or different material than the bottom electrode layer 306. For example, the top electrode layer 314 may be formed of Pt having an orientation of <111>. In certain examples, the thickness of the top electrode layer 314 is between about 30 nm and about 200 nm, such as between about 50 nm and about 150, for example, about 100 nm.
Formation of the template layer 310 is beneficial when the piezoelectric material layer 312 is formed of relaxor-PT type piezoelectric materials, which are a class of complex oxide materials showing exceptionally high piezoelectricity due to a unique free energy landscape. These piezoelectric properties are enhanced when the relaxor-PT type material is formed with a <001> orientation. Thus, in examples where the piezoelectric material layer 312 is formed of relaxor-PT type piezoelectric materials, such as PMN-PT, the template layer 310 may be formed of a perovskite PZT film having an orientation of <001>. PZT has a crystal structure closely matching that of relaxor-PT type piezoelectric materials and thus, a PZT template layer 310 may lower the nucleation energy for growth of a relaxor-PT type piezoelectric material layer 312 with a <001> orientation thereon, resulting in heteroepitaxial, cube-on-cube type crystal growth. This type of growth provides improved crystallinity with a five-fold (e.g., 5×) increase in <001> peak intensity when analyzed by XRD, such as 2theta-omega scans. A greater XRD intensity is crucial for obtaining vastly improved piezoelectric properties. Moreover, as PZT itself is a piezoelectric material, increasing the thickness of the PZT template layer 310 will not adversely affect the electromechanical properties or response of the relaxor-PT type piezoelectric material layer 312. In some examples, the template layer 310 has a thickness between about 10 nm and about 200 nm, such as between about 25 nm and about 175 nm, between about 50 nm and about 150, between about 75 nm and about 125, such as about 100 nm.
At block 402, the substrate 201 is loaded into the cluster tool 100 and is pre-processed. The substrate 201 may or may not have a thermal oxide layer, such as thermal oxide layer 302, already formed thereon prior to loading into the cluster tool 100. In certain embodiments, the substrate is loaded into the loading dock 140 by one of the factory interface robots 120 and is then passed through the first transfer chamber 124 by the first transfer robot 132 to an orient chamber, a pre-clean chamber, and/or other first processing chamber 160. As described above, pressure (P) in the first transfer chamber 124 may be about 1 microTorr. Accordingly, the pressure of the cluster tool 100 is held in a vacuum state.
During pre-processing, the substrate 201 may be exposed to a degas process performed in one of the first processing chambers 160. Optionally, a surface of the substrate 201 is exposed to a plasma to pre-clean the surface of the substrate 201, which may occur before or after performing the degas process. For example, the surface of the substrate 201 can be pre-cleaned (e.g., bombarded with reactive gas (e.g., H2) or non-reactive gas (e.g., Ar, Ne, He) ions and/or gas radicals (e.g., etched)) in a pre-clean chamber prior to being transferred to another first or second processing chamber 160, 170 for deposition of the first seed layer 304. Pre-cleaning the surface of the substrate 201 prior to depositing the first seed layer 304 can reduce surface defects in the first seed layer 304 when the first seed layer 304 is deposited on the substrate 201. Other processes that may be performed during block 402 can also include heating, maintaining the incoming temperature of the substrate 201, or cooling the substrate 201. After pre-processing at block 402, the substrate 201 may be transferred to one or more processing chambers 160, 170, which may include the components shown in processing chamber 200, to form individual layers of the film stacks 300 or 301 thereon.
The first seed layer 304 is formed on the substrate 201 at block 404. In certain embodiments, the first seed layer 304 is formed on the substrate 201 by PVD and/or an anneal and oxidation process. For example, a thin and crystalline Ti film may be deposited by PVD at room temperature, followed by exposure of the Ti film to an anneal and oxidation process to form a TiO2 layer.
At block 406, the bottom electrode layer 306 is formed over the first seed layer 304 in one of the processing chambers 160, 170. For example, the bottom electrode layer 306 may be deposited on the first seed layer 304 via a PVD process performed in a PVD chamber, such as processing chamber 200. In certain embodiments, the PVD process is performed between about 37° C. and about 600° C., such as between about 400° C. and about 600° C., and such as about 500° C. In certain embodiments, the target in the PVD chamber is negatively biased during the PVD process by a pulsed or continuous power supply providing a DC power with a power level between about 400 W and about 1000 W, such as between about 600 W and about 800 W. In certain embodiments, which can be combined with other embodiments described herein, the flow rate of Ar during the PVD process is between about 20 sccm and about 60 sccm, such as between about 30 sccm and about 50 sccm, and the pressure within the PVD chamber is between about 4 mTorr and about 25 mTorr, such as between about 10 mTorr and about 20 mTorr.
As described above, in certain embodiments, the bottom electrode layer 306 is formed of Pt having an orientation of <111>, thus supporting the subsequent formation of a highly oriented piezoelectric material layer 312. In further embodiments, the Pt bottom electrode layer 306 is deposited on a TiO2 first seed layer 304.
At block 408, the second seed layer 308 is formed on the bottom electrode layer 306. Similar to the first seed layer 304, the second seed layer 308 may be formed by depositing a thin Ti layer via PVD at room temperature and then annealing the Ti layer to form a TiO2 layer. In other examples, the second seed layer 308 is formed with different materials and/or by a different process. The second seed layer 308 has a uniform thickness between about 0.5 nm and about 5 nm, such as between about 1 nm and about 3 nm, such as about 2 nm, and a uniform <001> orientation. A thin and highly uniform seed layer with conformal crystal orientation enables uniformity in subsequent device layers and facilitates formation of piezoelectric material layers with excellent piezoelectric properties.
The template layer 310 may then be optionally deposited on the second seed layer 308 at block 410, as depicted in film stack 301. The template layer, which may be formed of a perovskite PZT film having an orientation of <001>, is deposited via a PVD process at a temperature between about 500° C. and about 750° C., such as about 650° C., and a pressure between about 5 mTorr and about 25 mTorr, such as between about 18 mTorr and about 20 mTorr. In certain embodiments, the target in the PVD chamber is negatively biased during the PVD process by a pulsed or continuous power supply providing a RF power with a power level between about 1000 W and about 2500 W, such as between about 1200 W and about 2000 W. In certain embodiments, which can be combined with other embodiments described herein, the flow rate of Ar during the PVD process is between about 20 sccm and about 60 sccm, such as between about 30 sccm and about 50 sccm, and the flow rate of O2 is between about 0 sccm and about 20 sccm, such as between about 5 sccm and about 15 sccm.
The deposition process described above results in the template layer 310 having a uniform thickness ranging between about 10 nm and about 200 nm, such as between about 50 nm and about 150 nm, and such as about 100 nm. As previously described, the template layer 310 may be formed of piezoelectric materials having similar properties to the piezoelectric material layer 312, and thus, forming a thicker template layer 310 will not adversely affect the piezoelectric properties of the film stack.
At block 412, the piezoelectric material layer 312 is formed, for example, by a PVD process substantially similar to the process for forming the template layer 310. In certain embodiments, the target in the PVD chamber is negatively biased by a pulsed or continuous power supply providing a RF power with a power level between about 1000 W and about 2500 W, such as between about 1200 W and about 2000 W. In certain embodiments, which can be combined with other embodiments described herein, the flow rate of Ar during the PVD process is between about 20 sccm and about 60 sccm, such as between about 30 sccm and about 50 sccm, and the flow rate of O2 is between about 0 sccm and about 20 sccm, and such as between about 5 sccm and about 15 sccm.
In certain embodiments, the piezoelectric material layer 312 is formed directly on the second seed layer 308, which is depicted in film stack 300. In certain other embodiments, the piezoelectric material layer 312 is deposited over the template layer 310, as depicted in film stack 301. Formation of the piezoelectric material layer 312 over the template layer 310 is particularly beneficial when the piezoelectric material layer 312 is formed of a relaxor-PT type material, such as lead PMN-PT or PIN-PMN-PT. In such examples, the template layer 310 may be formed with a crystal structure closely matching that of the relaxor-PT type material, thus facilitating uniform heteroepitaxial growth of the piezoelectric material layer 312 with a <001> orientation and excellent piezoelectric properties.
Following the formation of the piezoelectric material layer 312, the top electrode layer 314 is formed over the film stack 300 or 301 at block 414. Similar to the bottom electrode layer 306, the top electrode layer 314 may be formed of Pt deposited over the piezoelectric material layer 312 via a PVD process performed at a temperature between about 300° C. and about 600° C., such as about 500° C. In certain embodiments, the target in the PVD chamber is negatively biased during the PVD process by a pulsed or continuous power supply providing a DC power with a power level between about 400 W and about 1000 W, and such as between about 600 W and about 800 W. In certain embodiments, which can be combined with other embodiments described herein, the flow rate of Ar during the PVD process is between about 20 sccm and about 60 sccm, such as between about 30 sccm and about 50 sccm, and the pressure within the PVD chamber is between about 4 mTorr and about 25 mTorr, such as between about 10 mTorr and about 20 mTorr.
After blocks 402-414 have been completed, and the film stack 300 or 301 is formed, the substrate 201 may be returned to the factory interface 104 via the first and/or second transfer robots 132, 136 and one of the factory interface robots 120.
An optional display unit 501 may be coupled to the controller 500. The controller 500 includes a processor 504, a memory 508, and support circuits 512 that are coupled to one another. The controller 500 may be on-board the cluster tool 100, or in an alternative example, the controller 500 may be on-board the processing chamber in
The display unit 501 includes an input control unit, such as power supplies, clocks, cache, input/output (I/O) circuits, coupled to the various components of the display unit 501 to facilitate control thereof. The processor 504 may be one of any form of general purpose microprocessor, or a general purpose central processing unit (CPU), each of which can be used in an industrial setting, such as a programmable logic controller (PLC).
The memory 508 includes at least one non-transitory computer readable medium and may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), or any other form of digital storage, local or remote. The memory 508 contains instructions, that when executed by the processor 504 (e.g., central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC)), facilitates the operation and processing within of any of the processing chambers illustrated in
In one example, the controller 500 may be implemented as the program product stored on a computer-readable storage media (e.g. 508) for use with a computer system (not shown). The program(s) of the program product define functions of the disclosure, described herein.
In summary, thin piezoelectric films having highly uniform thicknesses and crystal orientations may be formed though the methods disclosed herein. In certain examples, the highly-uniform piezoelectric films are facilitated by deposition of ultra-thin TiOx seed layers having uniform thicknesses from center to edge. In certain examples, the highly-uniform piezoelectric films are facilitated by deposition of PZT template layers closely matching the crystal structures of subsequently formed piezoelectric films. The increased uniformity of the piezoelectric films results excellent piezoelectric properties, thus enabling improved piezoelectric performance of the resulting devices.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2020/110838 | 8/24/2020 | WO |
