1. Field of the Invention
The present invention generally relates to a design structure for determining means, and more particularly, to a design structure for determining Internet access on a system on a chip.
2. Description of the Related Art
Conventional integrated circuits are increasingly relying on autonomous functions, or intellectual properties (IP's), provided on the integrated circuit. IP on an integrated circuit may also be referred to as an electronic circuit (EC). Each IP, or EC, may provide a separate function. Increasingly, enough IP's are being provided on to a single integrated circuit, that the resulting integrated circuit may be referred to a system on a chip (SOC). In a SOC, all conventional computer functions are found on one integrated circuit, including a central processing unit (CPU) and Internet access.
As more and more IP functions are being placed on the conventional integrated circuit, the likelihood increases that the manufacturer, designer, or programmer for each IP may be different. As more and more producers contribute a different IP to an integrated circuit, the different IP's become more autonomous. That is, the SOC or integrated circuit designer may rely on a third-party IP design to work properly because the integrated circuit designer cannot hope to account for the operations of each IP on the integrated circuit.
Furthermore, with each IP, it is more and more difficult for the integrated chip designer to completely understand, configure, customize, or program each IP. This difficulty would arise in part because each IP may be provided by a different designer and each IP provides a different function. Primarily, however, this difficulty would arise because a single conventional integrated circuit would have hundreds of different IP's placed on it.
Therefore, the SOC designer has to rely on each autonomous IP to be self-sufficient because the SOC designer cannot account for every IP on the SOC. In order to be more self-sufficient, conventional autonomous IP may require Internet access to become fully configured or to receive updates or commands. That is, conventional IP is becoming more and more “plug and play,” for their integrated circuit designers.
However a problem arises in that each IP cannot be designed with an Internet access protocol, structure, or hardware. Accordingly, a need arises for the conventional autonomous IP to determine and access the Internet without the expensive and unrealistic step for each IP to be configured to access the Internet.
In view of the foregoing, and other, exemplary problems, drawbacks, and disadvantages of the conventional systems, it is an exemplary feature of the present invention to include a method for determining Internet access by an autonomous electronic circuit on a system on a chip integrated circuit, the method including snooping on a system bus to determine if Internet activity is occurring on the system bus, collecting local header information when the snooping has determined that Internet activity is occurring on the system bus, creating a packet including the local header information, and requesting Internet access with the created packet.
It is another exemplary feature of the present invention to include a computer-readable medium storing a program for determining Internet access by an autonomous electronic circuit on a system on a chip integrated circuit, the method including snooping on a system bus to determine if Internet activity is occurring on the system bus, collecting local header information when the snooping has determined that Internet activity is occurring on the system bus, creating a packet including the local header information, and requesting Internet access with the created packet.
An additional benefit of the present invention would be to create a solution for how an autonomous piece of IP can connect to the Internet through an unknown Internet access port. In the future the Internet will become even more pervasive and time to market pressures keep increasing, IP will be placed on SOCs without the time to create a complete system.
Likewise, autonomous IP may need the ability to access their development source in order to obtain updates or other information. Thus, the present invention provides an autonomous piece of IP with a method to snoop the data bus and duplicate the data packet in order to send the information to an external Internet location.
An additional benefit of the present invention would be that autonomous IP have the ability to communicate over the Internet. In addition, the SOC designer is not required to devote time, energy, or resources to system setup. Another benefit is that there can be advanced help/problem correcting/status without system designer interaction.
The foregoing and other purposes, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
Referring now to the drawings, and more particularly to
Nonetheless, each of the autonomous EC's would exemplarily not be provided with Internet access or the systems, hardware, or design to independently or autonomously access the Internet. Nonetheless, each EC may require Internet access to function properly.
That is, exemplarily, at least one EC or IP on an exemplary system on a chip would have Internet access capabilities. However, because each of the other EC's may not be preprogrammed with the information of where Internet access is to be acquired on SOC 100, an exemplary method would be provided to each EC to find and acquire Internet access through system bus 105.
A piece of IP, that is XXth EC 150, is able to physically access the Internet. For example, XXth EC 150 may consist of both the upper layers and physical tools required for accessing the Internet. Exemplarily, a different device (such as second EC 120) can already be preconfigured to access the Internet by doing a bus write to XXth EC 150 with correct packet information for sending out an Internet request. As part of the packet, the sending EC will know its bus ID and include that bus ID in the packet so that return information can be sent back to the sending EC. This return information could be data, error codes or a completion response. XXth EC 150 would then take the packet and send the packet from the other EC out onto the Internet.
Step 210 would exemplarily snoop for an Internet header or other information indicating Internet access. Snooping would include accessing, inspecting, and monitoring system bus 105 of SOC 100, for example. After system bus 105 is accessed, the snooping would exemplarily include monitoring the activity on system bus 105. Exemplary Internet access information could include ASCII data such as: “www,” “http://,” HTML code, an internet protocol address (for example, 9.61.105.109), a transmission control protocol, a packet header, etc. Thus, in Step 210, the electronic traffic on system bus 105 would be monitored for signs of Internet activity.
Accordingly, Step 220 exemplarily determines whether such an electronic signature has been snooped or found. If no Internet access signature has been found by the snooping of Step 210, Step 210 is repeated.
After Internet activity has been snooped, Step 230 would identify the sender and receiver of the Internet activity. Exemplarily, a EC providing or having Internet access would be determined. For example, XXth EC 150 could be identified or first EC 110 (already being configured to access the Internet through XXth EC 150) would also be identified. Step 240 would exemplary check the header information of the Internet activity. Since the sender of the data packet could be either the Internet Access XXth EC 150 or another requesting EC (second EC 120, for example), an EC performing method 200 must decide to whom the information must be sent.
Step 250 would exemplarily form a packet for the EC or IP to access the Internet with. Then Step 260 would exemplarily determine to whom the packet should be sent. That is, in snooping the bus, method 200 would not necessarily be able to discern which of first EC 110 or XXth EC 150 is configured with Internet access capability. Therefore, method 200 would exemplarily decide to which of EC 110 or XXth EC 150 the packet should be sent.
The packet would exemplarily be sent in Step 270. Exemplarily, method 200 would put the packet on the data bus sending it to the selected EC. The selected EC being an EC having Internet access or being configured to access the Internet through another EC as identified in Step 230. That is, Step 260 may decide to send the packet to first EC 110 and the packet would be sent in Step 270.
After sending the packet, Step 280 waits for a response. Exemplarily, Step 280 would wait for a predetermined period of time. If a response is returned, Step 290 would be executed a link to the Internet is established. Because, in the present example, first EC 110 does not actually have its own Internet access, no response is returned.
If no response is returned during the predetermined period of time, Step 300 would exemplarily change the header information to another EC or IP determined to have Internet access. Alternatively, method 200 would simply return to Step 210 and resume snooping. Step 310 would exemplarily then send the packet to the newly selected EC or IP and similarly wait for a response. Thus, in the present example, the packet would then be sent to XXth EC 150.
Step 320 would likewise exemplarily wait for a response for a predetermined period of time. If a response is a returned, method 200 would establish a link in Step 330 or return to Step 210 to continue snooping.
In Step 290 and Step 330, the EC or IP would exemplarily begin communicating through the found EC's to the Internet. This communication would include any activity specified by the designer or programmer of the searching EC.
Referring to
Referring to
Exemplarily, method 200 may also wait for multiple packets from multiple EC's to determine the common target bus ID which should be the Internet access point. In addition, once an Internet access point on the system bus is determined, the present invention may also exemplarily memorize these locations for future access. In addition, the method should have the ability to send the packet through multiple levels of protocols.
Design process 510 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in
As with other design structure types described herein, netlist 580 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.
Design process 510 may include hardware and software modules for processing a variety of input data structure types including netlist 580. Such data structure types may reside, for example, within library elements 530 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 30 nm, etc.). The data structure types may further include design specifications 540, characterization data 550, verification data 560, design rules 570, and test data files 585 which may include input test patterns, output test results, and other testing information.
Design process 510 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 510 without deviating from the scope and spirit of the invention. Design process 510 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 510 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 520 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 590. Design structure 590 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures).
Similar to design structure 520, design structure 590 preferably includes one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in
Design structure 590 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GLI, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 590 may include information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in
In addition to the system described above, a different aspect of the invention includes a computer-implemented method for performing the above method. As an example, this method may be implemented in the particular environment discussed above.
Such a method may be implemented, for example, by operating the CPU 611 to execute a sequence of machine-readable instructions. These instructions may reside in various types of signal bearing media.
Thus, this aspect of the present invention is directed to a programmed product, including signal-bearing media tangibly embodying a program of machine-readable instructions executable by a digital data processor incorporating the CPU 611 and hardware above, to perform the method of the invention.
This signal-bearing media may include, for example, a RAM contained within the CPU 611, as represented by the fast-access storage for example. Alternatively, the instructions may be contained in another signal-bearing media, such as a magnetic data storage diskette 700 (
Whether contained in the computer server/CPU 611, or elsewhere, the instructions may be stored on a variety of machine-readable data storage media, such as DASD storage (e.g., a conventional “hard drive” or a RAID array), magnetic tape, electronic read-only memory (e.g., ROM, EPROM, or EEPROM), an optical storage device (e.g., CD-ROM, WORM, DVD, digital optical tape, etc.), paper “punch” cards, or other tangible signal-bearing media including transmission media such as digital and analog media, and tangible signal-bearing media for communication links and wireless communication. In an illustrative embodiment of the invention, the machine-readable instructions may include software object code, complied from a language such as “C” etc.
While the invention has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
Further, it is noted that, Applicants' intent is to encompass equivalents of all claim elements, even if amended later during prosecution.