Patent Application
20080059741
Like reference symbols in the various drawings indicate like elements.
In some implementations, the first group of circuits 102 and second group of circuits 104 include “standard” logic cells or elements, such as a logic cell 109. As shown, each standard logic cell (e.g., logic cell 109) includes certain standard resources, such as, for example, logic gates; memory elements (e.g., flip-flops); multiplexers; various interconnections for forming data paths; clock, reset, or other global signals; etc. Aspects of the cells can be standardized, for example, to facilitate efficient production of FPGA devices (field programmable gate array devices), PLDs (programmable logic devices) or ASIC devices (applications specific integrated circuits). By using standard logic cells in an FPGA, PLD or ASIC design, a hardware designer can take advantage of known electrical characteristics (e.g., propagation delays, capacitance, inductance, etc.) to reduce design times.
In some implementations, the standard logic cells are included in configurable logic blocks (CLBS) that, along with configurable routing channels, are included in an FPGA or PLD device. Various components of the CLBs can be selectively coupled together with the configurable routing channels to provide specific hardware functions that, for example, have been designed in a hardware description language or with a schematic capture tool, placed and routed within a specific FPGA or PLD architecture, and loaded into the FPGA or PLD device during a configuration process. In other implementations, the standard logic cells are included in design libraries of particular ASIC devices. Like CLBs in an FPGA or PLD device, the standard logic cells in an ASIC design library can be ultimately coupled together with various routing channels to provide specific hardware functions; however, ASIC devices are generally not as configurable as FPGA or PLD devices. The specific hardware functions implemented in ASIC devices can also be designed in a hardware description language or a schematic capture tool, simulated, placed and routed, and the design can be fabricated in a semiconductor fabrication process.
Whether implemented in FPGAs, PLDs, ASICs, or other devices, multiple standard logic cells in the first group of circuits 102 can be combined to perform complex operations (e.g., one or more functions). In some implementations, the standard logic cells are combined to store and process protected data. For example, the standard logic cells can be combined to form at least part of a secure memory for storing protected data. As another example, the standard logic cells can be combined to form at least part of a hardware encryption or decryption engine for securing protected data. As another example, the standard logic cells can be combined to form at least part of a secure access control or payment mechanism that stores protected identification information, such as a smart card, banking card or Subscriber Identity Module (SIM) card.
A hacker may attempt to access or corrupt the protected data that is stored or processed by the device 100 using a variety of different invasive or non-invasive attacks. In particular, the hacker may employ a radiation-based attack during which the hacker directs a beam of radiation (e.g. a laser beam, x-ray, gamma ray, etc.) at the first group of circuits (e.g., at an element of a standard logic cell) that is susceptible to being affected by such radiation; the element may have been previously exposed (e.g., by the hacker grinding off packaging material that protects the element), or the radiation may be able to penetrate intact packaging. In some implementations, radiation interferes with semiconductor devices at the transistor level, for example, by injecting charges or internal currents that disrupt the normal operation of the devices. Register structures within semiconductor devices can be particularly sensitive to such disruptions. As a more specific example, some flip-flops, when subjected to certain radiation, can latch and output values that are independent of the values on their inputs. Thus, in some implementations, a hacker can use radiation to modify digital values stored within a flip-flop or other circuit.
Modification of particular digital values by an invasive or noninvasive attack can cause the normal operation of the device 100 to be altered. For example, if device 100 employs the first group of circuits 102 to implement an encryption or security algorithm, the encryption or security algorithm can be affected or compromised if a bit is unexpectedly changed within, for example, logic cell 109 (e.g., by an external radiation source). By repeatedly directing radiation at the logic cell 109 (or to other logic cells) during the operation of the device 100, a hacker can, in some instances, cause the device 100 to completely bypass a security algorithm; in other instances, the hacker can obtain information about the operation of the device 100 that enables the hacker to subsequently crack a corresponding security algorithm in another manner (e.g., the hacker may be able to obtain a key value, which can be subsequently used to access protected information in a manner that is determined by the device to be “authorized”). A vulnerability in the device 100 that allows hackers to modify particular digital values within the device 100 using an invasive or noninvasive attack can also impact the marketability of the device 100 as a “secure device.” Accordingly, it can be advantageous to detect events that are likely to be attacks of the device.
To detect events that are likely to be attacks, the device 100 employs the second group of circuits 104—which has a similar susceptibility to attack (e.g., to radiation) as the first group of circuits 102—in conjunction with the detection circuit 106. In some implementations, the second group of circuits 104 also includes standard logic cells, or portions of standard logic cells, including a memory element 110. Alternatively, the second group of circuits 104 can include other standard elements (not shown) that are common to the first group of circuits 102 in architecture and function. Because the second group of circuits 104 has a similar susceptibility to attack as the first group of circuits 102, the second group of circuits 104 detects, in some implementations, an attack that can compromise the security of the first group of circuits 102. Upon detecting such an attack, the detection circuit 106 can trigger a countermeasure circuit 108 that initiates a protective countermeasure to maintain the security of the device 100. As described above, example countermeasures can include resetting or powering down portions of the device. A specific example of the second group of circuits 104 (also referred to below as “circuit 104”) is now illustrated and described with reference to
During normal operation, since the memory elements are configured to persistently store a known state (e.g., a logic zero), none of the memory elements will have at its output a different state (e.g., a logic one), and the detection circuit 106 will accordingly have a known output state (e.g., not output a logic one). However, if one of the memory elements (e.g., flip-flop 202A) is subjected to certain kinds of attacks (e.g., radiation attacks (schematically depicted by lightning bolt 203)), that memory element can latch and output a new value (e.g., a logic one), and the detection circuit 106 can detect this new value and flag the detection at its output (e.g., by outputting a logic one or other appropriate value on the net labeled “LIGHT_FAULT” in
As further depicted in
Other countermeasure circuits (not shown) can also be triggered. For example, in some implementations, countermeasure circuits can prevent read data from being provided to an output interface of the device 100; countermeasure circuits can prevent write data from being stored in the device 100; countermeasure circuits can cause the device to “freeze” and not respond to external inputs; countermeasure circuits can cause protected data to be erased; countermeasure circuits can cause communication channels (not shown) of the device 100 to be closed; countermeasure circuits can cause portions of the device 100 to self-destruct to secure protected data (e.g., a countermeasure circuit can subject certain electrically closed internal traces or fuses to short voltages or currents that cause the traces to become electrically open (e.g., melt), irreversibly preventing the device 100 from providing stored data to external circuitry); or countermeasure circuits can initiate other actions or cause other results.
In some implementations, multiple countermeasure circuits can be triggered in sequence or parallel. For example, some implementations include a counter (not shown) that tracks a number of times the LIGHT_FAULT signal is asserted. The first time the LIGHT_FAULT signal is asserted, the reset circuit 208A can be triggered to reset a portion of the device 100; the second time the LIGHT_FAULT signal is asserted, the power-down control 208B can be triggered to power down a portion of the device 100; the third time the LIGHT_FAULT signal is asserted, a circuit (not shown) that causes a portion of the device 100 to self-destruct can be activated, irreversibly altering the device 100 and securing protected data stored in or processed by the device 100. In some implementations, different countermeasure circuits can be triggered based on a specific location within the device 100 that an attack is detected. For example, more drastic countermeasures can be initiated if the attack is detected in areas of the device 100 that store or process protected data, whereas less drastic countermeasures can be initiated if an attack is detected in areas of the device 100 that do not directly store or process protected data.
In some implementations, the detection circuit 106 only asserts the LIGHT_FAULT signal if more than one memory element 202A, 202B or 202N has a value other than the expected value. For example, in some implementations, the detection circuit requires unexpected values from at least two memory elements 202A, 202B or 202N before asserting the LIGHT_FAULT signal. In particular, the detection circuit 106 can include more complicated circuitry than a single OR gate; moreover, some implementations of the detection circuit 106 include a counter (not shown) that must reach a predetermined value before the LIGHT_FAULT signal is asserted. In this manner, sensitivity of the detection circuit 106 can be “tuned” based on various environmental or process parameters. For example, in very noisy environments, occasional glitches in the memory element 202A may be anticipated. By requiring multiple unexpected values from the memory elements 202A, 202A or 202N, “false-positive” initiations of a countermeasure circuit 108 can be avoided, but by triggering the LIGHT_FAULT signal after a predetermined number of unexpected values from the memory elements 202A, 202B and 202N, the device 100 can still be protected from true attacks.
As shown in
A few example detection and countermeasure circuits are illustrated and described with reference to
To protect a large portion of the device 100, the detection cells can be distributed across a substantial portion of the surface of the device 100. Accordingly, for example, radiation that is directed to function cells will likely impinge on one or more detection cells and the radiation can thereby be detected. For example, if a hacker directs radiation to the function cell 304 (e.g., in an attempt to access or corrupt data stored or processed by the device 100), the radiation will be likely to also impinge on the detection cell 307. If enough detection cells are included, radiation that impinges on any portion of the device 100 can be detected. For example, if a typical radiation-based attack involves focusing a laser beam on portions of the device 100, and if a typical laser beam generally affects a fixed number (e.g., 500) of function cells simultaneously, then by including at least one detection cell for substantially every fixed number (e.g., 500) of function cells and substantially uniformly distributing the detection cells across the surface of the device 100, a laser-based attack of any portion of the device 100 is likely to be detected.
Detection cells can be distributed across the surface of the device 100 in a number of ways. For example, in some implementations, the detection cells are placed and routed in a regular pattern (e.g., a checkerboard pattern (not shown)) along with the function cells. As another example, a number of detection cells are randomly distributed across the device 100; in particular, for instance, a number (e.g., one hundred) detection cells can be randomly placed across the device 100. As another example, one detection cell can be placed with each group of a certain number of function cells; in particular, for instance, one detection cell can be included with substantially every twenty function cells, and the detection cell can be placed at a location that is convenient based on the placement and routing of the twenty function cells. As another example, all of the function cells can be placed and routed, and detection cells can be added around the placed and routed function cells. In some implementations, the detection cells are standard logic cells that are not used as function cells. As another example, critical portions of the device 100 can be placed and routed (e.g., portions of the device 100 most affecting security of data that is to be stored or processed by the device 100), and detection cells can be added in greater number around the critical portions.
In some implementations, “spare” standard logic cells are routed with function cells in order to provide a means to more easily debug, repair or enhance functionality (e.g., in case bugs arise in a final layout). That way, if, for example, after an ASIC is produced, it is determined that a circuit in the ASIC is not functioning properly, a nearby spare logic cell can be used to correct the functionality. If there are enough spare logic cells in the design, the change can be implemented, for example, with a small change to a metal interconnect layer, rather than by an entire redesign of the ASIC. In these implementations, the spare cells can be used as detection cells—unless and until they are subsequently needed to implement changes, at which point, detection functionality of that cell can be disconnected and the spare cell can be used to implement the changes.
The method 400 includes configuring (402) a circuit to persistently store a first value. For example, with reference to
The method 400 includes monitoring (404) the stored value, and determining (406) whether the stored value is equal to a second value. For example, the method 400 can include monitoring (404) outputs of the memory elements 202A, 202B and 202N with the detection circuit 106 to determine (406) whether any of the memory elements 202A, 202B or 202N currently have a logic one value.
If the monitored stored value(s) is (are) not equal to the second value, the method 400 includes continuing to monitor (404) the stored value(s). If the stored value is equal to the second value, then the method 400 includes initiating (408) a countermeasure. For example, the method 400 can include initiating a countermeasure 108 in response to assertion of the LIGHT_FAULT signal, which indicates that one or more of the memory elements 202A, 202B or 202N is currently storing an unexpected value—a possible indication of a radiation-based attack. In particular, initiating (408) a countermeasure can include, for example, triggering a reset circuit 208A, triggering a power-down control circuit 208B, triggering an alarm circuit 208C, or triggering some other countermeasure circuit 108.
A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the described implementations. For example, the techniques and methods described herein can be applied to FPGAs, PLDs, ASICs and other electrical circuits used to implement smart cards, banking cards, secure memory devices, SIM cards or used in other applications; countermeasures can be applied in many different ways or combinations of ways; detection cells can detect many different kinds of radiation, including, for example, visible light, infrared radiation, laser light, x-rays, or gamma rays; detection cells can be placed in a device in many different ways and may include cells that are not used to implement a function performed by the device; detection cells can detect attacks other than radiation-based attacks, such as, for example, voltage glitch attacks. Accordingly, other implementations are within the scope of the following claims.
