Patent Application
20240206201
This application claims the benefit of priority from Japanese Patent Application No. 2022-203690 filed on Dec. 20, 2022, the entire contents of which are incorporated herein by reference.
What is disclosed herein relates to a detection device.
In these years, optical biometric sensors are known as biometric sensors used for personal authentication, for example. Fingerprint sensors (refer to United States Patent Application Publication No. 2018/0012069 (US-A-2018/0012069), for example) and vein sensors are known as such biometric sensors. In a fingerprint sensor described in US-A-2018/0012069, a plurality of photoelectric conversion elements such as photodiodes are arranged on a semiconductor substrate. Each of the photoelectric conversion elements outputs a signal that changes depending on the amount of light emitted thereto.
Organic photo detectors, such as organic photodiodes (OPDs), are known as the photoelectric conversion elements for detection. In detection devices using the OPDs, defects in an organic semiconductor layer or a conductive layer generated by foreign matter or external scars can cause spot-like irregularities, which may cause degradation in detection accuracy and imaging characteristics.
For the foregoing reasons, there is a need for a detection device capable of improving the detection accuracy and the imaging characteristics.
According to an aspect, a detection device includes: a plurality of organic photodiodes arranged in a detection area; a plurality of capacitive elements each coupled in parallel to a corresponding organic photodiode of the organic photodiodes; an analog front-end (AFE) circuit configured to read an electric charge amount stored in each of the capacitive elements to acquire a detection value of each of the organic photodiodes; a power supply circuit configured to supply a power supply potential to collectively apply a reverse bias to the organic photodiodes; and a control circuit configured to control the power supply potential. The organic photodiodes each includes: an active layer; an upper electrode provided with an upper buffer layer interposed between the upper electrode and the active layer; and a lower electrode provided with a lower buffer layer interposed between the lower electrode and the active layer.
The following describes modes (embodiments) for carrying out the present disclosure in detail with reference to the drawings. The present disclosure is not limited to the description of the embodiments given below. Components described below include those easily conceivable by those skilled in the art or those substantially identical thereto. In addition, the components described below can be combined as appropriate. What is disclosed herein is merely an example, and the present disclosure naturally encompasses appropriate modifications easily conceivable by those skilled in the art while maintaining the gist of the disclosure. To further clarify the description, the drawings may schematically illustrate, for example, widths, thicknesses, and shapes of various parts as compared with actual aspects thereof. However, they are merely examples, and interpretation of the present disclosure is not limited thereto. The same component as that described with reference to an already mentioned drawing is denoted by the same reference numeral through the description and the drawings, and detailed description thereof may not be repeated where appropriate.
In this disclosure, when an element is described as being “on” another element, the element can be directly on the other element, or there can be one or more elements between the element and the other element.
The sensor base member 21 is electrically coupled to a control substrate 121 through a flexible printed circuit board 71. The flexible printed circuit board 71 is provided with the AFE circuit 48. The control substrate 121 is provided with the control circuit 122 and the power supply circuit 123.
The control circuit 122 includes, for example, a control integrated circuit (IC) that outputs logic control signals. The control circuit 122 may be, for example, a programmable logic device (PLD) such as a field-programmable gate array (FPGA).
The control circuit 122 performs processes related to a detection operation and an operation to calibrate a sensor power supply potential VDDSNS to be described later in the detection device 1. The control circuit 122 supplies control signals to the sensor area 10, the gate line drive circuit 15, and the signal line selection circuit 16 to control the detection operation in the sensor area 10. The control circuit 122 also supplies control signals to the first and the second light sources 61 and 62 to control lighting and non-lighting of the first and the second light sources 61 and 62.
In the present disclosure, the control circuit 122 generates and outputs a sensor power supply control signal VDDSNSCTRL (to be described later) to the power supply circuit 123.
The power supply circuit 123 supplies voltage signals including, for example, the sensor power supply potential VDDSNS (refer to
The sensor base member 21 has a detection area AA and a peripheral area GA. The detection area AA is an area in which a plurality of optical sensors PD (organic photodiodes) PD (refer to
The gate line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the gate line drive circuit 15 is provided in an area extending along the second direction Dy in the peripheral area GA. The signal line selection circuit 16 is provided in an area extending along a first direction Dx in the peripheral area GA and is provided between the sensor area 10 and the AFE circuit 48.
The first direction Dx is one direction in a plane parallel to the sensor base member 21. The second direction Dy is one direction in the plane parallel to the sensor base member 21 and is a direction orthogonal to the first direction Dx. The second direction Dy may non-orthogonally intersect the first direction Dx. A third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy, and is a direction normal to the sensor base member 21.
The first light sources 61 are provided on the first light source base member 51, and are arranged along the second direction Dy. The second light sources 62 are provided on the second light source base member 52, and are arranged along the second direction Dy. The first light source base member 51 and the second light source base member 52 are electrically coupled, through terminals 124 and 125 provided on the control substrate 121, to the control circuit 122 and the power supply circuit 123.
For example, inorganic light-emitting diodes (LEDs) or organic electroluminescent (EL) diodes (organic light-emitting diodes (OLEDs)) are used as the first and the second light sources 61 and 62.
Light emitted from the first and the second light sources 61 and 62 is mainly reflected on a surface or inside of an object to be detected, such as a finger Fg, and is incident on the sensor area 10. Through this operation, the sensor area 10 can detect a shape of asperities on the surface of the finger Fg or the like, and information on a living body (hereinafter, also called “biometric information”) in the finger Fg or the like. Examples of the biometric information include pulse waves, pulsation, and a vascular image of the finger Fg or a palm. That is, the detection device 1 may be configured as a fingerprint detection device to detect a fingerprint or a vein detection device to detect a vascular pattern of, for example, veins.
In an aspect of the present disclosure, the light emitted from the first light sources 61 and the light emitted from the second light sources 62 may have different wavelengths from each other. Thus, the detection device 1 can detect the various information on the living body by performing the detection based on the light emitted from the first light sources 61 and the detection based on the light emitted from the second light sources 62.
The arrangement of the first and the second light sources 61 and 62 illustrated in
The sensor area 10 includes the optical sensors PD. In the present disclosure, each of the optical sensors PD included in the sensor area 10 is an organic photodiode (OPD). The optical sensor PD outputs an electrical signal corresponding to light emitted thereto as a detection signal Vdet to the signal line selection circuit 16. The sensor area 10 performs the detection in response to a gate drive signal Vgcl supplied from the gate line drive circuit 15.
The detection control circuit 11 supplies respective control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection circuit 40 to control operations of these circuits. The detection control circuit 11 supplies various control signals including, for example, a start signal STV, a clock signal CK, and a reset signal RST1 to the gate line drive circuit 15. The detection control circuit 11 also supplies various control signals including, for example, a selection signal ASW to the signal line selection circuit 16. The detection control circuit 11 also supplies various control signals to the first and the second light sources 61 and 62 to control the lighting and the non-lighting of each group of the first and the second light sources 61 and 62.
The gate line drive circuit 15 drives a plurality of gate lines GCL (refer to
The signal line selection circuit 16 includes a switch circuit that sequentially or simultaneously selects a plurality of signal lines SGL (refer to
The detection circuit 40 includes the AFE circuit 48, a signal processing circuit 44, a storage circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 performs control to cause the AFE circuit 48 and the signal processing circuit 44 to operate in synchronization with each other based on a control signal supplied from the detection control circuit 11.
The AFE circuit 48 is an analog front-end integrated circuit (IC), for example. The AFE circuit 48 is a signal processing circuit having functions of at least a detection signal amplifying circuit 42 and an analog-to-digital (A/D) conversion circuit 43. The detection signal amplifying circuit 42 amplifies the detection signal Vdet. The A/D conversion circuit 43 converts the analog signal output from the detection signal amplifying circuit 42 into a digital signal at a predetermined sampling period and outputs an AFE signal AFESIG (to be described later). As illustrated in
In the present disclosure, the control circuit 122 includes the signal processing circuit 44 and the storage circuit 46.
The signal processing circuit 44 detects a predetermined physical quantity received by the sensor area 10 based on an output signal of the AFE circuit 48. The signal processing circuit 44 is a logic circuit. The signal processing circuit 44 can detect the asperities on the surface of the finger Fg or the palm based on the signals from the AFE circuit 48 when the finger Fg is in contact with or in proximity to a detection surface. The signal processing circuit 44 can detect the information on the living body based on the signals from the AFE circuit 48. Examples of the information on the living body include the vascular image, the pulse waves, the pulsation, and a blood oxygen level of the finger Fg or the palm.
The signal processing circuit 44 may also perform processing of acquiring the detection signals Vdet (information on the living body) simultaneously detected by the optical sensors PD, and averaging the detection signals Vdet. In this case, the detection circuit 40 can perform stable detection by reducing measurement errors that would be caused by noise or relative positional misalignment between the object to be detected, such as the Fg finger, and the sensor area 10.
The storage circuit 46 temporarily stores therein the signals processed by the signal processing circuit 44. In the present disclosure, the storage circuit 46 also stores therein information on a biometric data acquisition area that is set in a biometric data acquisition area setting process flow (to be described later) when the signal processing circuit 44 acquires the biometric data, and stores therein various types of setting information. In an aspect of the present disclosure, the storage circuit 46 may include, for example, a random-access memory (RAM), a read-only memory (ROM), and an electrically erasable programmable read-only memory (EEPROM). The storage circuit 46 may be a register circuit, for example.
The following describes a circuit configuration example of the detection device 1.
The gate lines GCL extend in the first direction Dx, and are each coupled to the partial detection areas PAA arranged in the first direction Dx. A plurality of gate lines GCL(1), GCL(2), . . . , GCL(8) are arranged in the second direction Dy, and are each coupled to the gate line drive circuit 15. In the following description, the gate lines GCL(1), GCL(2), . . . , GCL(8) will each be simply referred to as the gate line GCL when they need not be distinguished from one another. For ease of understanding of the description,
The signal lines SGL extend in the second direction Dy, and are each coupled to the optical sensors PD of the partial detection areas PAA arranged in the second direction Dy. A plurality of signal lines SGL(1), SGL(2), . . . , SGL(12) are arranged in the first direction Dx, and are each coupled to the signal line selection circuit 16 and a reset circuit 17. In the following description, the signal lines SGL(1), SGL(2), . . . , SGL(12) will each be simply referred to as the signal line SGL when they need not be distinguished from one another.
For ease of understanding of the description,
In
The gate line drive circuit 15 receives the various control signals such as the start signal STV, the clock signal CK, and the reset signal RST1 from the control circuit 122 (refer to
The gate line drive circuit 15 may perform different driving for each of detection modes including the detection of a fingerprint and the detection of a plurality of different items of the biometric information (such as the pulse waves, the pulsation, the vascular image, and the blood oxygen level). For example, the gate line drive circuit 15 may collectively drive more than one of the gate lines GCL.
Specifically, the gate line drive circuit 15 simultaneously selects a predetermined number of the gate lines GCL from among the gate lines GCL(1), GCL(2), . . . , GCL(8) based on the control signals. For example, the gate line drive circuit 15 simultaneously selects six gate lines GCL(1) to GCL(6) and supplies thereto the gate drive signals Vgcl. The gate line drive circuit 15 supplies the gate drive signals Vgcl through the selected six gate lines GCL to the first switching elements Tr. By this operation, block units PAG1 and PAG2 each including more than one of the partial detection areas PAA arranged in the first direction Dx and the second direction Dy are selected as the detection targets. The gate line drive circuit 15 collectively drives the predetermined number of the gate lines GCL and sequentially supplies the gate drive signals Vgcl to each unit of the predetermined number of the gate lines GCL.
The signal line selection circuit 16 includes a plurality of selection signal lines Lsel, the plurality of output signal lines Lout, and third switching elements TrS. The third switching elements TrS are provided correspondingly to the signal lines SGL. Six signal lines SGL(1), SGL(2), . . . , SGL(6) are coupled to a common output signal line Lout1. Six signal lines SGL(7), SGL(8), . . . , SGL(12) are coupled to a common output signal line Lout2. The output signal lines Lout1 and Lout2 are each coupled to the AFE circuit 48.
The signal lines SGL(1), SGL(2), . . . , SGL(6) are grouped into a first signal line block, and the signal lines SGL(7), SGL(8), . . . , SGL(12) are grouped into a second signal line block. The selection signal lines Lsel are coupled to the gates of the respective third switching elements TrS included in one of the signal line blocks. One of the selection signal lines Lsel is coupled to the gates of the third switching elements TrS in the signal line blocks.
Specifically, selection signal lines Lsel1, Lsel2, . . . , Lsel6 are coupled to the third switching elements TrS corresponding to the signal lines SGL(1), SGL(2), . . . , SGL(6), respectively. The selection signal line Lsel1 is coupled to the third switching element TrS corresponding to the signal line SGL(1) and the third switching element TrS corresponding to the signal line SGL(7). The selection signal line Lsel2 is coupled to the third switching element TrS corresponding to the signal line SGL(2) and the third switching element TrS corresponding to the signal line SGL(8).
The control circuit 122 (refer to
The signal line selection circuit 16 may collectively couple more than one of the signal lines SGL to the AFE circuit 48. Specifically, the control circuit 122 (refer to
The detection is performed for each of the block units PAG1 and PAG2 by the operations of the gate line drive circuit 15 and the signal line selection circuit 16. As a result, the strength of the detection signal Vdet obtained by a one-time detection operation increases, so that the sensor sensitivity can be improved.
As illustrated in
The control circuit 122 supplies a reset signal RST2 to the reset signal line Lrst. This operation turns on the fourth switching elements TrR to electrically couple the signal lines SGL to the reference signal line Lvr. The power supply circuit 123 supplies a reference signal COM to the reference signal line Lvr. This operation supplies the reference signal COM to a capacitive element Ca (refer to
Each of the first switching elements Tr is provided correspondingly to the optical sensor PD. The first switching element Tr is formed of a thin-film transistor, and in this example, formed of an n-channel metal oxide semiconductor (MOS) thin-film transistor (TFT).
The gates of the first switching elements Tr belonging to the partial detection areas PAA arranged in the first direction Dx are coupled to the gate line GCL. The sources of the first switching elements Tr belonging to the partial detection areas PAA arranged in the second direction Dy are coupled to the signal line SGL. The drain of the first switching element Tr is coupled to the cathode of the optical sensor PD and the capacitive element Ca.
The anode of the optical sensor PD is supplied with the sensor power supply potential VDDSNS from the power supply circuit 123. The cathode of the optical sensor PD and the capacitive element Ca are supplied with the reference signal COM that serves as an initial potential of the signal line SGL and the capacitive element Ca from the power supply circuit 123.
In the present disclosure, the sensor power supply potential VDDSNS is a variable potential having a normal potential of 2.75 V, for example. In the present disclosure, the potential of the reference signal COM is, for example, 0.75 V, as described above. That is, the potential difference between the potential of the reference signal COM and the sensor power supply potential VDDSNS is applied to the optical sensor PD. By this operation, a reverse bias is applied between the anode and the cathode of the optical sensor PD.
When the partial detection area PAA is irradiated with light, a current corresponding to the amount of the light flows through the optical sensor PD. As a result, an electric charge corresponding to the amount of the light is stored in the capacitive element Ca. After the first switching element Tr is turned on, a current corresponding to the electric charge stored in the capacitive element Ca flows through the signal line SGL. The signal line SGL is coupled to the AFE circuit 48 through a corresponding one of the third switching elements TrS of the signal line selection circuit 16. By this operation, the detection device 1 can detect a signal corresponding to the amount of the light received by the optical sensor PD in each of the partial detection areas PAA or signals corresponding to the amounts of the light received by the optical sensors PD in each of the block units PAG1 and PAG2.
During a read period Pdet (refer to
The following describes a configuration example of the optical sensor PD.
The sensor structure 22 includes a TFT layer 221, a cathode electrode (lower electrode) 222, the optical sensor PD, and an anode electrode (upper electrode) 226. The optical sensor PD detects first light LD incident from a second surface FU side.
The TFT layer 221 is provided with various types of wiring such as the gate line GCL and the signal line SGL. The sensor base member 21 and the TFT layer 221 serve as a drive circuit that drives the sensor and are also called a backplane.
The optical sensor PD includes an active layer 224, a hole transport layer (lower buffer layer) 223 provided between the active layer 224 and the cathode electrode (lower electrode) 222, and an electron transport layer (upper buffer layer) 225 provided between the active layer 224 and the anode electrode (upper electrode) 226. In other words, the hole transport layer (lower buffer layer) 223, the active layer 224, and the electron transport layer (upper buffer layer) 225 of the optical sensor PD are stacked in this order in a direction orthogonal to the sensor base member 21.
The active layer 224 changes in characteristics (for example, voltage-current characteristics and resistance value) according to light that illuminates the active layer 224. An organic material is used as a material of the active layer 224. Specifically, the active layer 224 has a bulk heterostructure containing a mixture of a p-type organic semiconductor and an n-type fullerene derivative (PCBM) that is an n-type organic semiconductor. As the active layer 224, low-molecular-weight organic materials can be used, such as fullerene (C60), phenyl-C61-butyric acid methyl ester (PCBM), copper phthalocyanine (CuPc), fluorinated copper phthalocyanine (F16CuPc), 5,6,11,12-tetraphenyltetracene (rubrene), and perylene diimide (PDI) (derivative of perylene).
The active layer 224 can be formed by a vapor deposition process (dry process) using the low-molecular-weight organic materials listed above. In this case, the active layer 224 may be, for example, a multilayered film of CuPc and F16CuPc, or a multilayered film of rubrene and C60. The active layer 224 can also be formed by a coating process (wet process). In this case, the active layer 224 is made using a material obtained by combining the above-listed low-molecular-weight organic materials with a high-molecular-weight organic material. As the high-molecular-weight organic material, for example, poly(3-hexylthiophene) (P3HT) and F8-alt-benzothiadiazole (F8BT) can be used. The active layer 224 can be a film made of a mixture of P3HT and PCBM, or a film made of a mixture of F8BT and PDI.
The hole transport layer (lower buffer layer) 223 and the electron transport layer (upper buffer layer) 225 are provided to facilitate electrons and holes generated in the active layer 224 to reach the cathode electrode (lower electrode) 222 or the anode electrode (upper electrode) 226. The hole transport layer (lower buffer layer) 223 is in direct contact with the top of the cathode electrode (lower electrode) 222. The active layer 224 is in direct contact with the top of the hole transport layer (lower buffer layer) 223.
The electron transport layer (upper buffer layer) 225 is in direct contact with the top of the active layer 224, and the anode electrode (upper electrode) 226 is in direct contact with the top of the electron transport layer (upper buffer layer) 225.
The cathode electrode (lower electrode) 222 faces the anode electrode (upper electrode) 226 with the optical sensor PD interposed therebetween. A light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is used as the anode electrode (upper electrode) 226. A metal material such as silver (Ag) or aluminum (Al) is used as the cathode electrode (lower electrode) 222. Alternatively, the cathode electrode (lower electrode) 222 may be made of an alloy material containing at least one or more of these metal materials.
The protective film 23 is provided on the second surface FU so as to cover the anode electrode (upper electrode) 226. The protective film 23 is a passivation film provided to protect the optical sensor PD.
The following describes an operation example of the detection device 1.
As illustrated in
The sensor power supply potential VDDSNS is a signal that applies the reverse bias between the anode and the cathode of the optical sensor PD. For example, the reference signal COM of substantially 0.75 V is applied to the anode of the optical sensor PD. By applying, for example, the sensor power supply potential VDDSNS of substantially 2.75 V to the cathode of the optical sensor PD, a reverse bias of substantially 2.0 V is applied between the anode and the cathode. The control circuit 122 sets the reset signal RST2 to “H”, and then, supplies the start signal STV and the clock signal CK to the gate line drive circuit 15 to start the reset period Prst. During the reset period Prst, the control circuit 122 supplies the reference signal COM to the reset circuit 17 and uses the reset signal RST2 to turn on the fourth switching elements TrR for supplying a reset voltage. This operation supplies the reference signal COM as the reset voltage to each of the signal lines SGL.
During the reset period Prst, the gate line drive circuit 15 sequentially selects the gate lines GCL based on the start signal STV, the clock signal CK, and the reset signal RST1. The gate line drive circuit 15 sequentially supplies gate drive signals Vgcl {Vgcl(1), . . . , Vgcl(M)} to the gate lines GCL. Each of the gate drive signals Vgcl has a pulsed waveform having a power supply voltage VDD serving as a high-level voltage and a power supply voltage VSS serving as a low-level voltage.
Specifically, as illustrated in
In the same manner, the gate line drive circuit 15 supplies the gate drive signals Vgcl(2), . . . , Vgcl(M−1), Vgcl(M) at the high-level voltage to gate lines GCL(2), . . . , GCL(M−1), GCL(M) during periods V(2), . . . , V(M−1), V(M), respectively.
Through this operation, during the reset period Prst, the capacitive elements Ca of all the partial detection areas PAA are sequentially electrically coupled to the signal lines SGL, and are supplied with the reference signal COM. As a result, the capacitance of the capacitive elements Ca is reset. The capacitance of the capacitive elements Ca of some of the partial detection areas PAA can be reset by partially selecting the gate lines and the signal lines SGL.
Examples of the method of controlling the exposure include a method of controlling the exposure during non-selection of the gate lines and a method of always controlling the exposure.
In the method of controlling the exposure during non-selection of the gate lines, the gate drive signals {Vgcl(1), . . . , Vgcl(M)} are sequentially supplied to all the gate lines GCL coupled to the optical sensors PD serving as the detection targets, and all the optical sensors PD serving as the detection targets are supplied with the reset voltage. Then, after all the gate lines GCL coupled to the optical sensors PD serving as the detection targets are set to a low voltage (the first switching elements Tr are turned off), the exposure starts and the exposure is performed during the exposure period Pex. After the exposure ends, the gate drive signals {Vgcl(1), . . . , Vgcl(M)} are sequentially supplied to the gate lines GCL coupled to the optical sensors PD serving as the detection targets as described above, and reading is performed during the read period Pdet.
In the method of always controlling the exposure, the control for performing the exposure can also be performed during the reset period Prst and the read period Pdet (the exposure is always controlled). In this case, the exposure period Pex(1) starts after the gate drive signal Vgcl(1) is supplied to the gate line GCL(1) during the reset period Prst. The exposure periods Pex {(1), . . . , (M)} are actual exposure periods and are periods during which the capacitive elements Ca are charged from the optical sensors PD and do not includes any periods in which light is emitted, other than these periods. The electric charge stored in the capacitive element Ca during the reset period Prst causes a reverse-directional current (from cathode to anode) to flow through the optical sensor PD due to light irradiation, and the potential difference in the capacitive element Ca decreases. The start timings and the end timings of the actual exposure periods Pex(1), . . . , Pex(M) for the partial detection areas PAA corresponding to the gate lines GCL are different between the exposure periods Pex. Each of the exposure periods Pex(1), . . . , Pex(M) starts when the gate drive signal Vgcl changes from the power supply voltage VDD serving as the high-level voltage to the power supply voltage VSS serving as the low-level voltage in the reset period. Each of the exposure periods Pex(1), . . . , Pex(M) ends when the gate drive signal Vgcl changes from the power supply voltage VSS to the power supply voltage VDD in the read period Pdet. The lengths of the exposure time of the actual exposure periods Pex(1), . . . , Pex(M) in the partial detection areas PAA corresponding to the gate lines GCL are equal to one another.
During the exposure periods Pex {(1) . . . (M)}, a current flows correspondingly to the light irradiating the optical sensor PD of each of the partial detection areas PAA. As a result, an electric charge is stored in each of the capacitive elements Ca.
At a time before the read period Pdet starts, the control circuit 122 sets the reset signal RST2 to a low-level voltage. This operation stops the operation of the reset circuit 17. The reset signal may be set to a high-level voltage only during the reset period Prst. During the read period Pdet, the gate line drive circuit 15 sequentially supplies the gate drive signals Vgcl to the gate lines GCL in the same manner as during the reset period Prst.
Specifically, the gate line drive circuit 15 supplies the gate drive signal Vgcl(1) at the high-level voltage (power supply voltage VDD) to the gate line GCL(1) during a row read period VR(1) illustrated in
In the same manner, the gate line drive circuit 15 supplies the gate drive signals Vgcl(2), . . . , Vgcl(M−1), Vgcl(M) at the high-level voltage to the gate lines GCL(2), . . . , GCL(M−1), GCL(M) during row read periods VR(2), . . . , VR(M−1), VR(M), respectively. That is, the gate line drive circuit 15 supplies the gate drive signal Vgcl to the gate line GCL in each of the row read periods VR(1), VR(2), . . . , VR(M−1), VR(M). The signal line selection circuit 16 sequentially or simultaneously selects the signal lines SGL based on the selection signal ASW during each period in which the gate drive signal Vgcl is set to the high-level voltage. In other words, the signal line selection circuit 16 sequentially or simultaneously couples the signal lines SGL to one AFE circuit 48. By this operation, the detection device 1 can output the detection signals Vdet of all the partial detection areas PAA to the AFE circuit 48 during the read period Pdet.
With reference to
As illustrated in
After a period t1 elapses from a rising edge of the gate drive signal Vgcl(j), a period t2 starts in which the selection signal ASW(k) is set to a high level. After the selection signal ASW(k) is set to the high level and the third switching element TrS is turned on, the AFE circuit 48 is electrically coupled to the capacitor (capacitive element Ca) of the partial detection area PAA via the third switching element TrS. This operation changes the output (Vout) of the third switching element TrS (refer to
At this time, the potential of the inverting input portion of the detection signal amplifying circuit 42 is set to a virtual short-circuit potential of an operational amplifier, and therefore, becomes the reference potential (Vref). The A/D conversion circuit 43 reads the output voltage of the detection signal amplifying circuit 42. In the example illustrated in
Specifically, after the switch SSW is turned on in the period t4, the electric charge moves from the capacitor (capacitive element Ca) of the partial detection area PAA to the capacitor (capacitive element Cb) of the detection signal amplifying circuit 42 of the AFE circuit 48. At this time, the reference potential (Vref) voltage (at 0.75 V, for example) is applied to the non-inverting input (+) of the detection signal amplifying circuit 42. As a result, the output (Vout) of the third switching element TrS is also set to the reference potential (Vref) voltage due to the virtual short-circuit between the inputs of the detection signal amplifying circuit 42. The voltage of the capacitive element Cb is set to a voltage corresponding to the electric charge stored in the capacitor (capacitive element Ca) of the partial detection area PAA at a location where the third switching element TrS is turned on in response to the selection signal ASW(k). After the output (Vout) of the third switching element TrS is set to the reference potential (Vref) voltage due to the virtual short-circuit, the output of the detection signal amplifying circuit 42 reaches a voltage corresponding to the capacitance of the capacitive element Cb. The A/D conversion circuit 43 reads the output voltage of the detection signal amplifying circuit 42 at this time. The voltage of the capacitive element Cb is, for example, a voltage between two electrodes provided on a capacitor constituting the capacitive element Cb.
In the example illustrated in
The light sources (the first light sources 61 or the second light sources 62) are continuously turned on during the periods t(1) and t(2). The control circuit 122 can control the lighting and the non-lighting of the light sources depending on the detection target. For example, the control circuit 122 may switch on and off the first and the second light sources 61 and 62 at intervals of a certain period of time, or may continuously turn on either of the first and the second light sources 61 and 62.
If foreign matter and/or external scars cause defects in the sensor structure 22 of the optical sensor PD and, for example, water enters inside, spot-like irregularities (hereinafter, also called “spot irregularities”) considered to be caused by charge trapping may be generated. The spot irregularities progress over time and may cause degradation in detection accuracy and imaging characteristics as the detection device 1.
Even if the spot irregularities are caused by the defects in the optical sensor PD, in an initial state after the detection device 1 is produced, the dark area DAA due to the spot irregularity caused by foreign matter or external scars of the optical sensor PD is small, and the difference in brightness between the dark area DAA and the normal area BRA where no spot irregularities are occurred is also small, as illustrated in
In
In the present disclosure, the sensor power supply potential VDDSNS is increased in accordance with the change over time of the AFE output values corresponding to the optical sensors PD in the entire detection area AA when the entire detection area AA is irradiated with a constant amount of light (at 1 μW, for example), whereby the reverse bias voltage applied to the optical sensors PD in the entire detection area AA is increased. In other words, the sensor power supply potential VDDSNS is controlled so that a second sensor power supply potential VDDSNS2 at a second time after a first time is higher than a first sensor power supply potential VDDSNS1 at the first time. This operation allows the detection device 1 according to the present disclosure to reduce spot irregularities that would be caused by the defects in the optical sensors PD and improve the detection accuracy and the imaging characteristics.
As illustrated in
The functions of the AFE output value detection circuit 401, the threshold generation circuit 402, the comparative determination circuit 403, the sensor power supply control signal output circuit 404, and the processing circuit 406 may be integrated into the signal processing circuit 44, for example. The function of the storage circuit 405 may be integrated into the storage circuit 46, for example.
In the calibration process to be described later, the sensor power supply control circuit 400 outputs, to the power supply circuit 123, the sensor power supply control signal VDDSNSCTRL for changing the sensor power supply potential VDDSNS to be supplied to the optical sensors PD in the entire detection area AA.
In the first embodiment of the present disclosure, at the time of the first operation (for example, in a testing process in the production line of the detection device 1), the control circuit 122 initially sets a calibration process execution timer T to perform the calibration process for the sensor power supply potential according to the first embodiment. Specifically, the control circuit 122 sets the value of the calibration process execution timer T to “0” (T=0).
After the detection device 1 starts (Step S001), the control circuit 122 determines whether the value of the calibration process execution timer T is equal to or higher than a predetermined calibration process execution time threshold Tth (Step S002). The calibration process execution time threshold Tth is set as appropriate according to the characteristics of the device.
If the value of the calibration process execution timer T is lower than the predetermined calibration process execution time threshold Tth (T<Tth, No at Step S002), the control circuit 122 performs the detection process mentioned above (Step S004), and then performs a predetermined end process (Step S005) to end the overall operation in the detection device 1 illustrated in
If the value of the calibration process execution timer T is equal to or higher than the predetermined calibration process execution time threshold Tth (T≥Tth, Yes at Step S002), the control circuit 122 performs the calibration process for the sensor power supply potential VDDSNS according to the first embodiment illustrated in
In the calibration process for the sensor power supply potential VDDSNS according to the first embodiment illustrated in
The AFE output value detection circuit 401 detects an AFE output value AFESIG(n, m) (n is a natural number from 1 to N, and m is a natural number from 1 to M, refer to
The AFE output value detection circuit 401 determines whether all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA have been stored (Step S105). If all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA have not been stored (No at Step S105), the process from Step S103 to Step S104 is repeated until all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA are stored (Yes at Step S105).
If all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA have been stored (Yes at Step S105), AFE output value information illustrated in
After the AFE output value information illustrated in
The AFE output value descending order sort information illustrated in
Specifically, the processing circuit 406 sets that: n=0, m=0, and p=0 (where p is a natural number from 1 to N×M (=P)) (Step S111); m=m+1 (Step S112); and n=n+1 (Step S113). The processing circuit 406 reads the AFE output signal level AFESIG(n, m) from the storage circuit 405 (Step S114).
The processing circuit 406 sets that p=p+1 (Step S115), reads the AFE output value AFESIG(p) corresponding to the rank p (Step S116), and determines whether the AFE output value AFESIG(n, m) is equal to or higher than the AFE output value AFESIG(p) (AFESIG(n, m)≥AFESIG(p), Step S117).
If the AFE output value AFESIG(n, m) is lower than the AFE output value AFESIG(p) (AFESIG(n, m)<AFESIG(p), No at Step S117), the process from Step S115 to Step S117 is repeated.
If the AFE output value AFESIG(n, m) is equal to or higher than the AFE output value AFESIG(p) (AFESIG(n, m) AFESIG(p), Yes at Step S117), the processing circuit 406 increments the AFE output value AFESIG(p) at the current rank p and higher ranks (AFESIG(P−1)=AFESIG(P), . . . , AFESIG(p)=AFESIG(p+1)) and stores the AFE output value AFESIG(n, m) as the AFE output value AFESIG(p) at the rank p (Step S118).
The processing circuit 406 then determines whether n=N (Step S119). If n=N is not established (No at Step S119), the processing circuit 406 repeats the process from Step S113 to Step S119. If n=N (Yes at Step S119), the processing circuit 406 sets that n=0 (Step S120) and determines whether m=M (Step S121). If m=M is not established (No at Step S121), the processing circuit 406 repeats the process from Step S112 to Step S121.
The descending order sort process described above (Steps S111 to S121) generates the AFE output value descending order sort information illustrated in
If m=M (Yes at Step S121), the threshold generation circuit 402 reads the AFE output value descending order sort information stored in the storage circuit 405 and extracts a threshold AFESIGth for the AFE output value AFESIG(p) (Step S131). A specific example of the threshold AFESIGth will be described with reference to
In the present disclosure, the AFE output value AFESIG(p) with the largest number of the AFE output values AFESIG(p) having the same value is set as the threshold AFESIGth, as illustrated in
The threshold generation circuit 402 stores the extracted threshold AFESIGth in the storage circuit 405 (Step S132).
The comparative determination circuit 403 reads the threshold AFESIGth stored in the storage circuit 405 (Step S133), extracts the number A of the AFE output values AFESIG(p) that are equal to or higher than the threshold AFESIGth (Step S134, refer to
If the number A of the AFE output values AFESIG(p) that are equal to or higher than the threshold AFESIGth is smaller than the predetermined number Ath (A<Ath, No at Step S135), the process returns to the overall operation of the detection device 1 illustrated in
If the number A of the AFE output values AFESIG(p) that are equal to or higher than the threshold AFESIGth is equal to or larger than the predetermined number Ath (A Ath, Yes at Step S135), the sensor power supply control signal output circuit 404 generates the sensor power supply control signal VDDSNSCTRL to cause the power supply circuit 123 to increase the sensor power supply potential VDDSNS by ΔV (Step S191) and outputs the sensor power supply control signal VDDSNSCTRL to the power supply circuit 123, and the process starting from Step S102 is repeated.
If the number A of the AFE output values AFESIG(p) that are equal to or higher than the threshold AFESIGth is smaller than the predetermined number Ath (A<Ath, No at Step S135), the process returns to the overall operation of the detection device 1 illustrated in
The detection device 1 according to the first embodiment performs the calibration process described above each time a predetermined time (calibration process execution time) elapses. This operation increases the sensor power supply potential VDDSNS with the passage of time t, as illustrated in
According to the first embodiment described above, the calibration process for the sensor power supply potential VDDSNS according to the first embodiment is performed each time a predetermined time (calibration process execution time threshold Tth) or more elapses. Specifically, in the calibration process for the sensor power supply potential VDDSNS according to the first embodiment, the sensor power supply potential VDDSNS is increased when, among all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA, the number A of the AFE output values AFESIG(p) that are equal to or higher than the threshold AFESIGth is equal to or larger than the predetermined number Ath.
This operation allows the sensor power supply potential VDDSNS to increase in accordance with the change over time of the AFE output values corresponding to the optical sensors PD in the entire detection area AA when the entire detection area AA is irradiated with a constant amount of light (at 1 μW, for example). As a result, the reverse bias voltage applied to the optical sensors PD in the entire detection area AA can be increased. Thus, the spot irregularities that would be caused by the defects in the optical sensors PD can be reduced, and the detection accuracy and the imaging characteristics can be improved.
As illustrated in
In the calibration process for the sensor power supply potential VDDSNS according to the second embodiment illustrated in
The average value calculation circuit 407 extracts a predetermined number of upper values of the AFE output values AFESIG(p) with reference to the AFE output value descending order sort information (Step S142). The average value calculation circuit 407 extracts a predetermined number of lower values of the AFE output values AFESIG(p) with reference to the AFE output value descending order sort information (Step S143). The predetermined numbers of the upper and lower values of the AFE output values AFESIG(p) to be extracted are each 10, for example. FIG. 24 illustrates an example of extracting the AFE output values AFESIG(1) to AFESIG(10) from the rank 1 to the rank 10 in descending order as the upper values, and extracting the AFE output values AFESIG(P) to AFESIG(P−9) from the rank P to the rank P−9 in ascending order as the lower values. However, the predetermined number “10” illustrated herein by which each group of the upper and lower values of the AFE output values AFESIG(p) is extracted is an example, and the present disclosure is not limited by the predetermined number by which each group of the upper and lower values of the AFE output values AFESIG(p) is extracted.
The average value calculation circuit 407 calculates the average value AFESIGave of the AFE output values AFESIG(1) to AFESIG(10) from the rank 1 to the rank 10 extracted in descending order and the AFE output values AFESIG(P) to AFESIG(P−9) from the rank P to the rank P−9 extracted in ascending order (Step S144).
The average value calculation circuit 407 stores the calculated average value AFESIGave in the storage circuit 405 (Step S145).
The comparative determination circuit 403a reads the threshold AFESIGaveth and the average value AFESIGave that are stored in the storage circuit 405 (Step S146), and determines whether the average value AFESIGave is equal to or higher than the threshold AFESIGaveth (Step S147).
If the average value AFESIGave is lower than the threshold AFESIGaveth (AFESIGave<AFESIGaveth, No at Step S147), the process returns to the overall operation of the detection device 1 illustrated in
If the average value AFESIGave is equal to or higher than the threshold AFESIGaveth (AFESIGave≥AFESIGaveth, Yes at Step S147), the sensor power supply control signal output circuit 404 generates the sensor power supply control signal VDDSNSCTRL to cause the power supply circuit 123 to increase the sensor power supply potential VDDSNS by ΔV (Step S191), and outputs the sensor power supply control signal VDDSNSCTRL to the power supply circuit 123, and the process starting from Step S102 is repeated.
If the average value AFESIGave is lower than the threshold AFESIGaveth (AFESIGave<AFESIGaveth, No at Step S147), the process returns to the overall operation of the detection device 1 illustrated in
According to the second embodiment described above, the calibration process for the sensor power supply potential VDDSNS according to the second embodiment is performed each time the predetermined time (calibration process execution time threshold Tth) or more elapses. Specifically, in the calibration process for the sensor power supply potential VDDSNS according to the second embodiment, the sensor power supply potential VDDSNS is increased if, among all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA, the average value AFESIGave of the predetermined number of the upper AFE output values AFESIG(p) and the predetermined number of the lower AFE output values AFESIG(p) is equal to or higher than the threshold AFESIGaveth.
This operation allows the sensor power supply potential VDDSNS to increase in accordance with the change over time of the AFE output values corresponding to the optical sensors PD in the entire detection area AA when the entire detection area AA is irradiated with a constant amount of light (at 1 μW, for example), in the same manner as in the first embodiment. As a result, the reverse bias voltage applied to the optical sensors PD in the entire detection area AA can be increased. Thus, the spot irregularities that would be caused by the defects in the optical sensors PD can be reduced, and the detection accuracy and the imaging characteristics can be improved, in the same manner as in the first embodiment.
A storage circuit 405a of a sensor power supply control circuit 400b according to the third embodiment illustrated in
In the calibration process for the sensor power supply potential VDDSNS according to the third embodiment illustrated in
The threshold generation circuit 402a then sets the upper threshold AFESIGthU (first threshold) for the upper average value AFESIGaveU and the lower threshold AFESIGthL (second threshold) for the lower average value AFESIGaveL (Step S152, refer to
The threshold generation circuit 402a sets the calculated upper threshold AFESIGthU as the threshold (first threshold) for the upper average value AFESIGaveU and sets the calculated lower threshold AFESIGthL as the threshold (second threshold) for the lower average value AFESIGaveL. The method for setting the upper and the lower thresholds AFESIGthU and AFESIGthL illustrated herein is an example, and the present disclosure is not limited by the method for setting the upper and the lower thresholds AFESIGthU and AFESIGthL.
An average value calculation circuit 407a extracts a predetermined number of upper values of the AFE output values AFESIG(p) with reference to the AFE output value descending order sort information (Step S153). The predetermined number of the upper values to be extracted from the AFE output values AFESIG(p) is set to 10, for example. In this case, the average value calculation circuit 407a calculates the upper average value AFESIGaveU of the AFE output values AFESIG(1) to AFESIG(10) from the rank 1 to the rank 10 extracted in descending order (Step S154), and stores the upper average value AFESIGaveU in the storage circuit 405a (Step S155).
The average value calculation circuit 407a extracts a predetermined number of lower values of the AFE output value AFESIG(p) by referring to the AFE output value descending order sort information (step S156). The predetermined number of the lower values to be extracted from the AFE output values AFESIG(p) is set to 10, for example. In this case, the average value calculation circuit 407a calculates the lower average value AFESIGaveL of the AFE output values AFESIG(P) to AFESIG(P−9) from the rank P to the rank P−9 extracted in ascending order (Step S157), and stores the lower average value AFESIGaveL in the storage circuit 405a (Step S158).
A comparative determination circuit 403b reads the upper threshold AFESIGthU and the upper average value AFESIGaveU that are stored in the storage circuit 405a (Step S159), and determines whether the upper average value AFESIGaveU is equal to or higher than the upper threshold AFESIGthU (Step S160).
If the upper average value AFESIGaveU is lower than the upper threshold AFESIGthU (AFESIGaveU<AFESIGthU, No at Step S160), the comparative determination circuit 403b reads the lower threshold AFESIGthL and the lower average value AFESIGaveL that are stored in the storage circuit 405a (Step S161), and determines whether the lower average value AFESIGaveL is equal to or lower than the lower threshold AFESIGthL (Step S162).
If the lower average value AFESIGaveL is higher than the lower threshold AFESIGthL (AFESIGaveL>AFESIGthL, No at Step S162), the process returns to the overall operation of the detection device 1 illustrated in
If the upper average value AFESIGaveU is equal to or higher than the upper threshold AFESIGthU (AFESIGaveU>AFESIGthU, Yes at Step S160) or if the lower average value AFESIGaveL is equal to or lower than the lower threshold AFESIGthL (AFESIGaveL≤AFESIGthL, Yes at Step S162), the sensor power supply control signal output circuit 404 generates the sensor power supply control signal VDDSNSCTRL to cause the power supply circuit 123 to increase the sensor power supply potential VDDSNS by ΔV (Step S191). The generated sensor power supply control signal VDDSNSCTRL is output to the power supply circuit 123, and the process starting from Step S102 is repeated.
If the upper average value AFESIGaveU is lower than the upper threshold AFESIGthU (AFESIGaveU<AFESIGthU, No at Step S160) and the lower average value AFESIGaveL is higher than the lower threshold AFESIGthL (AFESIGaveL>AFESIGthL, No at Step S162), the process returns to the overall operation of the detection device 1 illustrated in
According to the third embodiment described above, the calibration process for the sensor power supply potential VDDSNS according to the third embodiment is performed at a period of the predetermined time (calibration process execution time threshold Tth) or more. Specifically, in the calibration process for the sensor power supply potential VDDSNS according to the third embodiment, the sensor power supply potential VDDSNS is increased if the upper average value AFESIGaveU is equal to or higher than the upper threshold AFESIGthU (first threshold), or if the lower average value AFESIGaveL is equal to or lower than the lower threshold AFESIGthL (second threshold). The upper average value AFESIGaveU is the average value of the predetermined number of the upper AFE output values AFESIG(p) among all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA. The lower average value AFESIGaveL is the average value of the predetermined number of the lower AFE output values AFESIG(p) among all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA.
This operation allows the sensor power supply potential VDDSNS to increase in accordance with the change over time of the AFE output values corresponding to the optical sensors PD in the entire detection area AA when the entire detection area AA is irradiated with a constant amount of light (at 1 μW, for example), in the same manner as in the first and the second embodiments. As a result, the reverse bias voltage applied to the optical sensors PD in the entire detection area AA can be increased. Thus, the spot irregularities that would be caused by the defects in the optical sensors PD can be reduced, and the detection accuracy and the imaging characteristics can be improved, in the same manner as in the first and the second embodiments.
As illustrated in
A storage circuit 405b of the sensor power supply control circuit 400c according to the fourth embodiment illustrated in
In the calibration process for the sensor power supply potential VDDSNS according to the fourth embodiment illustrated in
The average value calculation circuit 407a extracts a predetermined number of lower values of the AFE output values AFESIG(p) with reference to the AFE output value descending order sort information (Step S174). The predetermined number of the lower values to be extracted from the AFE output values AFESIG(p) is set to 10, for example. In this case, the average value calculation circuit 407a calculates the lower average value AFESIGaveL of the AFE output values AFESIG(P) to AFESIG(P−9) from the rank P to the rank P−9 extracted in ascending order (Step S175), and stores the lower average value AFESIGaveL in the storage circuit 405b (Step S176).
The predetermined number “10” illustrated herein by which each group of the upper and lower values of the AFE output values AFESIG(p) is extracted is an example, and the present disclosure is not limited by the predetermined number by which each group of the upper and lower values of the AFE output values AFESIG(p) is extracted.
The difference value calculation circuit 408 reads the upper average value AFESIGaveU and the lower average value AFESIGaveL that are stored in the storage circuit 405b (Step S177), calculates the difference value ΔAFESIGr between the upper average value AFESIGaveU and the lower average value AFESIGaveL (Step S178), and stores the difference value ΔAFESIGr in the storage circuit 405b (Step S179).
The comparative determination circuit 403c reads the difference value ΔAFESIGr and the difference threshold ΔAFESIGrth that are stored in the storage circuit 405b (Step S180), and determines whether the difference value ΔAFESIGr between the upper average value AFESIGaveU and the lower average value AFESIGaveL is equal to or higher than the difference threshold ΔAFESIGrth (Step S181).
If the difference value ΔAFESIGr between the upper average value AFESIGaveU and the lower average value AFESIGaveL is lower than the difference threshold ΔAFESIGrth (ΔAFESIGr<ΔAFESIGrth, No at step S181), the process returns to the overall operation of the detection device 1 illustrated in
If the difference value ΔAFESIGr between the upper average value AFESIGaveU and the lower average value AFESIGaveL is equal to or higher than the difference threshold ΔAFESIGrth (ΔAFESIGr≥ΔAFESIGrth, Yes at Step S181), the sensor power supply control signal output circuit 404 generates the sensor power supply control signal VDDSNSCTRL to cause the power supply circuit 123 to increase the sensor power supply potential VDDSNS by ΔV (Step S191). The generated sensor power supply control signal VDDSNSCTRL is output to the power supply circuit 123, and the process starting from Step S102 is repeated. The value of ΔV serving as the increment of the sensor power supply potential VDDSNS is set to 0.1 V (ΔV=0.1 V), for example. The value of the increment ΔV (=0.1 V) of the sensor power supply potential VDDSNS illustrated herein is an example, and the present disclosure is not limited by the value of the increment ΔV of the sensor power supply potential VDDSNS.
According to the fourth embodiment described above, the calibration process for the sensor power supply potential VDDSNS according to the fourth embodiment is performed each time the predetermined time (calibration process execution time threshold Tth) or more elapses. Specifically, in the calibration process for the sensor power supply potential VDDSNS according to the fourth embodiment, the sensor power supply potential VDDSNS is increased if the difference value ΔAFESIGr between the upper average value AFESIGaveU and the lower average value AFESIGaveL is equal to or higher than the difference threshold ΔAFESIGrth. The upper average value AFESIGaveU is the average value of the predetermined number of the upper AFE output values AFESIG(p) among all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA. The lower average value AFESIGaveL is the average value of the predetermined number of the lower AFE output values AFESIG(p) among all the AFE output values AFESIG(n, m) corresponding to the optical sensors PD in the entire detection area AA.
This operation allows the sensor power supply potential VDDSNS to increase in accordance with the change over time of the AFE output values corresponding to the optical sensors PD in the entire detection area AA when the entire detection area AA is irradiated with a constant amount of light (at 1 μW, for example), in the same manner as in the embodiments described above. As a result, the reverse bias voltage applied to the optical sensors PD in the entire detection area AA can be increased. Thus, the spot irregularities that would be caused by the defects in the optical sensors PD can be reduced, and the detection accuracy and the imaging characteristics can be improved, in the same manner as in the embodiments described above.
In the embodiments described above, an aspect has been exemplified in which the calibration process for the sensor power supply potential is performed if the value of the calibration process execution timer T is equal to or higher than the predetermined calibration process execution time threshold Tth. However, an aspect may be employed in which the sensor power supply potential VDDSNS is increased when a predetermined time has elapsed, or each time a predetermined time has elapsed.
While the preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. The content disclosed in the embodiments is merely an example, and can be variously modified within the scope not departing from the gist of the present disclosure. Any modifications appropriately made within the scope not departing from the gist of the present disclosure also naturally belong to the technical scope of the present disclosure. At least one of various omissions, substitutions, and changes of the components can be made without departing from the gist of the embodiments and the modifications described above.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-203690 | Dec 2022 | JP | national |
