Patent Application
20240223082
Some integrated circuits (ICs) include a pin to which an external passive component (e.g., a resistor, a capacitor, etc.) is connected. The IC can be configured for a particular setting based on a parameter associated with the passive component. For example, the resistance of a resistor may map to a desired configuration setting for the IC. In one example, the configuration setting may be for an output current limit for the IC, the switching frequency of the IC, etc.
In one example, an integrated circuit (IC) includes a pin, a first passive component determination circuit, and a first switch having a first switch control input. The first switch is coupled between the first passive component determination circuit and the pin. The IC further includes a second passive component determination circuit and a second switch having a second switch control input. The second switch is coupled between the second passive component determination circuit and the pin. A logic circuit is coupled to first switch control input and to the second switch control input. The logic circuit is configured to close the first switch and open the second switch and then open the first switch and close the second switch.
The same reference numbers or other reference designators are used in the drawings to designate the same or similar (either by function and/or structure) features.
For an IC having a pin to which a single passive component is connected for configuration purposes, the number of different configuration settings depends, to a certain extent, on the resolution of the IC's circuitry to determine the passive component's parameter (e.g., resistance in the case of a resistor or capacitance in the case of a capacitor). Such passive component measurement circuitry may include an analog-to-digital converter (ADC) to convert an analog signal generated using the passive component to a digital code. The digital code is indicative of the passive component's parameter. A digital code includes one or more bits. A two-bit ADC, for example, can resolve four different levels of the passive component's parameter. In this example (a two-bit ADC), the passive component measurement circuitry permits four different values (or ranges of values) of the passive component to be connected to the IC's pin to thereby specify four different configuration settings for the IC. If it is desired to configure the IC with more than four different settings, a higher resolution ADC could be implemented but higher resolution ADCs are more complex, occupy more space on the IC, and consume more power.
The embodiments described herein are directed to an IC that has a configuration pin to which multiple passive components can be connected, instead of just one passive component. The IC includes circuitry that sequentially determines a value indicative of the parameter of each of the multiple passive components. For example, in the embodiment described herein, the passive components include a resistor coupled in parallel to a capacitor between the IC's configuration pin and ground. The circuitry first determines a value indicative of the resistance of the resistor, and then determines a value indicative of the capacitance of the capacitor. By permitting two passive components, each with its permitted multiple levels of parameters or ranges of parameters, a larger number of configuration settings can be implemented by the IC than would have otherwise have been the case for a pin measurement circuit that has a low-resolution ADC.
The configuration pin described above is shown in the example of
The example IC 102 in
The configuration circuit 120 in the example of
The resistance determination circuit 310 includes an operational amplifier (OP AMP) 312, a current mirror 314, a digital-to-analog converter (DAC) 316, a logic gate 318, a counter 320, and a transistor M1. In this example, transistor M1 is an n-channel field effect transistor (NFET). In other examples, transistor M1 can be implemented as a different type of transistor. The logic gate 318 is an inverter in this example.
The OP AMP 312 includes a non-inverting (positive, +) input, an inverting (negative, −) input, and an output. A direct current (DC) voltage V1 is provided to the non-inverting input. The source of transistor M1 is coupled to the negative input of OP AMP 312. The output of OP AMP 312 is coupled to the gate of transistor M1. OP AMP 312 and transistor M1 function as a voltage-to-current converter converting voltage V1 to a current IRset. The voltage on the non-inverting input of OP AMP 312 is also provided on the inverting input and thus on the source of transistor M1. Because the source of transistor M1 is coupled to resistor RSET, the voltage across resistor RESET is V1. The current through resistor RESET is IRset. A larger magnitude of voltage V1 results in a larger magnitude for current IRset, and vice versa. The magnitude of voltage V1 can be any voltage in a fairly wide range.
The current mirror 314 mirrors current IRset as current I1. The current mirror ratio implemented by current mirror 314 may be 1:1 or another suitable ratio. The current mirror 314 couples to DAC 316 and to the input 317 of logic gate 318 (e.g., inverter) at node A. The current into the DAC 316 is current I2. The current in to, or out of, the logic gate 318 is current I3. The sum of currents I2 and I3 equals current I1 from the current mirror 316. The output of logic gate 318 is coupled to a latch input 319 of counter 320. Responsive to the latch input being at one logic state (e.g., logic “1”), the counter 320 counts pulses of a clock signal provided on its clock input 311 and produces successively increasing digital codes (RegR) on its output 321 and holds its output code RegR at the value present when the latch input transitioned to logic 1. Responsive to the latch being at another logic state (e.g., logic “0”), the counter 320 ceases incrementing its output digital code. The counter can be reset by a signal provided on its reset (RST) input. For example, a logic “1” on its reset input causes the counter to set its output digital count back to 0.
The output 321 of counter 320 is coupled to the digital input 323 of DAC 316. The DAC 316 responds to each successively increasing digital code RegR by increasing the magnitude of current I2 at analog output 327. When the magnitude of current I1 is larger than the magnitude of current I2, current I3 flows into the logic gate 318, and the voltage on node A is logic high.
Responsive to the digital code RegR being large enough for DAC 316 to force current I2 to equal and exceed current I1, current I3 becomes negative (discharges the input 317 of logic gate 318) and the node A voltage becomes logic low. This transition is shown at 404 in
During the time that switch S1 is closed (ON), switches S2 and S3 are open (OFF), voltage V1 is also forced across capacitor CSET. With a DC voltage across the plates of capacitor CSET, little or no current flows into capacitor CSET. Thus, the digital code RegR represents the resistance value of resistor RSET. Before determining a value indicative of the capacitance of capacitor CSET, the logic 380 asserts switch control signal S3_CTL to close switch S3 to close long enough to discharge capacitor CSET.
During the next phase of operation in which the capacitance determination circuit 350 determines a value of indicative of the capacitance of capacitor CSET, the logic circuit 380 asserts control signals S1_CTL, S2_CTL, and S3_CTL to cause switches S1 and S3 to be open (OFF) and switch S2 to be closed (ON). The timing diagram of
The capacitance determination circuit 350 includes a current source circuit 352, a current mirror 354, an OP AMP 356, a comparator 358, a counter 360, transistor M2, and a resistor RDET. Switch S2 is coupled between the current source circuit 350 (at node C) and the parallel combination of resistor RSET and capacitor CSET. The current source circuit 350 produces a current I4. Switch S2 is also coupled to the non-inverting input of OP AMP 356. The inverting input of OP AMP 356 is coupled to the source of transistor M2 and to resistor RDET. Resistor RDET is coupled between the source of transistor M2 and ground. In this example, transistor M2 is an NFET. The drain of transistor M2 is coupled to one terminal 351 of current mirror 354, and the other terminal 353 of current mirror 354 is coupled through switch S2 to the capacitor CSET/resistor RSET parallel combination.
The non-inverting input of comparator 358 is coupled to switch S2, current source circuit 352, current mirror 354, and the non-inverting input of OP AMP 356 at node C. A DC threshold voltage V2 is provided to the inverting input of comparator 358. The output of comparator 358 is coupled to the latch input 361 of counter 360. The node coupling the output of the comparator and the latch input of the counter is labeled node B. The counter 360 counts pulses of a clock signal on its clock input 363 responsive to the voltage on the latch input 361 being at one logic state (e.g., logic 0). In this example, the counter 360 is an up-counter and thus increments its digital output code REGC on its output 365 with each successive pulse of the clock input signal. Responsive to the logic level on the logic input 361 being at a different logic state (e.g., logic), the counter 360 ceases counting and freezes its output digital code REGC.
Current source circuit 352 forces a constant level current I4 into the parallel combination of capacitor CSET and resistor RSET. The voltage across the capacitor CSET is the voltage on the mode pin 105 and is referred to as Vmode. Responsive to capacitor CSET being charged by a fixed current I4, the voltage across capacitor CSET (Vmode) increases approximately linearly as shown at 406 in
Comparator 358 compares voltage Vmode to V2 and produces an output signal indicative of whether Vmode is larger or smaller than V2. The output of comparator 358 is coupled to the latch 361 of counter 360. The counter 360 increments its digital code REGC starting, for example, from 0 when its reset (RST) input is forced high by logic 380 until Vmode equals V2. When Vmode reaches V2 (point 408 in
The function performed by the combination of OP AMP 356, transistor M2, resistor RDET, and current mirror 354 is create a current to approximately equal the current that flows through resistor RSET. As a result, the current IRdet from current mirror 354 offsets the current through resistor RSET, so that the counter 360 produces a digital code REGC that more accurately indicates the capacitance of capacitor CSET.
In this example, the resistor RDET is a configurable resistor. The configurable resistor RDET has a resistor control input 375, which is coupled to the counter output 321. The digital code REGR, which is indicative of resistor RSET, is provided to the resistor control input 375. The resistance of resistor RDET is configured based on the digital code REGR. In one example, the configurable resistor RDET includes multiple resistors, each coupled to a switch (e.g., in series with the switch or in parallel with the switch), and the digital code REGR controls the ON and OFF state of the switches to select just those resistors to be electrically coupled between the source of transistor M2 and ground to thereby approximate the resistance of resistor RSET.
The voltage Vmode is applied to across resistor RSET. The same voltage Vmode also is coupled to the non-inverting input of OP AMP 356. Through the OP AMP 356, the same voltage Vmode also is applied across resistor RDET. Thus, both resistors RSET and configurable resistor RDET have the same voltage. With configurable resistor RDET set for a resistance approximately equal to the resistance of resistor RSET, both resistors have approximately the same current. The current mirror 354 mirrors the current through transistor M2 and resistor RDET as current IRdet, which flows through resistor RSET while switch S2 is closed.
Logic 380 receives digital codes REGR and REGC. Digital code REGR is indicative of the resistance of resistor RSET. Digital code REGC is indicative of the capacitance of capacitor CSET. Logic 380, or other logic circuitry within IC 102 may configure one or more parameters about the operation of the IC based on both the REGB and REGC digital codes. Non-limiting examples of such configuration parameters are provided above. A technical benefit of the resistance determination circuit 310, capacitance determination circuit 350, switches S1 and S2, and logic 380 is that only a single a pin 105 need be available on the IC to which multiple passive components can be connected. Multiple pins (each pin for a separate passive component) are not needed. In some embodiments, however, multiple pins such as pin 105 may be included so that three, four or more passive components can be coupled to the IC for configuration parameter purposes.
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
Also, in this description, the recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, then X may be a function of Y and any number of other factors.
A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
As used herein, the term “pin” refers to any suitable type of electrical contact to one or more components fabricated on an IC. Different types of packages are available for ICs such as a flat package, a pin grid array, a surface mount package, a chip carrier, a small outline package, etc. Examples of a flat package include a quad-flat no-lead (QFN) package and a dual-flat no-lead (DFN) package. Some packages may have leads, while other packages may not have leads. Regardless of the package type the “pin” described herein is the electrical contact to the circuitry fabricated on the die.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.
While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a field effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT—e.g., NPN transistor or PNP transistor), an insulated gate bipolar transistor (IGBT), and/or a junction field effect transistor (JFET) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other types of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).
References may be made in the claims to a transistor's control input and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.
References herein to a FET being “ON” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “OFF” means that the conduction channel is not present so drain current does not flow through the FET. An “OFF” FET, however, may have current flowing through the transistor's body-diode.
Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter or, if the parameter is zero, a reasonable range of values around zero.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
