BRIEF DESCRIPTION OF THE DRAWINGS
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:
FIG. 1 shows a block diagram of a stage of a ring oscillator device according to one embodiment of the invention.
FIG. 2 shows an alternative embodiment of a ring oscillator device including three stages according to the invention.
It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements among the drawings.
DETAILED DESCRIPTION
The present invention is created based on, among others, the understanding that the sheet resistance of an un-silicided poly-silicon resistor varies with a variation in the surrounding temperature. As such, a value of the sheet resistance of an un-silicided poly-silicon resistor can be used to indicate/measure a temperature of a part of an IC chip, which is directly related to/reflects a thermal absorption thereof. The next question is to develop a device that can take advantage of the above mentioned thermal characteristic of an un-silicided poly-silicon resistor. Preferably, such a device should work without affecting the functioning of an IC chip to be measured. This enables characterization of the within chip thermal absorption variation of a real functional chip, which can be sold in the market. It is also desirable that the determination of the thermal absorption of an IC chip requires no destruction of the same. A ring oscillator does not interrupt the functioning of an IC chip. Based on the above, the current invention creates and uses a specially designed ring oscillator to determine a thermal absorption of a part of an IC chip.
Turning to the drawings, FIG. 1 shows a block diagram of a stage of a ring oscillator device 10 according to one embodiment of the invention. As shown in FIG. 1, ring oscillator 10 includes an inverter 12, e.g., a complementary metal oxide semiconductor (CMOS) inverter; an un-silicided poly-silicon resistor 14; and a decoupling capacitor (capacitor) 16, all between input port 20 and output port 22. Un-silicided poly-silicon resistor 14 is coupled to the output of inverter 12, and is positioned between the output of inverter 12 and output port 22 of ring oscillator 10. Capacitor 16 is coupled between the output of inverter 12 and a ground 24. FIG. 1 shows that capacitor 16 is positioned after un-silicided poly-silicon resistor 14, which is a preferable configuration, but does not necessarily limit the scope of the invention. The parameters of inverter 12, un-silicided poly-silicon resistor 14 and capacitor 16 should be carefully designed/tuned so that the delay of ring oscillator 10 varies predominantly with and is sensitive to a variation in a resistance of un-silicided poly-silicon resistor 14. For example, according to one embodiment, the CMOS transistors (not shown) that constitute inverter 12 may be made with long and wide devices so that there is very little relative variations in inverter 12 parameters. As a consequence, the delay of ring oscillator 10 is not sensitive to the variations in inverter 12 parameters, and the range of the variations in the delay of ring oscillator 12 is also not limited by inverter 12 parameters. The parameters of un-silicided poly-silicon resistor 14 and capacitor 16 may also be selected so that the delay of ring oscillator 10 will not vary substantially with or be sensitive to the potential variations in the capacitance of capacitor 16. For example, un-silicided poly-silicon resistor 14 may be fabricated with long and wide devices, and be lightly doped so that un-silicided poly-silicon resistor 14 has a large base resistance. As a consequence, even if the resistance of un-silicided poly-silicon resistor 14 decreases due to temperature variations, the decreased resistance value of un-silicided poly-silicon resistor 14 may still dominate capacitor 16 in influencing the delay of ring oscillator 10. For another example, dimensions of un-silicided poly-silicon resistor 14 are large compared to a process variation in the dimensions of the un-silicided poly-silicon such that the resistance is insensitive to the process variation.
Multiple ring oscillators 10 may be positioned nearby multiple parts of an IC chip to determine the thermal absorptions thereof. According to one embodiment, the multiple ring oscillators 10 may be fabricated on the IC chip (on-chip) as built-in-self-test (BIST) devices to determine variations in thermal absorptions across the chip. According to an alternative embodiment, ring oscillator 10 may be a separate device (off-chip) that is attached to an IC chip to determine the thermal absorption variations across the chip.
In operation, during a functioning state of an IC chip, a delay of a ring oscillator 10 may be measured and sent to, e.g., a computer system, to determine a resistance of un-silicided poly-silicon resistor 14 based on the delay. The computer system then determines a temperature based on the determined resistance of un-silicided poly-silicon resistor 14. As is appreciated, the temperature reflects thermal absorption of the part of the IC chip. Following this procedure, the thermal absorption variations of the multiple parts of the IC chip can be determined.
Ring oscillator 10 shown in FIG. 1 includes only one stage, i.e., one inverter 12. It should be appreciated that ring oscillator 10 may typically include any odd number of stages, and all are included in the current invention. For example, FIG. 2 shows an alternative embodiment of ring oscillator 100 including three stages 110. Each stage 110 includes an inverter 112, an un-silicided poly-silicon resistor 114 and a decoupling capacitor 116. Preferably, inverters 112, un-silicided poly-silicon resistors 114 and decoupling capacitors 116 are tuned to be of the same sizes, respectively, to facilitate the analyses and the calculation of the delay-resistance relationship. However, other configurations are also included in the invention.
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.