Patent Application
20120317380
The present invention relates generally to devices coupled to communication and storage systems, and more particularly to devices coupled to the communication and storage systems that use digital data with an embedded clock signal.
Typically, devices connected to communication and storage systems have a variation in clock rate between a transmitter and a receiver and this can, very often, result in varying incoming and outgoing data transfer rates between the devices. When a data stream enters a device at a higher or lower data transfer rate than the device clock rate, then an adjustment to the incoming data transfer rate with respect to the device clock rate is needed to avoid any loss of data due to resulting overflow or underflow condition. Generally, such a condition is overcome by using an elasticity first in first out (FIFO) in the receiving data path of the device. Further, special signatures are embedded in the incoming data stream to form special symbols, which are referred to as “skip symbols”, to the elasticity FIFO to adjust the difference in the incoming and outgoing data transfer rates. Typically, each symbol includes about 10 bits of data that is stored in a location in the elasticity FIFO. The adjustment to the data transfer rates is made on read side of the elasticity FIFO by either jumping a read pointer to skip one or more skip symbols or holding the read pointer at the skip symbols based on a difference in the incoming and outgoing data transfer rates. Existing elasticity FIFOs may require higher clock rate based on speed of data transmission and hence can result in implementation complexity and higher power consumption.
A device and method for a half-rate clock elasticity first in first out (FIFO) are disclosed. According to one aspect of the present subject matter, the method includes writing two data blocks substantially simultaneously to two locations in the elasticity FIFO specified by respective two write pointers in a write clock cycle of a write clock. Further, the method includes reading two data blocks substantially simultaneously from two consecutive or non-consecutive locations in the elasticity FIFO specified by two read pointers in a read clock cycle of a read clock. The two read pointers can independently adjust locations to read in a plurality of locations based on a type of data blocks in the elasticity FIFO and a predetermined elasticity FIFO threshold level in the read clock cycle to maintain an elasticity FIFO level at the predetermined elasticity FIFO threshold level to achieve a constant output rate.
According to another aspect of the present subject matter, the device coupled to a communication or storage system for receiving data from a network includes a write pointer generation module, a read pointer generation module coupled to the write pointer generation module, and the elasticity FIFO coupled to the write pointer generation module and the read pointer generation module. Further, the elasticity FIFO includes the plurality of locations to temporarily store data blocks.
The write pointer generation module generates the two write pointers and writes two data blocks substantially simultaneously to two locations in the elasticity FIFO specified by the respective two write pointers in the write clock cycle of the write clock. Further, the read pointer generation module generates the two read pointers and reads two data blocks substantially simultaneously from two consecutive or non-consecutive locations in the elasticity FIFO specified by the two read pointers in the read clock cycle of the read clock. The two read pointers independently adjust locations to read in the plurality of locations based on the type of the data blocks in the elasticity FIFO and the predetermined elasticity FIFO threshold level in the read clock cycle to maintain the elasticity FIFO level at the predetermined elasticity FIFO threshold level to achieve the constant output rate.
The device and methods disclosed herein may be implemented in any means for achieving various aspects, and other features will be apparent from the accompanying drawings and from the detailed description that follows.
Various embodiments are described herein with reference to the drawings, wherein:
The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present invention in any way.
A device and method for data processing using a half-rate elasticity first in first out (FIFO) are disclosed. In the following detailed description of the embodiments of the invention, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
The term “skip symbol” refers to a special character symbol which is different from normal data symbols and is not intended to carry any data, and included as a standard part of an incoming data stream.
Referring now to
As shown in
Further as shown in
In operation, the write pointer generation block 108 generates two write pointers WR PTR0 and WR PTR1. The two write pointers WR PTR0 and WR PTR1 provide address of locations in the elasticity FIFO 102 where the data blocks are written. The write pointer generation block 108 writes two data blocks substantially simultaneously at two locations in the elasticity FIFO 102 specified by the two write pointers WR PTR0 and WR PTR1. Each of the two write pointers WR PTR0 and WR PTR1 is advanced by two locations in the elasticity FIFO 102 in each write clock cycle when a write operation is enabled. Based on the two write pointers WR PTR0 and WR PTR1, two data blocks are continuously loaded to two locations in the elasticity FIFO 102. Further, the skip vector 110 includes information about the locations in the elasticity FIFO 102 holding skip symbols corresponding to the write pointers WR PTR0 and WR PTR1. In addition, the write vector 112 includes information about the number of locations in the elasticity FIFO 102, which includes the data blocks corresponding to the write pointers WR PTR0 and WR PTR1.
Further in operation, the read pointer generation block 116 generates read pointers RD PTR0 and RD PTR1. After the data blocks are written, at least two data blocks are substantially simultaneously read from the elasticity FIFO 102 using the two read pointers RD PTR0 and RD PTR1 based on a type of data blocks in the elasticity FIFO and a predetermined elasticity FIFO threshold level. Exemplary data blocks include data blocks and/or skip symbols. The two read pointers RD PTR0 and RD PTR1 provide address of the locations from where the data blocks are read in the elasticity FIFO 102 in a read clock cycle. Based on the two read pointers RD PTR0 and RD PTR1, the data blocks are unloaded from the locations in the elasticity FIFO 102 and then sent to a receive path logic via the multiplexers 118A and 118B and the timing FFs 120 and 122. In these embodiments, the synchronizer block 114 is used to synchronize data transfer rate between a write clock WR CLK and a read clock RD CLK. Further, the timing FFs 120 and 122 are used to register output from the multiplexers 118A and 118B before sending to the receive path logic. This process continues until all the locations in the elasticity FIFO 102 are read. The read pointers RD PTR0 and RD PTR1 operate independent of each other and simultaneously read two data blocks. During normal operation, each of the two read pointers RD PTR0 and RD PTR1 is advanced by two locations in each read clock cycle when a read operation is enabled. The two read pointers RD PTR0 and RD PTR1 independently adjust locations in the elasticity FIFO 102 to read in the plurality of locations based on the type of the data blocks in the elasticity FIFO 102 and the predetermined elasticity FIFO threshold level in the read clock cycle to maintain an elasticity FIFO level at the predetermined elasticity FIFO threshold level to achieve a constant output rate. This is explained in more detail with respect to
Referring now to
Similarly, the two read pointers RD PTR0 and RD PTR1 initially start at two locations 0 and 1, respectively, and two data blocks are read from the two locations, i.e., locations 0 and 1 respectively. The read process begins when the two write pointers WR PTR0 and WR PTR1 reach the predetermined elasticity FIFO threshold level. The two read pointers RD PTR0 and RD PTR1 increment to the next successive location after each data block is read from the elasticity FIFOs 202 and 204 until the data block is read from the last location, i.e., location 24. After data block is read from the last location, the two read pointers RD PTR0 and RD PTR1 return to the locations 0 and 1, respectively, and the read process is repeated until the device is stopped. In one exemplary implementation, a read operation is performed in each read clock cycle of the read clock RD CLK. The read clock RD CLK is an internal clock of the receiver.
Further, the elasticity FIFO 202 illustrates positions of the two write and two read pointers before the adjustments in a clock cycle (e.g., n). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 50 and data 51) substantially simultaneously to two locations, i.e., locations 0 and 1, respectively, in the elasticity FIFO 202. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 32 and data 33) substantially simultaneously from two locations, i.e., locations 7 and 8, respectively, in the elasticity FIFO 202. In this embodiment, two consecutive locations, i.e., locations 9 and 10, in the elasticity FIFO 202 hold skip symbols (including data 34 and data 35).
Furthermore, the elasticity FIFO 204 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+1). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 52 and data 53) substantially simultaneously to two locations, i.e., locations 2 and 3, respectively, in the elasticity FIFO 204. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 36 and data 37) substantially simultaneously from two locations, i.e., locations 11 and 12, respectively, upon skipping the two consecutive locations (i.e., locations 9 and 10) that are holding the skip symbols in the elasticity FIFO 204. The read pointer RD PTR0 skips the two consecutive locations (i.e., locations 9 and 10) that are holding the skip symbols and moves to next location, i.e., location 11, in the elasticity FIFO 204. The read pointer RD PTR1 moves to next location, i.e., location 12, in the elasticity FIFO 204.
Referring now to
Furthermore, the elasticity FIFO 304 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+1). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 52 and data 53) substantially simultaneously to two locations, i.e., locations 2 and 3, respectively, in the elasticity FIFO 304. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 34 and data 37) substantially simultaneously from two locations, i.e., locations 9 and 12, respectively, upon skipping the two consecutive locations (i.e., locations 10 and 11) that are holding the skip symbols in the elasticity FIFO 304. The RD PTR0 moves to next location, i.e., location 9, in the elasticity FIFO 304. The RD PTR1 skips the two consecutive locations (i.e., locations 10 and 11) that are holding the skip symbols (including data 35 and data 36) and moves to next location, i.e., location 12, in the elasticity FIFO 304.
In addition, the elasticity FIFO 306 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+2). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 54 and data 55) substantially simultaneously to two locations, i.e., locations 4 and 5, respectively, in the elasticity FIFO 306. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 38 and data 39) substantially simultaneously from two locations, i.e., locations 13 and 14, respectively, in the elasticity FIFO 306.
Referring now to
Furthermore, the elasticity FIFO 404 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+1). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 52 and data 53) substantially simultaneously to two locations, i.e., locations 2 and 3, respectively, in the elasticity FIFO 404. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 34 and data 37) substantially simultaneously from two locations, i.e., locations 9 and 12, respectively, upon skipping a part or all of the locations holding the skip symbols in the elasticity FIFO 404. The RD PTR0 moves to next location, i.e., location 9, in the elasticity FIFO 404. The RD PTR1 skips the two consecutive locations (i.e., locations 10 and 11) that are holding the skip symbols and moves to next location, i.e., location 12, in the elasticity FIFO 404. The pair of skip symbols (including data 35 and data 36) in the two consecutive locations, i.e., locations 10 and 11, is skipped and the third skip symbol (including data 37) in location 12 is read normally in the elasticity FIFO 404.
In addition, the elasticity FIFO 406 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+2). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 54 and data 55) substantially simultaneously to two locations, i.e., locations 4 and 5, respectively, in the elasticity FIFO 406. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 38 and data 39) substantially simultaneously from two locations, i.e., locations 13 and 14, respectively, in the elasticity FIFO 406.
Referring now to
Furthermore, the elasticity FIFO 504 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+1). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 52 and data 53) substantially simultaneously to two locations, i.e., locations 2 and 3, respectively, in the elasticity FIFO 504. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 34 and data 43) substantially simultaneously from two locations, i.e., locations 9 and 18, respectively, upon skipping the eight consecutive locations (i.e., locations 10-17) that are holding the skip symbols in the elasticity FIFO 504. The RD PTR0 moves to next location, i.e., location 9, in the elasticity FIFO 504. The RD PTR1 skips the eight consecutive locations (i.e., locations 10-17) that are holding the skip symbols (including data 35-42) and moves to next location, i.e., location 18, in the elasticity FIFO 504.
In addition, the elasticity FIFO 506 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+2). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 54 and data 55) substantially simultaneously to two locations, i.e., locations 4 and 5, respectively, in the elasticity FIFO 506. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 44 and data 45) substantially simultaneously from two locations, i.e., locations 19 and 20, respectively, in the elasticity FIFO 506.
Referring now to
Furthermore, the elasticity FIFO 604 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+1). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 77 and data 78) substantially simultaneously to two locations, i.e., locations 2 and 3, respectively, in the elasticity FIFO 604. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 62 and data 65) substantially simultaneously from two locations, i.e., locations 12 and 15, respectively, upon skipping the locations holding the skip symbols in the elasticity FIFO 604. The RD PTR0 skips the four consecutive locations (i.e., locations 8-11) that are holding the skip symbols (including data 58-61) and moves to next location, i.e., location 12, in the elasticity FIFO 604. The RD PTR1 skips the two consecutive locations (i.e., locations 13 and 14) that are holding the skip symbols (including data 63 and data 64) and moves to next location, i.e., location 15, in the elasticity FIFO 604.
In addition, the elasticity FIFO 606 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+2). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 79 and data 80) substantially simultaneously to two locations, i.e., locations 4 and 5, respectively, in the elasticity FIFO 606. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 66 and data 67) substantially simultaneously from two locations, i.e., locations 16 and 17, respectively, in the elasticity FIFO 606.
Referring now to
Furthermore, the elasticity FIFO 704 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+1). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 44 and data 45) substantially simultaneously to two locations, i.e., locations 19 and 20, respectively, in the elasticity FIFO 704. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 34 and data 35) substantially simultaneously from two locations, i.e., locations 9 and 10, respectively, without skipping the two consecutive locations (i.e., locations 9 and 10) that are holding the skip symbols in the elasticity FIFO 704.
In addition, the elasticity FIFO 706 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+2). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 46 and data 47) substantially simultaneously to two locations, i.e., locations 21 and 22, respectively, in the elasticity FIFO 706. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 36 and data 37) substantially simultaneously from two locations, i.e., locations 11 and 12, respectively, in the elasticity FIFO 706.
Referring now to
Furthermore, the elasticity FIFO 804 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+1). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 42 and data 43) substantially simultaneously to two locations, i.e., locations 17 and 18, respectively, in the elasticity FIFO 804. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 34 and data 35) substantially simultaneously from two locations, i.e., locations 9 and 10, respectively, without skipping the two consecutive locations (i.e., locations 9 and 10) that are holding the skip symbols in the elasticity FIFO 804.
In addition, the elasticity FIFO 806 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+2). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 44 and data 45) substantially simultaneously to two locations, i.e., locations 19 and 20, respectively, in the elasticity FIFO 806. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 34 and data 35) substantially simultaneously from two locations, i.e., locations 9 and 10, respectively, in the elasticity FIFO 806. The two read pointers RD PTR0 and RD PTR1 retain in the two locations, i.e., locations 9 and 10, respectively, until the elasticity FIFO level reaches the predetermined elasticity FIFO threshold level.
Referring now to
Furthermore, the elasticity FIFO 904 illustrates position of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+1). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 42 and data 43) substantially simultaneously to two locations, i.e., locations 17 and 18, respectively, in the elasticity FIFO 904. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 34 and data 35) substantially simultaneously from two locations, i.e., locations 9 and 10, respectively, without skipping the two consecutive locations (i.e., locations 10 and 11) that are holding the skip symbols in the elasticity FIFO 904. The positions of the two write and two read pointers after the adjustments in next clock cycles (e.g., n+2 and n+3) are explained with reference to
Referring now to
Furthermore, the elasticity FIFO 908 illustrates positions of the two write and two read pointers after the adjustments in a next clock cycle (e.g., n+3). The two write pointers WR PTR0 and WR PTR1 write two data blocks (including data 46 and data 47) substantially simultaneously to two locations, i.e., locations 21 and 22, respectively, in the elasticity FIFO 908. The two read pointers RD PTR0 and RD PTR1 read two data blocks (including data 36 and data 37) substantially simultaneously from two locations, i.e., locations 11 and 12, respectively, in the elasticity FIFO 908. The RD PTR0 moves to next location (i.e., location 11) that is holding the skip symbol and the RD PTR1 moves to next location, i.e., location 12, in the elasticity FIFO 908.
Referring now to
At block 1002, two data blocks are written substantially simultaneously to two locations in the elasticity FIFO specified by respective write pointers in a write clock cycle of a write clock. At block 1004, two data blocks are read substantially simultaneously from two consecutive or non-consecutive locations in the elasticity FIFO specified by two read pointers in a read clock cycle of a read clock. The two read pointers can independently adjust locations to read data from the plurality of locations based on a type of the data blocks in the elasticity FIFO and a predetermined elasticity FIFO threshold level in the read clock cycle to maintain an elasticity FIFO level at the predetermined elasticity FIFO threshold level to achieve a constant output rate. In one example embodiment, the predetermined elasticity FIFO threshold level includes a first predetermined number of locations filled with the data blocks that are waiting to be read.
In this embodiment, two data blocks are read substantially simultaneously from the two consecutive or non-consecutive locations in the elasticity FIFO specified by the two read pointers in the read clock cycle of the read clock upon the elasticity FIFO reaching the predetermined elasticity FIFO threshold level. The predetermined elasticity FIFO threshold level includes a second predetermined number of locations filled with the data blocks.
Further in these embodiments, the two read pointers can independently adjust the locations by determining a current elasticity FIFO level based on a number of the plurality of locations filled with the data blocks in each read clock cycle. In one example embodiment, if the current elasticity FIFO level is above the predetermined elasticity FIFO threshold level, then the two read pointers continue reading substantially the two locations specified by the two read pointers in each read clock cycle until they encounter one or more pairs of skip symbols stored in the plurality of locations. Upon encountering the one or more pairs of skip symbols the two read pointers continue reading next two locations including the data blocks upon skipping reading the one or more pairs of skip symbols stored in the plurality of locations.
In another example embodiment, if the current elasticity FIFO level is above the predetermined elasticity FIFO threshold level, then the two read pointers continue reading substantially the two locations specified by the two read pointers in each read clock cycle until they encounter the one or more pairs of skip symbols stored in the plurality of locations and upon encountering the one or more pairs of skip symbols the two read pointers continue reading next two consecutive or non-consecutive locations including the data blocks upon skipping reading part or all of incoming one or more skip symbols stored in the plurality of locations.
Furthermore, if the current elasticity FIFO level is below the predetermined elasticity FIFO threshold level, then the two read pointers continue reading substantially the two locations specified by the two read pointers in each read clock cycle until they encounter the one or more pairs of skip symbols stored in the plurality of locations and upon encountering the one or more pairs of skip symbols the two read pointers continue reading the encountered one or more skip symbols until the current elasticity FIFO level is equal to or above the predetermined elasticity FIFO threshold level. In addition, if the current elasticity FIFO level is equal to the predetermined elasticity FIFO threshold level, then the two read pointers continue reading substantially the two locations specified by the two read pointers in each read clock cycle without skipping any encountered one or more pairs of skip symbols stored in the plurality of locations.
Referring now to
At block 1108, a check is made to determine whether the current elasticity FIFO level is equal to the predetermined elasticity FIFO threshold level. If the current elasticity FIFO level is equal to the predetermined elasticity FIFO threshold level then the process goes to the block 1106 and repeats the process. If the current elasticity FIFO level is not equal to the predetermined elasticity FIFO threshold level, at block 1110, a check is made to determine whether the current elasticity FIFO level is greater than the predetermined elasticity FIFO threshold level. If the current elasticity FIFO level is greater than the predetermined elasticity FIFO threshold level, at block 1112, the two read pointers are skipped over the locations in the elasticity FIFO holding skip symbols. If the current elasticity FIFO level is less than the predetermined elasticity FIFO threshold level, at block 1114, the two read pointers retain over the locations in the elasticity FIFO holding skip symbols for one or more read clock cycles. This is explained in more detail with reference to
In various embodiments, the device and methods described in
Further, even though the present embodiments have been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the various embodiments. Furthermore, the various devices, modules, and the like described herein may be enabled and operated using hardware circuitry, for example, complementary metal oxide semiconductor based logic circuitry, firmware, software and/or any combination of hardware, firmware, and/or software embodied in a machine readable medium. For example, the various electrical structure and methods may be embodied using transistors, logic gates, and electrical circuits, such as application specific integrated circuit.
