The invention relates to a device and method for addressing power to at least a selected load from a plurality of loads, and in particular the invention relates to driving individual light sources in solid state lighting applications, such as decorative indoor and outdoor illumination for buildings or cars.
In solid state lighting applications, such as decorative indoor and outdoor illumination for buildings or cars, decorative effects are generated by using large amounts of small light sources to illuminate relatively large areas. Surprising effects can be obtained by controlling and especially varying the luminescence of individual light sources in time. For independent control of multiple electrical loads, such as light sources, several solutions are known in the art. A simple solution is to provide separate wiring to each load to be controlled. This solution has the disadvantage that it is complex and inconvenient to apply in the field of solid state lighting applications, since the number of wires grows proportionally with the amount of loads, i.e. light sources. Another solution is to add logic that enables addressing each individual load. This solution has the disadvantage of being very expensive, since the amount of logic needed is proportional with the amount of loads as well.
Furthermore it is known, for example from U.S. Pat. No. 6,628,273 to address display elements by taking propagation delays of electrical signals in conductors into account. This method has the disadvantage that its use is restricted to nanosecond time ranges, which are too small for lighting applications.
It is an object of the present invention to provide a method and device for addressing power to at least a selected load from a plurality of loads, in particular light sources such as light emitting diodes (LED's) or LED arrangements, without the requirement of large amounts of wires or logic.
The invention provides an electrical circuit for switching a load among a plurality of loads, the circuit comprising a plurality of cascaded subcircuits, matching the number of loads. When cascading the subcircuits, the total amount of wires remains constant.
In an aspect, the invention comprises an electrical circuit for addressing power to at least a selected load from a plurality of loads, the circuit comprising a plurality of cascaded subcircuits, each subcircuit for powering one of the loads, each subcircuit comprising a first input terminal for receiving a timed common power signal, a delay element for delaying a clock signal received on a second input terminal, the delay element for outputting a delayed clock signal on a output terminal, a switching element for switching the common timed power signal to the load, the switching under control of the delayed clock signal.
In another aspect, the invention relates to a method for independently controlling a single load among a plurality of loads, according to claim 10.
a shows a generic scheme of a subcircuit for forming a circuit according to the present invention.
b shows a scheme of a subcircuit for forming a circuit according to an embodiment of the present invention.
a shows a generic scheme of a subcircuit 100 for forming a circuit according to the present invention. The subcircuit comprises a first input terminal 10 for receiving a timed common power signal and a second input terminal 20 for receiving a clock signal with frequency ƒ. The clock signal is output with a predetermined phase delay by delay element 22 to output 30 which is also connected to switching element 40 for switching the load. The switching element 40 is further coupled with the timed common power signal, and has a switching output 50 for being connected with a load. In
Subcircuit 100 is configured to couple the switching output 50 with input 10, when a low value of the timed common power signal on input 10 coincides with a high value of the delayed clock signal at output 30. At that coincidence the load is powered by the voltage difference of the power supply line and the timed common power signal.
b shows an embodiment of the subcircuit 100 of
In order to avoid reflection of the clock signal, the cascade circuit is provided with an inductor 93 and a resistance 96 coupled to the last output terminal Resistance 96 is referred to as “terminal resistance” in the art. In a practical embodiment of the circuit of
The circuit is fed with a supply voltage of 10 Volts, and the timed common power signal has a duty cycle of 10%.
When the number of loads becomes large, for example about 50, it is also possible to use other than purely sinusoidal waveforms, for example square waves, which create pulses that rise steeper than the sinusoidals, enabling a more selective control of the switching element. These waveforms can be composed of multiple superimposed sinusoidals with different frequencies.
These waveforms, as well as the timing signals, can be accurately generated using simple electronics making use of the direct digital synthesis method. For generation of smooth waveforms, like sinusoidals, additional low-pass filters, such as RC filters may be used.
As required, a detailed embodiment of the present invention is disclosed herein; however, it is to be understood that the disclosed embodiment is merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention. The terms “a” or “an”, as used herein, are defined as one or more than one.
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06116818 | Jul 2006 | EP | regional |
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Number | Date | Country | |
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20120235590 A1 | Sep 2012 | US |
Number | Date | Country | |
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Parent | 12306736 | US | |
Child | 13487305 | US |