Patent Application
20190245545
The present invention basically relates to the technical field of clock and/or data recovery (CDR); in particular, the present invention relates to a device for controllably delaying an electrical signal as well as to an oscillator ring comprising at least one such device.
Furthermore, the present invention relates to a method for controlling the delay of an electrical signal as well as to this delay of the electrical signal by at least one such device and/or by at least one such oscillator ring.
Finally, the present invention relates to the use of at least one such device and/or of at least one such oscillator ring and/or of at least one such method.
Regarding the technological background of the present invention, attention is drawn at first to the documents WO 2013/174377 A2 and WO 2013/189494 A2.
In the document WO 2013/174377 A2, a circuit arrangement and a method for calibrating at least one activation signal provided for a voltage-controlled oscillator for clock and data recovery are disclosed.
Reference is made in particular to circuits for clock and data recovery or CDR circuits with binary phase detectors wherein the phase detector can output two digital phase detector output signals “up” (for accelerating) and “down” (for delaying).
The circuit arrangement according to the document WO 2013/174377 A2 assumes a voltage-controlled ring oscillator with two tuning inputs wherein the frequency of the ring oscillator can be set separately via the two tuning inputs. The frequency change is adjusted by four separate varactor(-diode)s.
A disadvantage of this oscillator is its low output frequency because four varactors are required so that more parasitic capacitance is generated in the oscillator.
In order to increase the output frequency as much as possible, it is proposed according to the document WO 2013/174377 A2 to embody the circuit arrangement for calibrating the activation signal provided for a voltage-controlled oscillator for clock and data recovery with at least one calibration oscillator, at least one reference oscillator assigned to the calibration oscillator, at least one clock counter connected downstream of the calibration oscillator and of the reference oscillator and at least one digital-to-analog converter connected downstream of the clock counter wherein the clock counter is embodied for counting the respective clock number of the calibration oscillator and of the reference oscillator as well as for integrating a clock error resulting from the difference between these two clock numbers, and the digital-to-analog converter for converting the clock error into analogue tuning signals from which the calibrated activation signal is derivable.
The voltage-controlled oscillator is driven in such way that in the voltage-controlled oscillator not four but only two varactor(-diode)s are required, the frequency change no longer being achieved with two activation signals but only with one activation signal but both the reference oscillator and the calibration oscillator, however, also continuing to each contain four varactor(-diode)s.
From the document WO 2013/189494 A2, a circuit arrangement and a method for clock and/or data recovery are known wherein a voltage-controlled ring oscillator is used. Such a ring oscillator, implemented in the form of four voltage-controlled oscillator buffer stages, and implementations of such voltage-controlled oscillator buffer stages are shown.
Such a voltage-controlled oscillator buffer stage comprises four varactors whose capacitance values are adjustable via two tuning voltages up and dnb that can be fed to the anodic pairwise connections of the varactors and which determine the oscillation frequency of the ring oscillator.
With their capacitive load, the varactors serve as frequency (co-)determining elements of the frequency variation.
Since in particular two slightly different voltages are to be adjusted, the varactors are operated in two operating points:
If no frequency variation upwards or downwards is to take place, the varactors are operated at an operating point of medium capacity. This capacity, however, reduces the maximum achievable frequency of the oscillator.
In addition, the insertion of the varactors into the signal path of the oscillator alone leads due to the additional wiring to an increase in parasitic capacitive loads, which also reduce the maximum achievable frequency of the oscillator.
Starting from the above-explained disadvantages and shortcomings as well as taking the outlined prior art into account, the object of the present invention is to prevent or at least reduce parasitic capacitive loads.
This object is achieved by a device according to the present invention with the herein described features, by an oscillator ring according to the present invention with the herein described features, and by a method according to the present invention with the herein described features. Advantageous embodiments and expedient further developments of the present invention are characterized in the respective dependent claims.
This object is achieved by a device for controllably delaying an electrical signal, the device comprising
This object is further achieved by an embodiment of the device according to the present invention, wherein
This object is further achieved by an embodiment of the device according to the present invention, further comprising a first current modulation stage for adjusting the quiescent current of the first quiescent current source and a second current modulation stage for adjusting the quiescent current of the third quiescent current source.
This object is further achieved by an embodiment of the device according to the present invention, further comprising a first current modulation stage for adjusting the quiescent current of the first quiescent current source and a third current modulation stage for adjusting the quiescent current of the second quiescent current source.
This object is further achieved by an embodiment of the device according to the present invention, wherein the first and/or second and/or third current modulation stage is/are designed to supply and feed a respective additional current into the quiescent current setting of the first and/or second and/or third quiescent current source.
This object is further achieved by an embodiment of the device according to the present invention, wherein the first and/or second and/or third current modulation stage is respectively provided
This object is further achieved by an embodiment of the device according to the present invention, wherein
This object is further achieved by an embodiment of the device according to the present invention, wherein
This object is further achieved by an embodiment of the device according to the present invention, wherein
This object is further achieved by an embodiment of the device according to the present invention, wherein in the first and/or second and/or third current modulation stage, respectively, the first and the second current modulation quiescent current source are designed for supplying and feeding the respective additional current, controlled by the first and second control signal, into a quiescent current setting of the first and/or second and/or third quiescent current source, respectively.
This object is further achieved by an embodiment of the device according to the present invention, further comprising
This object is further achieved by an embodiment of the device according to the present invention, wherein
This object is further achieved by an oscillator ring, comprising at least one device of the type described above.
This object is further achieved by a method for controlling the delay of an electrical signal and for said delaying the electrical signal by at least one device of the type described above and/or by at least one oscillator ring of the type described above,
This object is further achieved by a use of at least one device of the type described above and/or of at least one oscillator ring of the type described above and/or of at least one method of the type described above in the clock and/or data recovery by at least one digital phase detector wherein from the at least one digital phase detector a discretized signal for frequency increase is supplied as a first control signal and/or a discretized signal for frequency reduction is supplied as a second control signal.
In other words, the present invention provides a device for controllably delaying an electrical signal, the device comprising:
According to an advantageous embodiment of the present invention, the above object is further achieved by a device with a first current modulation stage for adjusting the quiescent current of the first quiescent current source and a second current modulation stage for adjusting the quiescent current of the third quiescent current source.
According to a further advantageous embodiment of the present invention, the above object is also achieved by a device with a first current modulation stage for adjusting the quiescent current of the first quiescent current source and a third current modulation stage for adjusting the quiescent current of the second quiescent current source.
In an advantageous embodiment of the present invention, the above object is further achieved by a device which is characterized in that the first and/or second and/or third current modulation stage are/is respectively provided with
According to a further embodiment of the present invention, the above object is advantageously achieved by a device in which the first and/or second and/or third current modulation stage is/are designed to supply and feed a respective additional current into the quiescent current setting of the first and/or second and/or third quiescent current source.
According to another advantageous embodiment of the present invention, the above object is achieved by a device which is characterized in that in the first and/or second and/or third current modulation stage, respectively, the first and the second current modulation quiescent current source are designed for supplying and feeding the respective additional current, controlled by the first and second control signal, into a quiescent current setting of the first and/or second and/or third quiescent current source, respectively.
The above object is further achieved by an oscillator ring which comprises at least one device of the type described above.
Furthermore, the above object is achieved by a method for controlling the delay of an electrical signal and for said delaying the electrical signal by at least one device of the type described above and/or by at least one oscillator ring of the type described above wherein said method is characterized in that
The above object is besides achieved by a use of at least one device of the type described above and/or of at least one oscillator ring of the type described above and/or of a method of the type described above in the clock and/or data recovery by at least one digital phase detector wherein from the at least one digital phase detector a discretized signal for frequency increase is supplied as a first control signal and/or a discretized signal for frequency reduction is supplied as a second control signal.
With regard to exemplary technical application areas of the present oscillator with frequency switching, it has to be taken into account, in particular for applications in clock recovery circuits (CDR=Clock and/or Data Recovery) with binary phase detector, that only small frequency variations with respect to a medium frequency are necessary so that here the desired frequency variation can be achieved advantageously only with the slight variation of the operating current of the oscillator differential stages, i.e. of the first and/or the second signal transfer stage, and/or of the internal delay stage.
Further exemplary technical application fields are:
As already discussed hereinbefore, there are various possibilities for embodying and further developing the teaching of the present invention in an advantageous manner. To this end, on the one hand reference is made to the explanations above as well as to the dependent claims, on the other hand further embodiments, features and advantages of the present invention are explained in greater detail hereinafter, inter alia based upon the exemplary embodiments illustrated by
It is shown in:
Like, similar or corresponding embodiments, elements or features are provided with identical reference numerals in
At this point it should be mentioned that a delay stage, embodied with only a first differential pair and a second differential pair as well as an internal delay stage and a common resistive load, corresponds to the state of the art, shown for example in the monograph by Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, pages 518 and 519,
According to
Thus, the delay of the interpolating delay stage varies overall by variation of the control voltage between the extreme values determined by the delays of the first differential pair on the one hand—of the fast first signal transfer path—and of the interconnection of the second differential pair with the internal delay stage on the other hand—of the slow second signal transfer path—.
The frequency variation thus obtained between the minimum oscillation frequency of a ring oscillator embodied with such an interpolating delay stage when only the slow, second signal transfer path is switched on, and its maximum oscillation frequency when only the fast, first signal transfer path is switched on, however, goes far beyond the above-mentioned only small frequency variations in relation to a medium frequency.
Current modulation stages are added to that according to the invention for adjusting the quiescent currents of at least one of the quiescent current sources, i.e. for adjusting
Advantageously, these further differential stages are arranged as a first current modulation stage for setting the quiescent current of the first quiescent current source (=first current modulation) and as a second current modulation stage for setting the quiescent current of the third quiescent current source (=second current modulation) for modulation of the quiescent current of the first differential pair (=first current modulation) or of the internal delay stage (=second current modulation), as shown in
In another embodiment of the present invention, not shown in the figures, these further differential stages are arranged advantageously as the first current modulation stage for setting the quiescent current of the first quiescent current source (=first current modulation) and as a third current modulation stage for setting the quiescent current of the second quiescent current source (=third current modulation) for modulation of the quiescent current of the first differential pair (=first current modulation) or of the second differential pair (=third current modulation).
Still another embodiment of the present invention, also not shown in the figures, comprises a first current modulation stage for setting the quiescent current of the first quiescent current source (=first current modulation), a second current modulation stage for setting the quiescent current of the third quiescent current source (=second current modulation) and a third current modulation stage for setting the quiescent current of the second quiescent current source (=third current modulation).
The devices according to the figures of the drawing are now described in more detail, with identical drawing elements comprising the same reference numerals and a repeated description of these drawing elements being omitted in order to avoid unnecessary repetitions. With regard to the configurations, features and advantages of the present invention, he following explanations thus refer—unless stated otherwise—to all embodiments of the present invention illustrated by
Such a delay stage 200 is hereinafter referred to as the device for controllable delay of an electrical signal according to the invention. The delay stage 200 is for example embodied as interpolating delay stage 200, as is shown by
Each of the four delay stages 200 comprises a differential input 201 with two input terminals 202, 203 and a differential output 204 with two output terminals 205, 206.
An electrical signal supplied to differential input 201 is output at the differential output 204 with defined, adjustable delay. For this electrical signal, the delay stage 200 forms an electrical quadripole.
Four of these quadripoles, i.e. the four delay stages 200, are interconnected in
At an end of the cascade connection, the differential output 204 of the last of the delay stages 200 is cross-connected with the differential input 201 of the first of the delay stages 200. This forms the oscillator ring on the one hand, and on the other hand the electrical signal from the differential output 204 of the last of the delay stages 200 is fed in reversed polarity to the differential input 201 of the first of the delay stages 200.
In this way, the electrical signal passes through the cascade connection in alternating polarity and thus oscillates at the differential inputs 201 and the differential outputs 204 at a frequency determined by the sum of the delays of all delay stages 200 of the cascade connection.
The delay stage 200 according to
The first signal transfer path 207 comprises a first signal transfer stage 208 with a first differential pair 209 of source-coupled transistors 210, 211 and a common, adjustable first quiescent current source 212. The delay stage 200 is further configured with a second signal transfer path 213 between the differential input 201 and the differential output 204.
The second signal transfer path 213 comprises a second signal transfer stage 214 with a second differential pair 215 of source-coupled transistors 216, 217 and a common adjustable second quiescent current source 218, and an internal delay stage 219 arranged between the differential input 201 and the second signal transfer stage 214 with a third differential pair 220 of source-coupled transistors 221, 222 and a common adjustable third quiescent current source 223.
All transistors of the first signal transfer path 207 and of the second signal transfer path 213, i.e. the first and the second source-coupled transistor 210, 211 of the first differential pair 209 as well as the common, adjustable first quiescent current source 212 common to the first differential pair 209, the first and the second source-coupled transistor 216, 217 of the second differential pair 215 as well as the adjustable second quiescent current source 218 common to the second differential pair 215 and the first and the second source-coupled transistors 221, 222 of the third differential pair 220 as well as the adjustable third quiescent current source 223 common to the third differential pair 220 are formed as NMOS field-effect transistors in the shown embodiment of the present invention.
The delay stage 200 is further provided with a signal combination stage 224 for additive superposition of the electrical signal transmitted via the first signal transfer path 207 with the electrical signal transmitted via the second signal transfer path 213.
Therefor, the signal combination stage 224 is provided with a resistive load common to the first differential pair 209 of the first signal transfer stage 208 and the second differential pair 215 of the second signal transfer stage 214 and comprising a first work resistor 225 and a second work resistor 226.
The first work resistor 225 of the signal combination stage 224 is connected on the one hand with a first connection point 227 of the drain terminals of the first source-coupled transistor 210 of the first differential pair 209 of the first signal transfer stage 208 and of the first source-coupled transistor 216 of the second differential pair 215 of the second signal transfer stage 214 and on the other hand with a first supply voltage terminal 229 carrying a first supply voltage potential VDD.
The second work resistor 226 of the signal combination stage 224 is connected on the one hand with a second connection point 228 of the drain terminals of the second source-coupled transistor 211 of the first differential pair 209 of the first signal transfer stage 208 and of the second source-coupled transistor 217 of the second differential pair 215 of the second signal transfer stage 214 and on the other hand with the first supply voltage terminal 229.
The first and second connection points 227, 228 each form a current node for the additive superposition of the currents in the drain terminals of the first source-coupled transistors 210, 216 and of the second source-coupled transistors 211, 217.
A voltage proportional to the additively superimposed currents in the drain terminals then respectively occurs at the work resistors; both voltages together form a differential signal at the differential output 204 of delay stage 200.
The internal delay stage 219 also comprises two work resistors, namely a third work resistor 230 which is connected, on the one hand, with a third connection point 232 of the drain terminal of the first source-coupled transistor 221 of the third differential pair 220 of the internal delay stage 219 and of the gate terminal of the first source-coupled transistor 216 of the second differential pair 215 of the second signal transfer stage 214 and, on the other hand, with the first supply voltage terminal 229, and a fourth work resistor 231 which is connected, on the one hand, with a fourth connection point 233 of the drain terminal of the second source-coupled transistor 222 of the third differential pair 220 of the internal delay stage 219 and of the gate terminal of the second source-coupled transistor 217 of the second differential pair 215 of the second signal transfer stage 214 and, on the other hand, with the first supply voltage terminal 229.
The first quiescent current source 212 is connected on the one hand with the interconnected source terminals of the first differential pair 209 of source-coupled transistors 210, 211 of the first signal transfer stage 208 and on the other hand with a second supply voltage terminal 234 carrying a second supply voltage potential VSS.
The second quiescent current source 218 is connected on the one hand with the interconnected source terminals of the second differential pair 215 of source-coupled transistors 216, 217 of the second signal transfer stage 214 and on the other hand with the second supply voltage terminal 234.
The third quiescent current source 218 is connected on the one hand with the interconnected source terminals of the third differential pair 220 of source-coupled transistors 221, 222 of the internal delay stage 219 and on the other hand with the second supply voltage terminal 234.
Advantageously, the quiescent current settings of the quiescent current sources 212, 218, 223 for the first, second and third differential pair 209, 215 and 220, respectively, can be carried out by control voltages to be supplied to the gate terminals of the NMOS field effect transistors forming the quiescent current sources 212, 218 and 223; in particular, ground potential is selected as second supply voltage potential VSS, and a positive voltage potential with respect to ground is selected as first supply voltage potential VDD.
According to the embodiment described, the device according to
In an unshown variation of this embodiment, a third current modulation stage may additionally be provided for setting the quiescent current of the second quiescent current source 218, the structure of this third current modulation stage being at least substantially identical to that of the first current modulation stage 235 and of the second current modulation stage 236.
Furthermore, variations are possible in which either only the first, second or third current modulation stage is provided, or only the first and the third current modulation stages, or only the second and the third current modulation stages. All these variations solve the problem of the present invention. As an example, only the embodiment according to
In the embodiment according to
The drain terminals of the second source-coupled transistor 242 of the first differential stage 237 of the first current modulation stage 235 and of the first source-coupled transistor 243 of the second differential stage 238 of the first current modulation stage 235, as well as of the second source-coupled transistor 246 of the first differential stage 239 of the second current modulation stage 236 and of the first source-coupled transistor 247 of the second differential stage 240 of the second current modulation stage 236 are connected with the second supply voltage terminal 234 carrying the second supply voltage potential VSS.
The drain terminals of the first source-coupled transistor 241 of the first differential stage 237 of the first current modulation stage 235 and of the second source-coupled transistor 244 of the second differential stage 238 of the first current modulation stage 235 are connected with each other and with a fifth connection point 249 of the coupled source terminals of the first source-coupled transistor 210, and of the second source-coupled transistor 211 of the first differential pair 209 of the first signal transfer stage 208 with the first quiescent current source 212 to the first differential pair 209 of the first signal transfer stage 208.
The drain terminals of the first source-coupled transistor 245 of the first differential stage 239 of the second current modulation stage 236 and of the second source-coupled transistor 248 of the second differential stage 240 of the second current modulation stage 236 are connected with each other and with a sixth connection point 250 of the coupled source terminals of the first source-coupled transistor 221 and the second source-coupled transistor 222 of the third differential pair 220 of the internal delay stage 219 with the third quiescent current source 223 to the third differential pair 220 of the internal delay stage 219.
In the first current modulation stage 235, the source terminals of the first source-coupled transistor 241 and of the second source-coupled transistor 242 of the first differential stage 237 are connected with each other and with the drain terminal of a transistor forming a fourth quiescent current source 251 comprised by the first current modulation stage 235, and further the source terminals of the first source-coupled transistor 243 and of the second source-coupled transistor 244 of the second differential stage 238 are connected with each other and with the drain terminal of a transistor forming a fifth quiescent current source 252 comprised by the first current modulation stage 235.
The source terminals of the transistors forming the fourth and the fifth quiescent current sources 251, 252 are connected with the first supply voltage terminal 229 carrying the first supply voltage potential VDD.
The gate terminals of the transistors forming the fourth and the fifth quiescent current sources 251, 252 are connected with a common control voltage terminal 255, via which a common control voltage is supplied in operation to the fourth and the fifth quiescent current sources 251, 252 for setting an, in particular matching, quiescent current in the fourth and the fifth quiescent current sources 251, 252. The fourth and the fifth quiescent current sources 251, 252 thus comprise a common quiescent current setting by the common control voltage at the gate terminals.
In the same way, in the second current modulation stage 236, the source terminals of the first source-coupled transistor 245 and of the second source-coupled transistor 246 of the first differential stage 239 are connected with each other and with the drain terminal of a transistor forming a sixth quiescent current source 253 comprised by the second current modulation stage 236, and further the source terminals of the first source-coupled transistor 247 and of the second source-coupled transistor 248 of the second differential stage 240 are connected with each other and with the drain terminal of a transistor forming a seventh quiescent current source 254 comprised by the second current modulation stage 236.
The source terminals of the transistors forming the sixth and the seventh quiescent current sources 253, 254 are also connected with the first supply voltage terminal 229 carrying the first supply voltage potential VDD.
Accordingly, the gate terminals of the transistors forming the sixth and the seventh quiescent current sources 253, 254 are connected with a common control voltage terminal 256 via which a common control voltage is supplied in operation to the sixth and the seventh quiescent current sources 253, 254 for setting an, in particular matching, quiescent current in the sixth and the seventh quiescent current sources 253, 254. The sixth and the seventh quiescent current sources 253, 254 thus comprise a common quiescent current setting by the common control voltage at the gate terminals.
All transistors in the first and the second current modulation stages 235 and 236 are embodied as PMOS field effect transistors in the embodiment according to
The two differential stages 237, 238 or 239, 240 of each of the current modulation stages 235 or 236 are controlled by control signals at the gate terminals of the source-coupled transistors 241, 242 or 243, 244 or 245, 246 or 247, 248 of the differential stages 237 or 238 or 239 or 240.
These control signals at the gate terminals of the source-coupled transistors 241, 242 or 243, 244 or 245, 246 or 247, 248 are preferably discretized control signals which can preferably be supplied by a digital phase detector.
The control signals from the phase detector usually consist of a discretized signal for frequency increase (in
In particular, in the embodiment according to
The common control voltage or common control voltages at the common control voltage terminals 255 and/or 256, respectively, is/are selectable independently of the control voltages to be supplied to the gate terminals of the NMOS field effect transistors forming the quiescent current sources 212, 218 and 223 for the quiescent current settings of the quiescent current sources 212, 218, 223 for the first, second and third differential pair 209, 215 and 220, respectively.
This and mutually independent dimensioning of the transistors of the first to third quiescent current sources 212, 218, 223 and of the transistors of the fourth to seventh quiescent current sources 251, 252, 253, 254 make it possible to set the quiescent currents of the fourth to seventh quiescent current sources 251, 252, 253, 254 independently of the quiescent currents of the first to third quiescent current sources 212, 218, 223, for example to lower current intensities.
During operation of the ring oscillator 100 or of the delay stage 200, the quiescent currents of the fourth to seventh quiescent current sources 251, 252, 253, 254 are fed, controlled by the signal for frequency increase up/upb and the signal for frequency reduction dn/dnb, selectively to the fifth connection point 249 of the coupled source terminals of the first source-coupled transistor 210 and of the second source-coupled transistor 211 of the first differential pair 209 of the first signal transfer stage 208 with the first quiescent current source 212 to the first differential pair 209 of the first signal transfer stage 208 or to the sixth connection point 250 of the coupled source terminals of the first source-coupled transistor 221 and of the second source-coupled transistor 222 of the third differential pair 220 of the internal delay stage 219 with the third quiescent current source 223 to the third differential pair 220 of the internal delay stage 219, respectively.
This results in a—compared to the quiescent currents of the first and of the third quiescent current sources 212 and 223 preferably small—change in the quiescent currents of the first and of the third quiescent current sources 212, 223 of the first differential pair 209 of the source-coupled transistors 210, 211 or of the third differential pair 220 of the source-coupled transistors 221, 222 by at least one of the fourth to seventh quiescent current sources 251, 252, 253, 254.
This corresponds to a current modulation at the coupled source terminals of the transistors 210, 211 or 221, 222, respectively caused by the signals for frequency increase up/upb or for frequency reduction dn/dnb, i.e. the quiescent currents resulting in the coupled source terminals of the transistors 210, 211 or 221, 222 are, preferably slightly with respect to the quiescent currents of the first and of the third quiescent current sources 212 and 223, varied by the signals for frequency increase up/upb and frequency reduction dn/dnb, respectively.
The differential stages 237, 238 of the first current modulation stage 235 and the differential stages 239, 240 of the second current modulation stage 236 provide in this way for a slight quantized, i.e. so to speak digital current modulation achieved with this current modulation, and lead therefore essentially by the modulation of the transconductances of the source-coupled transistors 210, 211 in the first differential pair 209 and of the source-coupled transistors 221, 222 in the third differential pair 220 of the internal delay stage 219—and/or in the second differential pair 215 according to one of the aforementioned variations of the embodiment—, respectively, to a modulation of the delay of the signal in the first and second and third differential pairs 209 and 215 and 220, respectively, and thus to a corresponding modulation of the oscillation frequency of the oscillator 100.
This type of quantized frequency modulation is in particular applicable with advantage for CDRs with digital phase detectors. The control signals for the modules of the first current modulation stage 235 for the first current modulation and of the second current modulation stage 236 for the second current modulation are fed from the phase detector of the CDR.
With the mentioned control signals up/upb, dn/dnb from the phase detector, three cases [a], [b] and [c] are distinguished:
case [a]: Increasing the frequency compared to medium frequency by up=1 and dn=0;
case [b]: Reducing the frequency compared to frequency by up=0 and dn=1;
case [c]: Maintaining the medium frequency by up=0 and dn=0.
The first differential stage 237, to which the frequency increase signal up/upb is fed, and the second differential stage 238, to which the frequency reduction signal dn/dnb is fed, of the first current modulation stage 235 do not feed current into the quiescent current setting of the first differential pair 209 of source-coupled transistors 210, 211.
Thus the whole quiescent current of the first quiescent current source 212 is available to the first differential pair 209, the transconductance of the source-coupled transistors 210, 211 of the first differential pair 209 is maximized, which results in maximized oscillation frequency of the oscillator ring, i.e. of the ring oscillator 100.
The same applies to the effect of the first and second differential stages 239 and 240, respectively, to which the frequency increase signal up/upb and the frequency reduction signal dn/dnb is also fed, of the second current modulation stage 236 on the quiescent current setting of the internal delay stage 219.
The first and the second differential stages 237, 238, which in turn are driven by the frequency increase signal up/upb and the frequency reduction signal dn/dnb, of the first current modulation stage 235 feed an additional current, i.e. the quiescent currents of the fourth quiescent current source 251 and of the fifth quiescent current source 252, via the first source-coupled transistor 241 of the first differential stage 237 and the second source-coupled transistor 244 of the second differential stage 238 into the quiescent current setting of the first differential pair 209 of the source-coupled transistors 210, 211.
Thus the quiescent current of the first differential pair 209 is reduced by this current, i.e. by the current sum of the quiescent currents of the fourth quiescent current source 251 and of the fifth quiescent current source 252, the transconductance of the first differential pair 209 is reduced, which results in reduced oscillation frequency of the oscillator ring 100.
The same applies to the effect of the first and second differential stages 239 and 240, respectively, to which the frequency increase signal up/upb and the frequency reduction signal dn/dnb is also fed, of the second current modulation stage 236 on the quiescent current setting of the internal delay stage 219.
The first differential stage 237 is again driven by the frequency increase signal up/upb. The first current modulation stage 235 feeds an additional current, i.e. the quiescent current of the fourth quiescent current source 251, via the first source-coupled transistor 241 of the first differential stage 237 into the quiescent current setting of the first differential pair 209 of the source-coupled transistors 210, 211, whereas the second differential stage 238, which is driven by the frequency reduction signal dn/dnb, does not.
Therefore, for the quiescent current setting of the first differential pair 209 of the source-coupled transistors 210, 211, a situation occurs halfway between the cases [a] and [b], leading to the setting of a medium oscillator frequency.
The same applies to the effect of the first and second differential stages 239 and 240, respectively, to which the frequency increase signal up/upb and the frequency reduction signal dn/dnb are also fed, of the second current modulation stage 236 on the quiescent current setting of the internal delay stage.
An essential advantage of the present invention is that no parasitic capacitances, in particular no parasitic capacitive loads, occur due to the insertion of frequency varying elements into the signal path of the oscillator.
A further advantage is that by variation of the quiescent current settings of the first current modulation stage 235 and of the second current modulation stage 236, the level of the frequency modulation can be adjusted in a relatively wide range.
Since, for example, when used in a CDR (=Clock and/or Data Recovery), the level of the frequency modulation determines the bandwidth of the CDR, the bandwidth of a CDR can additionally be varied without further intervention in the signal path of the oscillator 100, which reacts sensitively to additional parasitic elements.
In the state of the art mentioned above, this would only be possible by adding further varactors to the signal path. However, this is not possible without adding additional parasitic wiring capacitors, which reduces the maximum oscillation frequency of the oscillator.
In contrast thereto, the present invention avoids or at least reduces capacitive loads in the signal transfer paths. As delay stage in a ring oscillator, the device according to the present invention enables higher oscillation frequencies.
While this invention has been described as having a preferred design, it is understood that it is capable of further modifications, and uses and/or adaptations of the invention and following in general the principle of the invention and including such departures from the present disclosure as come within the known or customary practice in the art to which the invention pertains, and as may be applied to the central features hereinbefore set forth, and fall within the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2016 113 031.1 | Jul 2016 | DE | national |
| 10 2017 114 602.4 | Jun 2017 | DE | national |
This application is a continuation of international (WO) patent application no. PCT/DE2017/100578, filed 12 Jul. 2017, which claims the priority of German (DE) patent application no. 10 2016 113 031.1, filed 14 Jul. 2016, and of German (DE) patent application no. 10 2017 114 602.4, filed 29 Jun. 2017, the respective contents of each being hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/DE2017/100578 | Jul 2017 | US |
| Child | 16247289 | US |
