The present disclosure generally relates to a device and a method for controlling electrodes of a display panel, especially but not exclusively of a plasma display panel, which are used during display panel addressing phases.
A memory-effect A.C. plasma display panel generally comprises two parallel plates separated by a space containing a discharge gas. The plates are provided on their internal surfaces with electrode networks covered with a dielectric layer, which define image elements or pixels.
All common line electrodes Elcom are connected to a same voltage source Com. Each line scan electrode Els is associated with a line electrode control circuit comprising, for example, a first switch Tlh capable of connecting line scan electrode Els to a high line reference voltage Vscan and a second switch Tll capable of connecting line scan electrode Els to a low line reference voltage Vbw. Each column electrode Ec is associated with a column electrode control circuit comprising, for example, a first switch Tdh capable of connecting column electrode Ec to a high column reference voltage Vpp and a second switch Tdl capable of connecting column electrode Ec to a low column reference voltage, for example, ground GND.
When the plasma panel is in operation, to display an image, a succession of scannings, or even of sub-scannings, of the pixel array is performed to activate or not certain array pixels. Each scanning or sub-scanning for example comprises the following steps:
More specifically, in an addressing phase, the lines are successively addressed by placing the corresponding line scan electrode Els at voltage Vbw, the other line electrodes being maintained at voltage Vscan. For each selected line, the column electrodes Ec of the columns for which the pixels of the selected line are desired to be addressed are set to voltage Vpp, the other column electrodes being maintained at ground GND.
The panel is seen by each electrode as a capacitor which is charged or discharged in addressing and sustain steps at high voltages and frequencies. As an example, the high reference voltages of the column electrodes are generally greater than 50 volts and the addressing frequencies are generally greater than 100 kilohertz. A disadvantage of previously-described circuits for controlling column electrodes Ec is that the power lost at column electrodes Ec by the panel, which may exceed 100 watts, is essentially dissipated in the switches of the column electrode control circuits. It may be difficult to efficiently carry off the generated heat, in particular when the switches of the column electrode control circuits are made in integrated form.
To decrease power losses, a column electrode control circuit based on a resonant circuit where, for each column electrode Ec, the capacitor representative of the panel capacitance is put in resonance with an inductance around a given voltage, may be used. Theoretically, a resonant control circuit enables decreasing power losses on addressing of the column electrodes with respect to the column electrode control circuits shown in
However, with certain resonant control circuits, a decrease in power losses is actually only obtained for the display of images for which the pixels to be addressed and not to be addressed in the panel are relatively equally distributed. Such resonant control circuits may even result in power losses greater than those obtained with the control circuits of
Embodiments provide a device and a method for controlling control electrodes of a display panel, especially a plasma panel, enabling decreasing power losses in panel addressing.
According to one embodiment, the control device comprises a decreased number of components.
One embodiment provides a method for controlling electrodes for addressing a display panel comprising pixels distributed in lines and in columns, each addressing electrode being associated with a column in the panel, each line in the panel being successively selected for the addressing of the pixels in the line, the method comprising the maintaining, at least for part of the selection of each line, of at least one addressing electrode at a given reference voltage when the pixel of the line associated with said at least one addressing electrode is to be addressed, and the setting to high impedance of said at least one addressing electrode between the successive selection of two lines having their pixels associated with said at least one addressing electrode which are to be addressed.
According to an embodiment, said at least one addressing electrode is connected to a node via a switch, the method comprising bringing, before selection of each line, the node at least from an additional reference voltage to said given reference voltage; maintaining the node at said given reference voltage during the line selection, the switch being on for at least part of the selection of the line to connect said at least one addressing electrode to the node when the pixel of the line associated with said at least one addressing electrode is to be addressed; and turning off the switch between the successive selection of two lines having their pixels associated with said at least one addressing electrode which are to be addressed to set said at least one addressing electrode to high impedance.
One embodiment also provides a device for controlling electrodes for addressing a display panel comprising pixels distributed in lines and in columns, each addressing electrode being associated with a column in the panel, each line in the panel being successively selected for the addressing of the pixels in the line, the device comprising means for maintaining, at least for part of the selection of each line, at least one addressing electrode at a given reference voltage when the pixel of the line associated with said at least one addressing electrode is to be addressed; and means for setting to high impedance said at least one addressing electrode between the successive selection of two lines having their pixels associated with said at least one addressing electrode which are to be addressed.
According to an embodiment, said at least one addressing electrode is connected to a node via a switch, the device further comprising a circuit designed for, before selection of each line, bringing the node at least from an additional reference voltage to said given reference voltage and maintaining the node at said given reference voltage during the line selection; means for controlling the turning-on of the switch for at least part of the selection of the line to connect said at least one addressing electrode to the node when the pixel of the line associated with said at least one addressing electrode is to be addressed; and means for controlling the turning-off of the switch between the successive selection of two lines having their pixels associated with said at least one addressing electrode which are to be addressed, to set said at least one addressing electrode to high impedance.
According to an embodiment, the switch comprises a first MOS transistor comprising a first power terminal connected to the node and a second power terminal, the bulk of the first transistor being connected to said second power terminal, and a second MOS transistor comprising a third power terminal connected to the second power terminal and a fourth power terminal connected to said at least one addressing electrode, the bulk of the second MOS transistor being connected to the third power terminal.
According to an embodiment, the gates of the first and second transistors are connected in common.
According to an embodiment, the device comprises a resonant circuit comprising a source of another additional reference voltage connected to the node via an inductance.
According to an embodiment, said at least one addressing electrode is connected to a source of the additional reference voltage via an additional switch.
The foregoing and other features will be discussed in detail in the following non-limiting and non-exhaustive description of specific embodiments in connection with the accompanying drawings.
In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.
For clarity, the same elements have been designated with the same reference numerals in the different drawings.
Control circuit 10 comprises a common control circuit 12 which is, generally, connected to an optimum number of column electrodes. As an example, only two column electrodes Ecn and Ecn+1 have been shown in
Circuit 10 comprises, for each column electrode Ec, a dedicated circuit 14 comprising a switch Tdh capable of connecting column electrode Ec to node E and a switch Tdl capable of connecting column electrode Ec to ground GND.
Capacitor C1 is charged up to voltage Vpp/2. The operating principle of circuit 10 is to have, for each column electrode Ec, capacitor C representative of the capacitance of the panel as seen from column electrode Ec resonate with inductance L around the voltage across capacitor C1. The voltage across capacitor C1 is automatically maintained substantially at Vpp/2 by the power transfers occurring on operation of control circuit 10.
In the present example, it is desired to only address the pixel associated with column electrode Ecn+1 on selection of the first line, and it is desired to only address the pixel associated with column electrodes Ecn and Ecn+1 on selection of the second line.
At time t1, switches Tdhn and Tdln+1 are on and switches Tdln and Tdhn+1 are off, given that it is only desired to address the pixel associated with column electrode Ecn. The addressing step starts with the turning-on of switch Tup, switches Trh, Trl, and Tdown being off. A positive current IL flows through inductance L, causing a rise in voltage VE from 0 volt up to Vpp. A rise in voltage Vcn from 0 to Vpp is thus obtained while voltage Vcn+1 is maintained at 0 volt.
At time t2, current IL cancels when voltage VE has almost reached Vpp. Diode D2 then prevents the flowing of a negative current IL. Diode D4 enables avoiding a discontinuity in the current when D2 cuts off the current by maintaining the voltage of node D at Vpp. Switch Tup is then turned off. Voltage VE is maintained at Vpp by turning on switch Trh.
At time t3, corresponding to the end of the addressing of the pixel of the first line associated with column electrode Ecn, switch Trh is turned off and switch Tdown is turned on. A negative current IL then flows through inductance L, causing a decrease in voltage VE from Vpp to 0 volt. Switch Tdhn being on, voltage Vcn also decreases from Vpp to 0 volt. Switch Tdln+1 being on, voltage Vcn+1 is maintained at 0 volt.
At time t4, when voltage VE has almost reached 0 volt, current IL cancels. Diode D1 prevents the flowing of a positive current IL. Diode D3 enables avoiding a discontinuity in the current when D1 cuts off the current by maintaining the voltage at node D at 0 volt. Switch Tdown is turned on and switch Trl is turned off to maintain voltage VE at 0 volt.
At time t5, switch Tdhn is maintained on and switch Tdln is maintained off given that, on selection of the second line, the corresponding pixel associated with column electrode Ecn is to be addressed. Further, switch Tdhn+1 is turned on and switch Tdln+1 is turned off given that, on selection of the second line, the pixel associated with column electrode Ecn+1 is to be addressed.
At times t5 and t6, on selection of the second line, switches Tup and Trh are successively turned on as previously described for times t1 and t2. Since switches Tdhn and Tdhn+1 are turned on, voltages Vcn and Vcn+1 increase from 0 volt to Vpp. Finally, at the end of the addressing of the pixels of the second line, from time t7 to time t8, switch Tdown is turned on to lower voltage VE from Vpp to 0 volt.
The previously-described method for controlling circuit 10 is advantageous for the display of an image in which the pixels of a same column associated with two successively-selected lines are in different states (addressed or non-addressed state). The power lost on addressing of the pixels is then lower than that lost by the column electrode control circuits shown in
One embodiment comprises, when the pixels associated with a same column electrode are to be addressed on successive selection of first and second lines, maintaining the column electrode at high impedance during the transition phase, between the end of the selection of the first line and the beginning of the selection of the second line, during which voltage VE successively varies from Vpp to 0 volt, then from 0 volt to Vpp. This enables maintaining the column electrode substantially at Vpp and thus decreasing power losses with respect to the control method of circuit 10 previously described in relation with
Between times t′1 and t′8, switches Tdln, Tdhn+1, Tdln+1, Tup, Tdown, Trh, and Trl are controlled identically to what has been previously described between times t1 and t8 in relation with
At time t′3, corresponding to the end of the addressing of the pixel of the first line associated with column electrode Ecn, switch Tdhn is turned off. Column electrode Ecn is then maintained at high impedance. Voltage Vcn thus varies little and remains substantially equal to Vpp.
Switch Tdhn is maintained off until time t′6, that is, for the entire transition phase during which voltage VE switches from Vpp to 0 volt, then from 0 volt to Vpp.
At time t′6, switch Tdhn is on. Since switch Trh is also on, column electrode Ecn is then maintained at Vpp.
Switch Tdhn is controlled, at times t′7 and t′8, identically to what has been previously described at times t7 and t8 in relation with
A diode Da assembled in parallel across transistor Ta has been shown, the cathode of diode Da being connected to node E. Diode Da corresponds to the “parasitic” diode between the first power terminal and the substrate of transistor Ta. A diode Db assembled in parallel across transistor Tb has further been shown, the cathode of diode Db being connected to column electrode Ec. Diode Db corresponds to the “parasitic” diode between the second power terminal and the substrate of transistor Tb.
The fact for the cathode of diode Db to be connected to column electrode Ec prevents the flowing of a leakage current from ground GND to node E when both transistors Ta and Tb are off while switch Tdl is off, when voltage VC is substantially equal to Vpp and voltage VE decreases from Vpp to 0 volt.
When switch Tdh′ is off, the voltage at the gates of transistors Ta and Tb is zero. Said transistors are thus on.
Specific embodiments have been described. Various alterations and modifications may be provided. In particular, although one embodiment has been described for a specific structure of resonant control circuits 10, it should be clear that it can apply to other resonant control circuit structures and even to circuits other than resonant control circuits. Indeed, one embodiment applies to any control circuit capable of varying voltage VE, to which are connected column electrodes Ec via the associated switch Tdh, between a low reference voltage and a high reference voltage, and for which voltage VE varies during the transition phase between the end of the selection of a line and the beginning of the selection of another line in the panel.
Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the embodiment(s). Accordingly, the foregoing description is by way of example only and is not intended to be limiting.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Number | Date | Country | Kind |
---|---|---|---|
0753713 | Mar 2007 | FR | national |