DEVICE AND METHOD FOR DRIVING DISPLAY PANEL

Abstract

A display driver comprises: a first grayscale line; output circuitry configured to receive a first grayscale voltage from the first grayscale line and perform digital-analog conversion on a pixel data to output a source output voltage corresponding to the pixel data, the digital-analog conversion being based on the first grayscale voltage; and first gamma assist circuitry comprising a first holding node to hold the first grayscale voltage received from the first grayscale line and configured to drive the first grayscale line based on a first voltage between the first holding node and the first grayscale line.

Description

BACKGROUND

Field

This disclosure relates to a device and method for driving a display panel.

Description of the Related Art

A display driver driving a display panel such as a liquid crystal display panel and an organic light emitting diode (OLED) display panel may be configured to output a source output voltage to a source line, which may be also referred to as a signal line or data line. To achieve image display with a high refresh rate, a display driver may be designed to reduce a setting time of a source output voltage.

SUMMARY

In one or more embodiments, a display driver comprises: a first grayscale line; output circuitry configured to receive a first grayscale voltage from the first grayscale line and perform digital-analog conversion on a pixel data to output a source output voltage corresponding to the pixel data, the digital-analog conversion being based on the first grayscale voltage; and first gamma assist circuitry comprising a first holding node to hold thereon the first grayscale voltage received from the first grayscale line and configured to drive the first grayscale line based on a first voltage between the first holding node and the first grayscale line.

In one or more embodiments, a method comprises: receiving a grayscale voltage from a first grayscale line; performing digital-analog conversion on a pixel data to output a source output voltage corresponding to the pixel data, the digital-analog conversion being based on the grayscale voltage; holding the first grayscale voltage received from the first grayscale line on a holding node; and driving the first grayscale line based on a first voltage between the holding node and the first grayscale line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates one example configuration of a display device, according to one or more embodiments;

FIG. 2 illustrates one example configuration of source driver circuitry, according to one or more embodiments;

FIG. 3 illustrates one example arrangement of gamma assist circuitry, according to one or more embodiments;

FIG. 4 illustrates one example configuration of gamma assist circuitry, according to one or more embodiments;

FIG. 5 illustrates one example operation of gamma assist circuitry, according to one or more embodiments;

FIG. 6 illustrates one example configuration of source driver circuitry, according to one or more embodiments;

FIG. 7 illustrates one example arrangement of gamma assist circuitry, according to one or more embodiments;

FIG. 8 illustrates one example configuration of a display device, according to one or more embodiments; and

FIG. 9 illustrates one example operation of gamma assist circuitry, according to one or more embodiments.

DETAILED DESCRIPTION

In the following, a description is given of embodiments of the present disclosure with reference to the attached drawings. In the attached drawings, same or similar components may be denoted by same or corresponding reference numerals. Suffixes may be attached to reference numerals to distinguish same components from each other.

In one or more embodiments, as illustrated in FIG. 1, a display device 100 comprises a display panel 1 and a display driver 2. In one or more embodiments, the display device 100 is configured to display an image on the display panel 1 based on an image data D_IN received from a host 3.

In one or more embodiments, the display panel 1 comprises gate lines 4, which may be also referred to as scan lines, source lines 5, display elements 6, and gate driver circuitry 7 configured to drive the gate lines 4. In one or more embodiments, each display element 6 is disposed at an intersection of a corresponding gate line 4 and source line 5. When an OLED display panel is used as the display panel 1, the display elements 6 may each comprise a light emitting element, a select transistor, and a hold capacitor in one or more embodiments. When a liquid crystal display panel is used as the display panel 1, the display elements 6 may each comprise a pixel electrode, a select transistor, and a hold capacitor, in one or more embodiments. Various interconnections other than the gate lines 4 and the source lines 5 may be disposed in the display panel 1, depending on the configuration of the display elements 6.

In one or more embodiments, the display driver 2 comprises source outputs S1 to S(2n) respectively connected to the source lines 5 of the display panel 1 and drives the source lines 5 based on the image data D_IN received from the host 3. In one or more embodiments, the display driver 2 comprises an interface 11, an image IP core 12, and source driver circuitry 13. In one or more embodiments, the interface 11 receives the image data D_IN from the host 3 and forwards the same to the image IP core 12. In one or more embodiments, the image IP core 12 performs desired image processing on the image data D_IN to generate a processed image data D_OUT. In one or more embodiments, the source driver circuitry 13 drives the source lines 5 of the display panel 1 to source output voltages corresponding to the processed image data D_OUT received from the image IP core 12. In one or more embodiments, the processed image data D_OUT comprises pixel data describing grayscale values of the respective display elements 6 of the display panel 1.

In one or more embodiments, in each horizontal sync period, source output voltages corresponding to the grayscale values described in the pixel data are written into display elements 6 connected to the gate line 4 selected in the horizontal sync period, via the source lines 5. In one or more embodiments, the brightness level of each display element 6 corresponds to the source output voltage written into the display element 6.

In one or more embodiments, as illustrated in FIG. 2, the source driver circuitry 13 comprises grayscale voltage generator circuitry 21, a plurality of grayscale lines 22₁ to 22_m, a plurality of output circuitries 23₁ to 23_2n, and a plurality of gamma assist circuitries 24. In FIG. 2, the symbols D₁ to D_2n denote pixel data of the processed image data D_OUT supplied to the source driver circuitry 13, the pixel data being associated with the source outputs S1 to S(2n), respectively.

In one or more embodiments, the grayscale voltage generator circuitry 21 is configured to generate grayscale voltages V₁ to V_m respectively corresponding to allowed grayscale values of the pixel data D₁ to D_2n and supply the generated grayscale voltages V₁ to V_m to the output circuitries 23₁ to 23_2n via the grayscale lines 22₁ to 22_m, respectively. In one or more embodiments, the voltage levels of the grayscale voltages V₁ to V_m are different from one another. In one or more embodiments, the grayscale voltage generator circuitry 21 is configured to maintain the grayscale voltages V₁ to V_m at desired voltage levels. In one or more embodiments, the grayscale voltage generator circuitry 21 is configured to, when the grayscale voltages V₁ to V_m undesirably change from the desired voltage levels, bring the grayscale voltages V₁ to V_m back to the desired voltage levels.

In one or more embodiments, the output circuitries 23₁ to 23_2n are configured to perform digital-analog conversion on the pixel data D₁ to D_2n to output source output voltages corresponding to the pixel data D₁ to D_2n to output terminals 25₁ to 25_2n, the digital-analog conversion being based on the grayscale voltages V₁ to V_m received via the grayscale lines 22₁ to 22_m. In one or more embodiments, the output terminals 25₁ to 25_2n are connected to the source outputs S1 to S(2n), and the source output voltages outputted from the output circuitries 23₁ to 23_2n are supplied to desired display elements 6 via the source outputs S1 to S(2n) and the source lines 5.

In one or more embodiments, each output circuitry 23_i comprises a decoder 26 and a source amplifier 27. In one or more embodiments, the decoder 26 of the output circuitry 23_i outputs to the source amplifier 27 at least one grayscale voltage selected from the grayscale voltages V₁ to V_m based on the pixel data D_i. In one or more embodiments, the source amplifier 27 of the output circuitry 23_i generates a source output voltage corresponding to the grayscale voltage selected by the decoder 26 on the output terminal 25_i. In one or more embodiments, the source amplifier 27 comprises a plurality of inputs and is configured to feed back the source output voltage to a first input and receive the grayscale voltage selected by the decoder 26 on a second input. In one or more embodiments, the source amplifier 27 is configured as a voltage follower.

In one or more embodiments, the grayscale voltages V₁ to V_m generated on the grayscale lines 22₁ to 22_m may vary upon changes in the source output voltages outputted from the output circuitries 23₁ to 23_2n. In one or more embodiments, when the source output voltages outputted from the source amplifiers 27 vary, the voltages on the second inputs of the source amplifiers 27, which receive the grayscale voltages from the decoders 26, may vary due to an influence of the input load capacitances. This may cause changes in the voltage levels of the grayscale voltages V₁ to V_m on the grayscale lines 22₁ to 22_m.

In one or more embodiments, the grayscale voltage generator circuitry 21 operates to bring the grayscale voltages V₁ to V_m back to the desired levels when the grayscale voltages V₁ to V_m on the grayscale lines 22₁ to 22_m undesirably change. This operation makes it possible to rapidly bring the grayscale voltage V₁ to V_m back to the desired voltage levels at least in the vicinity of the grayscale voltage generator circuitry 21.

In one or more embodiments, the gamma assist circuitries 24 are configured to drive the grayscale lines 22₁ to 22_m at positions apart from the grayscale voltage generator circuitry 21 to assist the bringing back of the grayscale voltages V₁ to V_m to the desired voltage levels. Such operation of the gamma assist circuitries 24 may be hereinafter referred to as “gamma assist operation.” Performing the gamma assist operation is effective for rapidly bringing the grayscale voltages V₁ to V_m back to the desired voltage levels over the entire of the grayscale lines 22₁ to 22_m. In one or more embodiments, the gamma assist operation reduces settling times of the source output voltages and thereby allows image display at a high refresh rate.

In one or more embodiments, as illustrated in FIG. 3, the plurality of gamma assist circuitries 24 are distributedly arranged along the direction in which the grayscale lines 22₁ to 22_m are extended. In one or more embodiments, first gamma assist circuitry 24₁ of the plurality of gamma assist circuitries 24 is disposed at first ends 29 of the grayscale lines 22₁ to 22_m, and second gamma assist circuitry 24₂ is disposed at second ends 30 of the grayscale lines 22₁ to 22_m. In one or more embodiments, the grayscale voltage generator circuitry 21 is disposed at midpoints of the grayscale lines 22₁ to 22_m. In one or more embodiments, half the remaining gamma assist circuitries 24 are disposed between the first gamma assist circuitry 24₁ and the grayscale voltage generator circuitry 21 at constant intervals and the remaining half are disposed between the second gamma assist circuitry 24₂ and the grayscale voltage generator circuitry 21 at constant intervals.

In one or more embodiments, as illustrated in FIG. 4, each gamma assist circuitry 24 comprises a plurality of gamma assist unit circuits 28 respectively connected to the grayscale lines 22₁ to 22_m. In FIG. 4, the gamma assist unit circuit 28 connected to the grayscale line 22_i is denoted by the numeral 28_i, and the gamma assist unit circuit 28 connected to the grayscale line 22_i+1 is denoted by the numeral 28_i+1.

In one or more embodiments, the gamma assist unit circuit 28_i comprises a holding node N_HLD to hold the grayscale voltage V_i received from the grayscale line 22_i and is configured to drive the grayscale line 22_i based on a voltage between the holding node N_HLD and the grayscale line 22_i.

In one or more embodiments, the gamma assist unit circuit 28_i comprises a gamma assist switch 31, capacitor elements 32, 33, and source follower circuitry 34.

In one or more embodiments, the gamma assist switch 31 is connected between the grayscale line 22_i and the holding node N_HLD. In one or more embodiments, the gamma assist switch 31 is configured to electrically connect and disconnect the grayscale line 22_i and the holding node N_HLD, based on the switch control signals SW_GMAST_P and SW_GMAST_N.

In one or more embodiments, the gamma assist switch 31 is configured as a transmission gate comprising a PMOS transistor MP1 and an NMOS transistor MN1. In one or more embodiments, the switch control signal SW_GMAST_N is supplied to the gate of the PMOS transistor MP1, and the switch control signal SW_GMAST_P is supplied to the gate of the NMOS transistor MN1. In one or more embodiments, the switch control signals SW_GMAST_P and SW_GMAST_N are complementary to each other. In one or more embodiments, the switch control signal SW_GMAST_P is a high active signal, which is pulled up to the high level when asserted. In such embodiments, the switch control signal SW_GMAST_N is a low active signal, which is pulled down to the low level when asserted. In one or more embodiments, the gamma assist switch 31 is turned on when the switch control signals SW_GMAST_P and SW_GMAST_N are asserted, and turned off when negated.

In one or more embodiments, the capacitor element 32 is connected between a power supply line 35 and the holding node N_HLD, and the capacitor element 33 is connected between a grounding line 36 and the holding node N_HLD. In one or more embodiments, the power supply line 35 and the ground line 36 are both potential-fixed lines of fixed potentials. In one or more embodiments, the power supply line 35 has an analog power supply level AVDD, and the grounding line 36 is circuit-grounded. In FIG. 4, the potential of the circuit ground is denoted by the symbol “AVSS.” In one or more embodiments, the capacitor elements 32 and 33 are used to stably hold the grayscale voltage V_i which has been written from the grayscale line 22_i via the gamma assist switch 31 on the holding node N_HLD when the gamma assist switch 31 is turned off. In one or more embodiments, a gate capacitance of a PMOS transistor MP2 is used as the capacitor element 32, and a gate capacitance of an NMOS transistor MN2 is used as the capacitor element 33. In one or more embodiments, the PMOS transistor MP2 has a source and drain connected to the power supply line 35 and a gate connected to the holding node N_HLD. In one or more embodiments, the NMOS transistor MN2 has a source and drain connected to the grounding line 36 and a gate connected to the holding node N_HLD.

In one or more embodiments, the source follower circuitry 34 of the gamma assist unit circuit 28_i comprises an output node N_OUT connected to the grayscale line 22_i and is configured to drive the grayscale line 22_i through a source follower operation, based on the voltage between the holding node N_HLD and the grayscale line 22_i. In one or more embodiments, the source follower circuitry 34 comprises NMOS transistors MN3, MN4, PMOS transistors MP3, MP4, and constant current sources 37 and 38.

In one or more embodiments, the NMOS transistor MN3 has a gate connected to the holding node N_HLD, a source connected to the output node N_OUT, and a drain supplied with a constant current from the constant current source 37. In one or more embodiments, this connection generates a potential corresponding to the voltage between the holding node N_HLD and the output node N_OUT on the drain of the NMOS transistor MN3. In one or more embodiments, the constant current source 37 comprises a PMOS transistor MP5 having a gate supplied with a bias voltage IBP_ASIST, a source connected to the power supply line 35, and a drain connected to the drain of the NMOS transistor MN3.

In one or more embodiments, the PMOS transistor MP4 has a gate connected to the drain of the NMOS transistor MN3, a source connected to the power supply line 35, and a drain connected to the output node N_OUT. In one or more embodiments, the PMOS transistor MP4 operates as a pull-up transistor configured to pull up the output node N_OUT based on the potential on the drain of the NMOS transistor MN3.

In one or more embodiments, the PMOS transistor MP3 has a gate connected to the holding node N_HLD, a source connected to the output node N_OUT, and a drain from which a constant current is drawn by the constant current source 38. In one or more embodiments, this connection generates a potential corresponding to the voltage between the holding node N_HLD and the output node N_OUT on the drain of the PMOS transistor MP3. In one or more embodiments, the constant current source 38 comprises an NMOS transistor MN5 having a gate supplied with a bias voltage IBN_ASIST, a source connected to the grounding line 36, and a drain connected to the drain of the PMOS transistor MP3.

In one or more embodiments, the NMOS transistor MN4 has a gate connected to the drain of the PMOS transistor MP3, a source connected to the grounding line 36, and a drain connected to the output node N_OUT. In one or more embodiments, the NMOS transistor MN4 operates as a pull-down transistor configured to pull down the output node N_OUT based on the potential on the drain of the PMOS transistor MP3.

In one or more embodiments, the source follower circuitry 34 of the gamma assist unit circuit 28_i is configured to reduce the voltage between the grayscale line 22_i and the holding node N_HLD by driving the grayscale line 22_i with the PMOS transistor MP4 or the NMOS transistor MN4 when the voltage between the grayscale line 22_i and the holding node N_HLD is larger than a predetermined voltage. This operation makes it possible to bring the grayscale voltage V_i back to the desired voltage level while suppressing excessive reaction to changes in the grayscale voltage V_i generated on the grayscale line 22_i.

In one or more embodiments, the source follower circuitry 34 of the gamma assist unit circuit 28_i is configured to raise the potential on the grayscale line 22_i by activating the PMOS transistor MP4 when the potential on the grayscale line 22_i is lower than the potential obtained by subtracting the threshold voltage of the NMOS transistor MN3 from the potential on the holding node N_HLD. In one or more embodiments, the source follower circuitry 34 of the gamma assist unit circuit 28_i is configured to lower the potential on the grayscale line 22_i by activating the NMOS transistor MN4 when the potential on the grayscale line 22_i is higher than the potential obtained by adding the threshold voltage of the PMOS transistor MP3 to the potential on the holding node N_HLD.

With reference to FIG. 5, in one or more embodiments, each gamma assist unit circuit 28_i is configured to perform the above-described “gamma assist operation” during a gamma assist operation period in each horizontal sync period, the gamma assist operation period being defined to include a time when the source output voltages start to change. In one or more embodiments, each gamma assist unit circuit 28_i drives the grayscale line 22_i based on the voltage between the holding node N_HLD and the output node N_OUT in the gamma assist operation. In one or more embodiments, each gamma assist unit circuit 28_i writes the grayscale voltage V_i generated on the grayscale line 22_i into the holding node N_HLD during a period other than the gamma assist operation period and drives the grayscale line 22_i based on the voltage between the holding node N_HLD and the output node N_OUT during the gamma assist operation period. This operation allows rapidly bringing the grayscale voltage V_i on the grayscale line 22_i back to the original voltage after the grayscale voltage V_i has changed due to changes in the source output voltages during the gamma assist operation period.

In one or more embodiments, a source amplifier control signal DISP_SOSRCE is asserted at time t_B when a period of time t_SNT0 has elapsed after each horizontal sync period starts at time t_A. The source amplifiers 27 start to output the source output voltages based on the pixel data D₁ to D_2n at time t_B. In this operation, the source output voltages start to change at time t_B. The switch control signals SW_GMAST_P and SW_GMAST_N are asserted to turn on the gamma assist switch 31 until the gamma assist operation period starts after each horizontal sync period has started. This allows writing the grayscale voltage V_i on the grayscale line 22_i into the holding node N_HLD of the gamma assist unit circuit 28₁. In the state in which the gamma assist switch 31 is turned on, the holding node N_HLD and the output node N_OUT have the same potential, and the gamma assist operation is not performed.

In one or more embodiments, the gamma assist operation period starts a time duration t₁ in advance before the time t_B, which is the time when the source output voltages start to change. In one or more embodiments, the gamma assist switch 31 is turned off when the gamma assist operation period has started. In one or more embodiments, the gamma assist operation is performed to drive the grayscale line 22_i based on the voltage between the holding node N_HLD and the output node N_OUT, upon the turn-off of the gamma assist switch 31. In one or more embodiments, even when the grayscale voltage V_i has changed due to changes in the source output voltages, the gamma assist operation brings the grayscale voltage V_i generated on the grayscale line 22_i back to the original voltage.

In one or more embodiments, the gamma assist operation period continues for a time duration t₂. In one or more embodiments, the time duration t₂ is set to be sufficiently long for completing the changes in the source output voltages in the gamma assist operation period. In one or more embodiments, the gamma assist switch 31 is turned on to stop the gamma assist operation when the gamma assist operation period has elapsed.

In one or more embodiments, the source amplifier control signal DISP_SOSRCE is negated at time t_C when a period of time t_SNT1 has elapsed after time t_B, and the source amplifiers 27 stop outputting the source output voltages based on the pixel data D₁ to D_2n at time t_C.

In one or more embodiments, as illustrated in FIG. 6, gamma assist circuitries 24A and 24B are disposed, where the gamma assist circuitries 24A offer the gamma assist operation for ones of grayscale lines 22₁ to 22_m belonging to a first group, and the gamma assist circuitries 24B offer the gamma assist operation for different ones of grayscale lines 22₁ to 22_m, the different ones belonging to a second group instead of the first group. In one or more embodiments, the gamma assist circuitries 24A are not connected to the grayscale lines 22 belonging to the second group; the gamma assist circuitries 24A do not offer the gamma assist operation for the grayscale lines 22 belonging to the second group. In one or more embodiments, the gamma assist circuitries 24B are not connected to the grayscale lines 22 belonging to the first group; the gamma assist circuitries 24B do not offer the gamma assist operation for the grayscale lines 22 belonging to the first group.

In one or more embodiments, the gamma assist circuitries 24A offer the gamma assist operation for the grayscale lines 22₁ to 22_p and the gamma assist circuitries 24B offer the gamma assist operation for the grayscale lines 22_p+1 to 22_m, where p is a given number larger than one and smaller than m. In one or more embodiments, p may be m/2 when m is divisible by two. In one or more embodiments, the gamma assist circuitries 24A and the gamma assist circuitries 24B are located at different positions along the direction in which the grayscale lines 22₁ to 22_m are extended. This arrangement is useful for a case when a single gamma assist circuitry cannot incorporate gamma assist unit circuits 28 connected to all the grayscale lines 22₁ to 22_m due to a restriction in the area of each gamma assist circuitry. In one or more embodiments, the gamma assist circuitries 24A each comprise gamma assist unit circuits 28₁ to 28_p connected to the grayscale lines 22₁ to 22_p, respectively, while not connected to the grayscale lines 22_p+1 to 22_m. In one or more embodiments, the gamma assist circuitries 24B each comprise gamma assist unit circuits 28_p+1 to 28_m connected to the grayscale lines 22_p+1 to 22_m, respectively, while not connected to the grayscale lines 22₁ to 22_p.

In one or more embodiments, as illustrated in FIG. 7, the gamma assist circuitries 24A and the gamma assist circuitries 24B are alternately arranged. In one or more embodiments, one of the gamma assist circuitries 24A and 24B is disposed at the first ends 29 of the grayscale lines 22₁ to 22_m, and another of the gamma assist circuitries 24A and 24B is disposed at the second ends 30 of the grayscale lines 22₁ to 22_m. Illustrated in FIG. 7 is the configuration in which one of the gamma assist circuitries 24B is disposed at the first ends 29 of the grayscale lines 22₁ to 22_m, and another of the gamma assist circuitries 24B is disposed at the second ends 30 of the grayscale lines 22₁ to 22_m. In one or more embodiments, half the remaining gamma assist circuitries 24A and 24B are disposed between the grayscale voltage generator circuitry 21 and the gamma assist circuitry 24A or 24B disposed at the first ends 29 at constant intervals, and the remaining half are disposed between the grayscale voltage generator circuitry 21 and the gamma assist circuitry 24A or 24B disposed at the second ends 30 at constant intervals.

In one or more embodiments, as illustrated in FIG. 8, multiplexers 8 selecting source lines 5 are disposed in a display panel 1A to achieve time division driving. In one or more embodiments, source lines 5 selected by the multiplexers 8 are connected to the source outputs S1 to S(2n), and source output voltages are written into desired display elements 6 via the selected source lines 5. In one or more embodiments, two source lines 5 are connected to each multiplexer 8, and each multiplexer 8 connects the source line 5 selected from the two source lines 5 connected thereto to the corresponding source output Si. In one or more embodiments, three or more source lines 5 may be connected to each multiplexer 8. In such embodiments, each multiplexer 8 connects the source line 5 selected from the three or more source lines 5 connected thereto to the corresponding source output Si.

When two source lines 5 are connected to each multiplexer 8, in one or more embodiments, the source output voltage is switched in synchronization with the selection of the two source lines 5 as illustrated in FIG. 9. In FIG. 9, the legend “#1” represents a source output voltage corresponding to the source line 5 first selected in each horizontal sync period, and the legend “#2” represents a source output voltage corresponding to the source line 5 subsequently selected in each horizontal sync period.

In one or more embodiments, the source amplifier control signal DISP_SOSRCE is asserted at time t_B when a period of time t_SNT0 has elapsed after each horizontal sync period starts at time t_A. In one or more embodiments, the source amplifiers 27 start to output the source output voltages #1 based on the pixel data D₁ to D_2n at time t_B. In one or more embodiments, at time t_D when a time duration t_SNT2 has elapsed thereafter, the source output voltage outputted from the source amplifiers 27 are switched from the source output voltages #1 to the source output voltages #2. In such embodiments, the source output voltages start to change at time to as well as time t_B. In one or more embodiments, the switching of the source output voltages is achieved by switching the pixel data D₁ to D_2n supplied to the decoders 26.

In one or more embodiments, the gamma assist operation is performed in a first gamma assist operation period defined to include time t_B and a second gamma assist operation period defined to include time t_D.

The switch control signals SW_GMAST_P and SW_GMAST_N are asserted to turn on the gamma assist switch 31, until the first gamma assist operation period starts after each horizontal sync period starts. This achieves writing the grayscale voltage V_i on the grayscale line 22_i into the holding node N_HLD of the gamma assist unit circuit 28_i.

In one or more embodiments, the first gamma assist operation period is starts a time duration t₁ in advance before the time t_B, which is the time when the source output voltages start to change. In one or more embodiments, the gamma assist switch 31 is turned off when the gamma assist operation period has started. In one or more embodiments, the gamma assist operation is performed to drive the grayscale line 22_i based on the voltage between the holding node N_HLD and the output node N_OUT when the gamma assist switch 31 is turned off.

In one or more embodiments, the first gamma assist operation period continues for a time duration t₂. In one or more embodiments, the time duration t₂ is set to be sufficiently long for completing the changes in the source output voltages in the first gamma assist operation period. In one or more embodiments, the gamma assist switch 31 is turned on to stop the gamma assist operation when the first gamma assist operation period has elapsed.

In one or more embodiments, the second gamma assist operation period starts a time duration t₃ in advance before the time to, which is the time when the source output voltages start to change. In one or more embodiments, the gamma assist switch 31 is turned off when the second gamma assist operation period has started. In one or more embodiments, the gamma assist operation is performed to drive the grayscale line 22_i based on the voltage between the holding node N_HLD and the output node N_OUT when the gamma assist switch 31 is turned off.

In one or more embodiments, the second gamma assist operation period continues for a time duration t₄. In one or more embodiments, the time duration t₄ is set to be sufficiently long for completing the changes in the source output voltages in the second gamma assist operation period. In one or more embodiments, the gamma assist switch 31 is turned on to stop the gamma assist operation when the second gamma assist operation period has elapsed.

In one or more embodiments, the source amplifier control signal DISP_SOSRCE is then negated at time t_C when a period of time t_SNT3 has elapsed after time t_D, and the source amplifiers 27 stop outputting the source output voltages based on the pixel data D₁ to D_2n at time t_C

In one or more embodiments, the source output voltages are similarly switched in synchronization with selection of the source lines 5 after the source output voltages start to be outputted when three or more source lines 5 are connected to each multiplexer 8. In one or more embodiments, gamma assist operation periods are defined to each include the time when the source output voltages start to be outputted and the times when the source output voltages are switched, and the gamma assist operation is performed during the gamma assist operation periods.

Although various embodiments of this disclosure have been specifically described, the technologies described in this disclosure may be implemented with various modifications.

Claims

1. A display driver, comprising: a first grayscale line;output circuitry configured to receive a first grayscale voltage from the first grayscale line and perform digital-analog conversion on a pixel data to output a source output voltage corresponding to the pixel data, the digital-analog conversion being based on the first grayscale voltage; andfirst gamma assist circuitry comprising a first holding node to hold the first grayscale voltage received from the first grayscale line and configured to drive the first grayscale line based on a first voltage between the first holding node and the first grayscale line.

2. The display driver according to claim 1, wherein the first gamma assist circuitry further comprises: a first MOS transistor having a source connected to the first grayscale line and configured to generate, based on a first potential on the first holding node, a second potential on a drain thereof through a source follower operation; anda second MOS transistor connected between the first grayscale line and a potential-fixed line of a fixed potential and configured to drive the first grayscale line based on the potential of the drain of the first MOS transistor.

3. The display driver according to claim 2, wherein the first gamma assist circuitry further comprises a first capacitor element connected between the first holding node and the potential-fixed line.

4. The display driver according to claim 1, wherein the first gamma assist circuitry further comprises: a first NMOS transistor having a source connected to the first grayscale line and configured to generate, based on a first potential on the first holding node, a second potential on a drain thereof through a source follower operation; anda first PMOS transistor connected between the first grayscale line and a power supply line and configured to drive the first grayscale line based on the potential of the drain of the first NMOS transistor.

5. The display driver according to claim 4, wherein the first gamma assist circuitry further comprises: a second PMOS transistor having a source connected to the first grayscale line and configured to generate, based on the first potential on the first holding node, a third potential on a drain thereof through a source follower operation; anda second NMOS transistor connected between the first grayscale line and a grounding line and configured to drive the first grayscale line based on the potential of the drain of the second PMOS transistor.

6. The display driver according to claim 5, wherein the first gamma assist circuitry further comprises: a first constant current source configured to supply a first constant current to the drain of the first NMOS transistor; anda second constant current source configured to draw a second constant current from the drain of the second PMOS transistor.

7. The display driver according to claim 4, wherein the first gamma assist circuitry further comprises a first capacitor element connected between the first holding node and the power supply line.

8. The display driver according to claim 5, wherein the first gamma assist circuitry further comprises a second capacitor element connected between the first holding node and the grounding line.

9. The display driver according to claim 1, wherein the first gamma assist circuitry further comprises a switch connected between the first grayscale line and the first holding node.

10. The display driver according to claim 9, wherein the switch is configured to be turned on during a first period of a horizontal sync period and turned off during a second period following the first period in the horizontal sync period, the second period including a time when the output circuitry starts outputting the source output voltage.

11. The display driver according to claim 10, wherein the switch is configured to be turned on during a third period following the second period in the horizontal sync period.

12. The display driver according to claim 1, further comprising: a second grayscale line extended in a first direction in which the first grayscale line is extended; andsecond gamma assist circuitry comprising a second holding node to hold a second grayscale voltage received from the second grayscale line and configured to drive the second grayscale line based on a voltage between the second holding node and the second grayscale line, the second gamma assist circuitry being not connected to the first grayscale line,wherein the first gamma assist circuitry and the second gamma assist circuitry are disposed at different positions in the first direction.

13. The display driver according to claim 12, wherein the output circuitry is configured to receive the second grayscale voltage from the second grayscale line and perform the digital-analog conversion based on the first grayscale voltage and the second grayscale voltage.

14. A display device, comprising: a display panel; anda display driver,wherein the display driver comprises: a grayscale line;output circuitry configured to receive a grayscale voltage from the grayscale line and perform digital-analog conversion on a pixel data to output a source output voltage corresponding to the pixel data, the digital-analog conversion being based on the grayscale voltage; andgamma assist circuitry comprising a holding node to hold the grayscale voltage received from the grayscale line and configured to drive the grayscale line based on a voltage between the holding node and the grayscale line.

15. The display device according to claim 14, wherein the gamma assist circuitry further comprises: a first MOS transistor having a source connected to the grayscale line and configured to generate, based on a first potential on the holding node, a second potential on a drain thereof through a source follower operation; anda second MOS transistor connected between the grayscale line and a potential-fixed line of a fixed potential and configured to drive the grayscale line based on the potential of the drain of the first MOS transistor.

16. The display device according to claim 15, wherein the gamma assist circuitry further comprises a first capacitor element connected between the holding node and the potential-fixed line.

17. The display device according to claim 14, wherein the gamma assist circuitry further comprises a switch connected between the grayscale line and the holding node.

18. A method, comprising: receiving a grayscale voltage from a grayscale line;performing digital-analog conversion on a pixel data to output an source output voltage corresponding to the pixel data, the digital-analog conversion being based on the grayscale voltage;holding the grayscale voltage received from the grayscale line on a holding node; anddriving the grayscale line based on a voltage between the holding node and the grayscale line.

19. The method according to claim 18, wherein holding the grayscale voltage on the holding node comprises: electrically connecting the grayscale line and the holding node during a first period of a horizontal sync period; andelectrically disconnecting the grayscale line and the holding node during a second period following the first period in the horizontal sync period, the second period including a time when the source output voltage starts to be outputted.

20. The method according to claim 19, wherein holding the grayscale voltage on the holding node further comprises: electrically connecting the grayscale line and the holding node during a third period following the second period in the horizontal sync period.