Patent Application
20080309681
1. Field of the Invention
The present invention relates to liquid crystal displays (LCDs), and more particularly, to devices and methods for driving LCD panels.
2. Description of the Prior Art
Please refer to
As shown in
In addition, the source driving circuit 120 comprises a decoder 124 and a buffer 128, where according to display data, the decoder 124 performs selection operations on the gray level voltages V(0), V(1), . . . , and V(M) and outputs a gray level voltage selected from the gray level voltages V(0), V(1), . . . , and V(M), and then a buffering operation is performed by utilizing the buffer 128 to drive the corresponding load within the LCD panel, i.e., the above-mentioned equivalent capacitance Cload.
As mentioned above, during the process of generating the gray level voltages, the voltage swing between the candidate gray level voltages VP(M−i) and VN(i) switched by the corresponding switching unit 116-i (i=0, 1, . . . , M) during polarity inversion is so large that installing large-sized transmission gates within the decoder 124 is necessary, where each transmission gate typically has a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor according to the conventional implementation method. However, at the same time point, there may be only one of the PMOS transistor and the NMOS transistor dominates the operation of the transmission gates and acts as a primary transistor, while the other one acts as a secondary transistor. In other words, at the same time point, about a half of the circuit layout area of the decoder 124 is not utilized effectively.
It is therefore an objective of the claimed invention to provide devices and methods for driving liquid crystal display (LCD) panels to solve the above-mentioned problem.
It is another objective of the claimed invention to provide devices and methods for driving LCD panels to reduce the voltage swings during the process of generating gray level voltages, so that the gray level voltages generated by utilizing the claimed invention is more stable than those generated by utilizing the prior art, and the switching speed can be further increased.
It is another objective of the claimed invention to provide devices and methods for driving LCD panels to prevent from using transmission gates during decoding display data, so that the number of transistors utilized during decoding the display data can be reduced to a half of the number of transistors required by the prior art, in order to save the circuit layout area.
According to a preferred embodiment of the claimed invention, a device for driving an LCD panel is disclosed. The device comprises: a gray level voltage generation circuit, for generating a plurality of gray level voltages respectively corresponding to a plurality of gray levels, and determining whether the gray level voltages are generated by utilizing a first set of reference voltages or a second set of reference voltages according to a polarity inversion control signal, where according to the polarity inversion control signal, the gray level voltage generation circuit determines whether a gray level voltage is generated by utilizing a maximum of the first set of reference voltages or a maximum of the second set of reference voltages, and further determines whether another gray level voltage is generated by utilizing a minimum of the first set of reference voltages or a minimum of the second set of reference voltages; and a source driving circuit, coupled to the gray level voltage generation circuit, for selecting a gray level voltage from the plurality of gray level voltages according to display data or inverted data of the display data to drive a source of a display cell of the LCD panel, where the source driving circuit determines whether the gray level voltage is selected by utilizing the display data or the inverted data according to the polarity inversion control signal.
While the device mentioned above is provided, a method for driving an LCD panel is further disclosed according to one embodiment of the claimed invention. The method comprises: generating a plurality of gray level voltages respectively corresponding to a plurality of gray levels, and determining whether the gray level voltages are generated by utilizing a first set of reference voltages or a second set of reference voltages according to a polarity inversion control signal. The step of determining whether the gray level voltages are generated by utilizing the first set of reference voltages or the second set of reference voltages further comprises: according to the polarity inversion control signal, determining whether a gray level voltage is generated by utilizing a maximum of the first set of reference voltages or a maximum of the second set of reference voltages; and according to the polarity inversion control signal, determining whether another gray level voltage is generated by utilizing a minimum of the first set of reference voltages or a minimum of the second set of reference voltages. The method further comprises: selecting a gray level voltage from the plurality of gray level voltages according to display data or inverted data of the display data to drive a source of a display cell of the LCD panel, and determining whether the gray level voltage is selected by utilizing the display data or the inverted data according to the polarity inversion control signal.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
According to this embodiment, the first set of buffer amplifiers 112-1 buffer the first set of reference voltages VREF_P(1), VREF_P(2), . . . , VREF_P(N−1), and VREF_P(N) to generate the first set buffered reference voltages at the output terminals of the first set of buffer amplifiers 112-1, while the second set of buffer amplifiers 112-2 buffer the second set of reference voltages VREF_N(1), VREF_N(2), . . . , VREF_N(N−1), and VREF_N(N) to generate the second set buffered reference voltages at the output terminals of the second set of buffer amplifiers 112-2, where the buffered reference voltage processed by a certain buffer amplifier is substantially equivalent to the reference voltage received by the same buffer amplifier. In addition, the first set of gray level resistors 114-1 are arranged in series and coupled to the first set of buffer amplifiers 112-1, in order to generate the first set of candidate gray level voltages VP(0), VP(1), . . . , VP(M−1), and VP(M) according to the first set of buffered reference voltages. Similarly, the second set of gray level resistors 114-2 are arranged in series and coupled to the second set of buffer amplifiers 112-2, in order to generate the second set of candidate gray level voltages VN(0), VN(1), . . . , VN(M−1), and VN(M) according to the second set of buffered reference voltages. As mentioned above, each set of gray level resistors out of the two sets of gray level resistors 114-1 and 114-2 comprise M voltage-dividing resistors arranged in series, where the terminals of these resistors are capable of being utilized for outputting voltages. According to this embodiment, since (M+1)>N, some of the nodes between the voltage-dividing resistors are not directly connected to a buffer amplifier.
Within this embodiment, the curve of the function fVP that may have the values of the first set of candidate gray level voltages VP(0), VP(1), . . . , VP(M−1), and VP(M) outputted by the first set of gray level resistors 114-1 with respect to the display data is illustrated as shown in
According to this embodiment, each switching unit 216-i (i=0, 1, . . . , M) is coupled to the candidate gray voltages VP(i) and VN(i) to select a candidate gray level voltage from the candidate gray level voltages VP(i) and VN(i) as a corresponding gray level voltage V(i) according to the polarity inversion control signal POL and its inverted signal POLB. As a result, the device 200 and the corresponding method provided by this embodiment of the present invention can determine whether the plurality of gray level voltages V(0), V(1), . . . , and V(M) shown in
Please note that, according to the curve of the function fVP as illustrated in
According to this embodiment, one set of candidate gray level voltages out of the two sets of candidate gray level voltages are selected as the gray level voltages V(0), V(1), . . . , and V(M) according to the polarity represented by the polarity inversion control signal POL, in order to be transmitted to the source driving circuits of respective display units of the LCD panel, such as the source driving circuit 220, where Cload represents the equivalent capacitance of the display cell driven by the source driving circuit 220.
The source driving circuit 220 of this embodiment comprises a display data control circuit 222, a decoder 224, and the above-mentioned buffer 128, where according to the display data, the decoder 124 selects a gray level voltage out of the gray level voltages V(0), V(1), . . . , and V(M) and outputs the selected gray level voltage (i.e., the gray level voltage DECODER_OUT shown in
According to this embodiment, if the polarity inversion control signal POL is at a high voltage level (meaning logic 1 here) while the inverted signal POLB is at a low voltage level, the output data D outputted by the display data control circuit 222 is the inverted display data. Conversely, if the polarity inversion control signal POL is at a low voltage level (meaning logic 0 here) while the inverted signal POLB is at a high voltage level, the output data D outputted by the display data control circuit 222 is still the display data. As a result, the display data control circuit 222 outputs the display data or the inverted data as the output data D in accordance with the polarity inversion control signal POL and its inverted signal POLB, so according to the output data D (which is the bypassed display data or the inverted data here), the decoder 224 can select from a plurality of gray level voltages the gray level voltage (e.g. the gray level voltage DECODER_OUT shown in
For example, if M=63, the number of transmission gates required for implementing the decoder 124 shown in
(32+16+8+4+2+1)*2=63*2=126;
where each transmission gate has a PMOS transistor and an NMOS transistor. In contrast to the decoder 124 shown in
According to a variation of this embodiment, each switching unit 216-i (i=0, 1, . . . , M) is coupled to candidate gray level voltages VP(M−i) and VN(M−i) to select a candidate gray level voltage as a corresponding gray level voltage V(i) from the candidate gray level voltages VP(M−i) and VN(M−i) according to the polarity inversion control signal POL and its inverted signal POLB. According to this variation, if the polarity inversion control signal POL is at a high voltage level while the inverted signal POLB is at a low voltage level, the output data D outputted by the display data control circuit 222 is still the display data. Conversely, if the polarity inversion control signal POL is at a low voltage level while the inverted signal POLB is at a high voltage level, the output data D outputted by the display data control circuit 222 is the inverted display data. Similar descriptions for this variation are not repeated in detail.
According to another variation of this embodiment, at least a portion of the source driving circuit 220 can be integrated into a single module regarding layout. For example, two or all elements of the display data control circuit 222, the decoder 224, and the buffer 128 can be integrated into a single module.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
