The present invention relates to methods and systems for forming a contact to a top electrode in, for example, ferroelectric capacitor devices.
A conventional ferroelectric capacitor includes a ferroelectric layer sandwiched between a bottom electrode and a top electrode. The ferroelectric layer may comprise, for example, PZT, SBT or BLT. The bottom electrode is mounted on a substrate, the electrical connection to the bottom electrode being via a metal plug through the substrate. The capacitor is covered with an interlayer dielectric hardmask, normally Tetraethyl Orthosilicate (TEOS), and connection to the top electrode is achieved by etching a window through the interlayer dielectric hardmask and filling the window with a metal filler.
A number of difficulties arise with this method of connection. Firstly, there is a danger of damage to the capacitor in the reactive ion etching process (RIE) used to create the contact window. Secondly, there is a danger of misalignment between the window and the capacitor, if the etching mask is misaligned which, given the small size of the capacitor, can easily happen. This misalignment could cause damage to the capacitor itself or could short circuit the capacitor.
One conventional way to reduce damage to the capacitor during the RIE process is to increase the thickness of the top electrode to reduce the likelihood of etching through the top electrode into the capacitor. However, this does not overcome misalignment problems.
In view of the foregoing problems with conventional processes and devices, a need exists for a method for reducing damage to the capacitor during the RIE process and for reducing alignment problems.
In general terms, the present invention proposes that a CMP (chemical mechanical polishing) process is applied to the interlayer dielectric of a capacitor to expose the top electrode and then a metal contact to the top electrode is applied. This is considered particularly advantageous because access to the top electrode is obtained without etching the interlayer dielectric, and there is therefore minimal risk of damage being caused to the top electrode.
Also, as there is no requirement for the formation of a window to form the contact to the top electrode, the process embodying the present invention is essentially self-aligning and, unlike conventional processes, there is no danger of over-etching due to misaligned masks which could result in either damage to the ferroelectric layer or short circuiting of the capacitor.
According to a first aspect of the present invention there is provided a method for fabricating a device comprising the steps of:
Preferably, said exposed surface of said second electrode has a first surface area, and said metal layer has a surface having a second surface area, said surface of said metal layer contacting said exposed second electrode, and wherein the step of etching said metal layer comprises etching said metal layer such that said second surface area is greater than said first surface area. This is particularly advantageous, as when the metal layer extends over the full exposed contact area of the top (second) electrode thereby giving a complete covering of the top electrode, contact to the top electrode will be more robust and improved relative to that obtained at the bottom of a window in a conventional process.
When etching the metal layer, there may be some resist and arc ashing, however, this will be much less than during conventional processes of establishing contact to the top electrode, resulting in negligible damage to the electrode.
According to a second aspect of the present invention there is provided a device comprising;
Preferred features of the invention will now be described, for the sake of illustration only, with reference to the following Figures in which:
a is a schematic cross-sectional view of a prior art capacitor of the type shown in
b is a schematic cross-sectional view of the prior art capacitor shown in
a is a schematic cross-sectional view of a capacitor according to an embodiment of the present invention with an encapsulation layer applied; and
b is a schematic cross-sectional view of the capacitor shown in
Ferroelectric capacitors 1, such as that shown in
a and 2b show the various processing stages of a device such as a ferroelectric capacitor 1 of the type shown in
As shown in
As shown in
a and 3b show the process of forming connection to the top electrode 7 according to an embodiment of the present invention. The capacitor 1 is covered with an interlayer dielectric 12. As in the capacitor of
Connection to the top electrode 7 is achieved by depositing a metal layer 14 onto the exposed surface of the top electrode to establish an electrical connection. This is shown in
The exposed surface area of the top electrode 7 which contacts the metal layer 14 could have a smaller surface area than that of the surface of the metal layer 14 with which it is in contact. Thus, the metal layer could extend beyond the contact face of the top electrode which makes mask alignment when etching the interconnection pattern easier.
The systems and methods according to the present invention may be particularly useful in the production of devices for use, for example, as ferroelectric random access memories.
Various modifications to the embodiments of the present invention described above may be made. For example, other materials and method steps can be added or substituted for those above. Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to the skilled reader, without departing from the spirit and scope of the invention.