Patent Application
20190089345
The present invention relates to a device and a method for generating a differential voltage.
To generate a differential voltage, a first terminal is connected to a supply voltage via a first switch and a first current limiting and a second terminal is connected to ground via a second switch and a second current limiting. Since the switches do not switch at exactly the same time and the currents swell to a differently strong extent at the terminals depending on the temperature and aging, common-mode interferences develop which interfere with the differential signal transfer in the further course due to asymmetric conductor guidance.
Common-mode interferences due to asymmetric signal generation should be avoided, so that the signals are less interfered with.
The present invention provides the advantage that common-mode interferences due to asymmetric signal generation are prevented. Thus, the signals are less interfered with.
It is provided to generate a corresponding differential signal with the aid of a current from an electrically isolated energy source.
In the embodiment according to the present invention, a capacitor C1 may be charged when switches S3 and S4 are closed, switches S1 and S2 being open at the same time. After charging the capacitor, switches S3 and S4 are opened. To generate a differential voltage, switches S1 and S2 are closed. Due to the electrical isolation, it is possible to open and close switches S1 and S2 with a time delay, without an undesirable common-mode signal resulting therefrom. The currents via switches S1 and S2 and thus at corresponding terminals L and H always have exactly the same absolute value.
Preferably, those capacitors should be used which may be implemented in silicon. To generate longer signals, a second parallel circuit according to the present invention is thus provided, it being possible to permanently achieve a desired level.
It is also possible to generate a negative level, as is implemented in a third specific embodiment.
Additional advantages and advantageous embodiments may be derived from the description of the figures and the drawings.
First capacitor C1 is provided to facilitate a current flow I1 from terminal L to terminal H in the charged state. A current cannot flow from L to H until both switches S1 and S2 are closed. The currents via S1 and S2 and thus at terminals L and H have exactly the same absolute value, regardless of temperatures, aging, or the like. If, for example, a differential voltage of 2 volts is to be achieved and the cable impedance is 60 ohm, then the current is limited to 33 mA with the aid of current limiting Ilim. It is also conceivable, however, that larger or smaller currents flow, so that the desired differential voltage may be achieved faster or have a higher degree of accuracy.
In this process, first capacitor C1 is discharged.
In order to charge first capacitor C1, two further switches S3 and S4 are provided. When switches S3 and S4 are closed, a potential VCC is connected to GND via first capacitor C1 and first capacitor C1 is charged.
If first capacitor C1 is exhausted, although the differential voltage is to be continuously maintained, second capacitor C2 is provided to facilitate the flow of current I2 from L to H. Current I2 flows from L to H, when both switches S5 and S6 are closed. During this time, first capacitor C1 may be recharged, so that its energy is available as soon as second capacitor C2 requires charging.
In order to charge second capacitor C2, two further switches S7 and S8 are provided. When switches S7 and S8 are closed, a potential VCC is connected to GND via second capacitor C2 and second capacitor C2 is charged.
As a result of the mutual support of capacitors C1 and C2, it is possible to permanently achieve a desired voltage level, while the capacitors may have smaller dimensions, since they must be able to store only a fraction of the energy necessary to transfer one or multiple bits.
If the supply is switched from first capacitor C1 to second capacitor C2, switches S5 and S6 are closed in addition to already closed switches S1 and S2 and then switches S1 and S2 are opened. Two diodes D1 and D2 are tasked with allowing switches S1, S2, S5, and S6 to be closed simultaneously, without a high compensating current being able to flow from one of capacitors C1, C2 to the respective other capacitor. As soon as switches S1 and S2 are open, first capacitor C1 may be charged when switches S3 and S4 are closed.
If negative differential voltage changes or negative differential voltages are supposed to be generated, switches S11 through S18 are actuated in the same manner as switches S1 through S8.
At beginning 100, a first capacitor C1 is charged. In a step 110, a switch S1 and a switch S2 are closed. Thereupon, a current I1 flows from a terminal L to a terminal H. As a result, first capacitor C1 is discharged. In [step] 120, switches S3 and S4 are closed. As a result, a potential VCC is connected to GND via first capacitor C1 and first capacitor C1 is charged.
At beginning 100, a first capacitor C1 is charged. In step 110, switch S1 and switch S2 are closed. Thereupon, a current I1 flows from a terminal L to a terminal H. As a result, first capacitor C1 is discharged.
In [step] 120, switches S5 and S6 are closed. The two diodes D1 and D2 are tasked with allowing switches S1, S2, S5, and S6 to be closed simultaneously, without a high compensating current being able to flow from one of capacitors C1, C2 to the respective other capacitor. In [step] 130, switches S1 and S2 are opened. As soon as switches S1 and S2 are open, switches S3 and S4 are closed, so that first capacitor C1 may be charged.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102017216667.3 | Sep 2017 | DE | national |
