Patent Application
20180067898
This application claims the benefit of Taiwan application Serial No. 105128733, filed Sep. 6, 2016, the subject matter of which is incorporated herein by reference.
The invention relates in general to a device and method for a communication system, and more particularly to a device and method for handling symbol rate estimation and interference.
To evaluate system performance or to set the configuration of a receiver, a receiver frequently needs to accurately estimate a symbol rate. However, when a signal is transmitted through a channel, it is affected by channel effects, e.g., co-channel interference (CCI), in a way that the receiver may not be able to accurately estimate the symbol rate. Thus, system performance may be incorrectly evaluated or the configuration of the receiver may be incorrectly set.
Further, in order mitigate the influence of interference, the receiver needs to learn the frequency of interference to prevent or eliminate the interference. However, due to negative effects (e.g., noises), it is challenging for the receiver to accurately estimate the frequency of the interference.
Therefore, there is a need for a solution that accurately estimates the symbol rate and the frequency of interference in the presence of channel effects.
The invention is directed to a device and method for handling symbol rate estimation. The device and method of the present invention are capable of obtaining an accurate symbol rate while power consumption and locking time are reduced, hence solving the above issues.
The present invention discloses a communication device. The communication device includes: a receiving circuit, receiving a first plurality of time-domain signals; a transforming circuit, coupled to the receiving circuit, transforming the first plurality of time-domain signals to a first plurality of frequency-domain signals according to a time-frequency transform operation; a magnitude circuit, coupled to the transforming circuit, performing an absolute value operation on the first plurality of frequency-domain signals to generate a first plurality of output signals; and a selecting circuit, coupled to the magnitude circuit, selecting a maximum signal that satisfies a check condition from the first plurality of output signals.
The present invention further discloses a method. The method includes: receiving a first plurality of time-domain signals by a receiving circuit; transforming the first plurality of time-domain signals to a first plurality of frequency-domain signals according to a time-frequency transform operation by a transforming circuit; performing an absolute value operation o the first plurality of frequency-domain signals to generate a first plurality of output signals by a magnitude circuit; and selecting a maximum signal that satisfies a check condition from the first plurality of output signals by a selecting circuit.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
The receiving circuit 200 may further receive a plurality of time-domain signals sig_t2. Similarly, the transforming circuit 202 transforms the time-domain signals sig_t2 to a plurality of frequency-domain signals sig_f2 according to the time-frequency transform operation. The magnitude circuit 204 performs the absolute value operation (i.e., that obtains respective absolute values of the frequency-domain signals sig_f2) on the frequency-domain signals sig_f2 to generate a plurality of output signals sig_f_out2. The selecting circuit 206 may correspondingly add the output signals sig_f_out1 and the output signals sig_f_out2 to generate a plurality of auxiliary signals sig_f_aux. The above operation may be repeated for a predetermined number of times, i.e., superimposing the output signals to the predetermined number of times.
The selecting circuit 206 selects a maximum signal sig_f_max that satisfies a check condition from the auxiliary signals sig_f_aux (or from the output signals sig_f_out1 if superimposing is not performed). The maximum signal sig_f_max has a maximum amplitude that satisfies the check condition. Based on the above description, during the process of searching for the maximum signal, the selecting circuit 206 considers not only the magnitude of the amplitude but also whether the signal satisfies the check condition. Thus, through the check condition, negative effects (e.g., noises and/or interference) may be reduced to increase the reliability of the selected signal.
It should be noted that, there are numerous ways for the selecting circuit 206 to select the maximum signal. For example, the selecting circuit 206 selects the maximum signal that satisfies the check condition sequentially from the output signals sig_f_out1 (or from the auxiliary signals sig_f_aux if superimposed is performed) by means of a window according to a sliding window method. Further, there are also numerous ways for implementing the check condition used for determining the reliability of a signal.
In one embodiment, when the selecting circuit 206 is used to estimate the bandwidth, one of the plurality of sets of output signals may satisfy the check condition according to an equation:
f({Zk}k=1,k≠sub_maxM)+Zsub_max>G*Zsub_max (1)
In equation (1), {Zk}k=1M is the set of output signals, M is a size of the window, f(•) is a function, sub_max is an index of a maximum signal of the set of output signals, and G is a positive real number. Preferably, G is a gain margin. That is to say, the check condition is determined as satisfied when G*Zsub_max is not excessively large. G is a designed value or a predetermined value, and may be determined based on system considerations or design requirements. For example, when higher reliability is required, G may be set to a larger positive real number, i.e., the maximum signal G*Zsub_max less likely satisfies equation (1). Conversely, when lower reliability is required, G may be set to a smaller positive real number, i.e., the maximum signal G*Zsub_max more easily satisfies equation (1).
In another embodiment, when the selecting circuit 206 is used for estimating interference, one of the plurality of sets of output signals may satisfy the check condition according to an equation:
f({Zk}k=1,k≠sub_maxM)+Zsub_max <G*Zsub_max (2)
In equation (2), {Zk}k=1M is the set of output signals, M is a size of the window, f(•) is a function, sub_max is an index of a maximum signal of the set of output signals, and G is a positive real number. Preferably, G is a gain margin. That is to say, the check condition is determined as satisfied when G*Zsub_max is sufficiently large. G is a designed value or a predetermined value, and may be determined based on system considerations or design requirements. For example, when higher reliability is required, G may be set to a smaller positive real number, i.e., the maximum signal G*Zsub_max less likely satisfies equation (2). Conversely, when lower reliability is required, G may be set to a larger positive real number, i.e., the maximum signal G*Zsub_max more easily satisfies equation (2).
It should be noted that, in the above embodiment, the functions of equation (1) and equation (2) may be an equation:
f({Zk}k=1,k ≠sub_maxM)=Σk=1,k≠sub_maxMZk (3)
That is, equation (1) and equation (2) mean that G*Zsub_max needs to be greater than the sum of all {Zk}k=1M in order to be determined that the check condition is satisfied. Further, equation (1) to equation (3) illustrate a method in which the maximum signal is selected from one set of output signals, and the selecting circuit 206 repeatedly performs equation (1) to equation (3) on all of the sets of output signals of the plurality of outputs signals sig_f_out1 (or the plurality of auxiliary signals sig_f_aux obtained after superimposing) to select the maximum signal sig_f_max.
For example, the size of the window that the selecting circuit 206 uses is 4 (i.e., M=4 in equation (1)), and a maximum signal is first selected from the auxiliary signals A1, . . . , A4, e.g., the auxiliary signal A2. Next, the selecting circuit 206 checks whether A2 satisfies Σk=1,k≠24Ak+A2>G*A2. As previously described, G is a positive real number and may be determined based on system considerations and design requirements. When the auxiliary signal A2 satisfies the check condition, the selecting circuit 206 regards the auxiliary signal A2 as the maximum signal for estimating a valid bandwidth, and stores the auxiliary signal A2 to the estimating module 20. According to the sliding window method, the selecting circuit 206 continues selecting a maximum signal from the auxiliary signals A2, . . . , A5, e.g., the auxiliary signal A4, and compares the size of the selected auxiliary signal with that of the previously stored auxiliary signal A2. Next, the selecting circuit 206 checks whether the auxiliary signal A4 satisfies the condition A4>A2. When this condition is satisfied, the temporarily stored maximum signal is updated as the auxiliary signal A4. It is continued to check Σk=2,k≠45Ak+A4>G*A4. If the auxiliary signal A4 satisfies the check condition, the bandwidth estimated according to this maximum value is determined as being valid. If auxiliary signal A4 does not satisfy the check condition, the bandwidth estimated according to this maximum value is determined as being invalid. Furthermore, if A4>A2 is not satisfied, the auxiliary signal A2 remains as the maximum signal and a state of regarding the bandwidth estimated according to the auxiliary signal A2 as being valid or invalid is maintained. The selecting circuit 206 continues performing the above operation until the auxiliary signals AN−3, . . . , AN have all been processed.
After the above operation is performed, it is determined that the bandwidth estimated according to the maximum signal, e.g., the auxiliary signal Amax, is valid if the maximum signal satisfies the check condition. Thus, the bandwidth estimating circuit 300 may estimate the bandwidth bw_est according to the output signal Amax, and the calculating circuit 302 may calculate the symbol rate sbr_est according to the bandwidth bw_est.
Operation details of the communication device 30 are similar to those of the communication device 20, with one main difference being that, the bandwidth estimating circuit 300 and the calculating circuit 302 are replaced by the interference estimating circuit 400. For example, operations associated with equation (1) and equation (3) are replaced by operations associated with equation (2) and equation (3)—such repeated description is omitted herein.
The operation of the estimating module 20 may be concluded into a process 60 according to an embodiment of the present invention based on the foregoing embodiments. The process 60 is applied in the communication device 30 or the communication device 40, and includes following steps, as shown in
In step 600, the process 60 begins.
In step 602, a plurality of time-domain signals are received.
In step 604, the time-domain signals are transformed to a plurality of frequency-domain signals according to a time-frequency transform operation.
In step 606, an absolute value operation is performed on the frequency-domain signals to generate a plurality of output signals.
In step 608, if a plurality of previous output signals that are previously received are present, the output signals and the previous output signals are superimposed to generate a plurality of auxiliary signals. Step 610 is performed if the number of times of superimposing is equal to a predetermined number of times, otherwise step 602 is iterated.
In step 610, a maximum signal that satisfies a check condition is selected from the auxiliary signals.
In step 612, the process 60 ends.
The process 60 is an example for illustrating the operation of the estimating module 20, and associated details may be referred from the foregoing description and shall be omitted herein.
It should be noted that, there are numerous ways to realize the estimating module 20 (and the receiving circuit 200, the transforming circuit 202, the magnitude circuit 204 and the selecting circuit 206 included), the communication device 30 (and the estimating module 20, the bandwidth estimating circuit 300 and the calculating circuit 302 included) and the communication device 40 (and the estimating module 20 and the interference estimating circuit 40 included). For example, based on design considerations or system requirements, the above circuits are integrated into one or multiple circuits, and are usually implemented by a digital circuit/digital circuits. In one embodiment, the receiving circuit 200 may include an analog-to-digital converter (ADC). Further, the estimating module 20, the communication device 30 and the communication device 40 may be realized by hardware, software, firmware (a combination of a hardware device, computer instructions and data, with the computer instructions and data being read-only software in the hardware device), an electronic system, and/or a combination of the above devices.
In one embodiment, the sliding window circuit may include a comparator 722, a comparator 724 and an AND gate 726. More specifically, the comparator 722 may compare a set of auxiliary signals (e.g., A1, . . . , A4 in the foregoing embodiment) to obtain the maximum signal (A2) in that set of auxiliary signals. The comparator 724 checks whether the maximum signal satisfies the check condition (e.g., equation (1) or equation (2) in the foregoing embodiment). The AND gate 726, coupled to the comparator 722 and the comparator 724, outputs the maximum signal to the value updating circuit 730 given that the maximum signal satisfies the check condition.
In conclusion, the present invention provides a device and method for handling symbol rate estimation and interference. The device and method of the present invention stop or continue receiving and handling additional time-domain signals according to whether a (maximum) signal satisfies a check condition. Thus, not only an accurate symbol rate and an accurate frequency of interference are obtained, but also unnecessary power consumption and lock time are reduced, thereby solving the issue that a communication device is required to process an excessive amount and unnecessary time-domain signals.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 105128733 | Sep 2016 | TW | national |
