Device and method for sampling rate conversion

Abstract

A resampler (1) is used to convert a digital input signal string (Sin) with an input sampling rate (fin) into a digital output signal string (Sout) with an output sampling rate (fout). An estimating unit (11) estimates a sampling rate ratio (Rk) between the input sampling rate (fin) and the output sampling rate (fout) and a setpoint phase of the output signal string (Sout). A regulating unit (12) compares an actual phase of the output signal string (Sout) to the setpoint phase, and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio (Rk) and a deviation of the actual phase from the setpoint phase. An interpolator (7) interpolates the input signal string (Sin) for producing the output signal string (Sout) at sampling times whose temporal position is determined by the control signal (RTC,k).

Description

BACKGROUND OF THE INVENTION

[0001] This application claims a foreign priority based on German patent application no. 101 02 166.6, filed Jan. 18, 2001 and the contents of that application are incorporated herein by reference.

[0002] The invention concerns a device for converting a digital input signal string with an input sampling rate into a digital output signal string with an output sampling rate that is different from the input sampling rate. Such a device is generally called a resampler. The invention also relates to a corresponding method.

[0003] Such a resampler is known from European patent document EP 0 665 546 A2, for example. In a resampler, the relationship between the input sampling rate and the output sampling rate must first be determined. In the aforementioned document, this is accomplished through a gate time measurement. The sampled values are interpolated at the output sample times specified by the output sampling rate in an interpolator. In this process, the interpolator is controlled by a detected sampling rate ratio. Since the determination of the sampling rate ratio is subject to measuring inaccuracy, buffering takes place in a buffer store, for example a FIFO, located at the output of the interpolator in the case of down-sampling and at the input of the interpolator in the case of up-sampling. In this regard, the integral behavior of the FIFO memory is exploited. EP 0 665 546 A1 proposes regulating the sampling rate ratio that controls the interpolator as a function of a fill level of the buffer store.

[0004] The regulation of the sampling rate ratio as a function of the fill level of the buffer store proposed in EP 0 665 546 A2 has the disadvantage that when the fill level of the buffer store memory changes, the group propagation-time delay of the digital signal through the resampler changes. In applications such as mobile radio telephony, relatively large changes in buffer store fill level (e.g. +/−1), which is to say a change by one storage unit, are not tolerable since they lead to variations in propagation-time delay of the signal through the resampler. With the buffer store fill level controller proposed in EP 0 665 546 A1, deviations in a clock rate ratio are detected relatively late, after a relatively large detuning of the ratio has already taken place. This leads to larger interpolation errors due to incorrect sampling times.

[0005] Consequently, an object of the invention is to provide a device (resampler) and a method (resampling method) for converting a digital input signal string with an input sampling rate into a digital output signal string with an output sampling rate, which device and/or method functions with high precision.

SUMMARY OF THE INVENTION

[0006] According to principles of this invention, this object is attained with regard to the device through the features of claim 1, and with regard to the method through the features of claim 9. The dependent claims contain advantageous refinements of the device and/or the method.

[0007] The invention is based on the realization that precision in controlling the interpolator and/or in determining the sampling times of the output signal string can be significantly improved if the regulation is not performed solely on the basis of an estimate of the sampling rate ratio between the input sampling rate and the output sampling rate, but also simultaneously on the basis of an estimate of the phase angle. As a result of an inventive phase-coherent regulation, a deviation in the sampling rate ratio is detected before the deviation becomes large enough to lead to a rise or fall in the storage level in the buffer store (FIFO). A great change in the group propagation-time delay through the resampler associated with the change in storage level is thus avoided, and the interpolation precision of the interpolator is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] An embodiment of the resampler and the resampling method in accordance with the invention is described below in detail with reference to the drawings. Shown in the drawings are:

[0009] FIG. 1 is a schematic representation of a resampler;

[0010] FIG. 2 is a block diagram of a resampler in accordance with the invention;

[0011] FIG. 3 is a block diagram of a detailed section of the resampler of the invention for determining a sampling rate ratio and a phase angle;

[0012] FIG. 4 is a block diagram of the timing control unit of the resampler in accordance with the invention;

[0013] FIG. 5 is a block diagram of a regulating device of the resampler in accordance with the invention;

[0014] FIG. 6 is a detailed representation of the regulator of the regulating device shown in FIG. 5;

[0015] FIG. 7 is a diagram explaining the method of operation of the regulating device shown in FIG. 5, and

[0016] FIG. 8 is a diagram explaining the method of operation of the timing control unit shown in FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

[0017] FIG. 1 shows the basic principle of a resampler 1 on which the invention is based. A first digital signal-processing unit 2 operating with the clock fin and a second digital signal-processing unit 3 operating with the clock fout are connected to the resampler 1. The first digital signal-processing unit 2 generates digital sampled values, for example with a width of 24 bits, which are fed to the resampler 1. Moreover, the resampler (sampling rate converter) is provided with a clock vin fin from the first digital signal-processing unit 2 and a clock vout fout from the second digital signal-processing unit 3. vin and vout are integer, whole number, multiples and can preferably be equal to 1. The clocks fin and fout are in general asynchronous and have an arbitrary ratio to one another that in general is not an integer. The resampler 1 has the task of converting the digital sampled values of the first digital signal-processing unit 2 operating with the clock fin into digital sampled values of the second digital signal-processing unit 3 operating with the clock fout. In the case that fout is smaller than fin, we are talking about down-sampling. In the case that fout is larger than fin, we are talking about up-sampling.

[0018] FIG. 2 shows an embodiment of a resampler 1 in accordance with the invention. The case of down-sampling is depicted. A first block 4 of the resampler 1 works at the input clock fin, while a second block 5 of the resampler 1 works at the output clock fout. The digital input signal string Sin supplied to the resampler 1 is fed to an interpolator 7 with the clock fin. An interpolation to generate the sampled values of the output signal string sout at the sampling times corresponding to the output sampling rate fout is performed in the interpolator 7. This is illustrated in FIG. 8. The sampled values A at the sampling times t1, t3, . . . t10 correspond to the input signal string sin, while the sampled values A at the sampling times t′1, t′2, . . . t′6 correspond to the output signal string sout.

[0019] In the illustrated case of down-sampling, the interpolator 7 is followed by a buffer store 6 that is implemented in the embodiment as a FIFO (first-in-first-out). In particular, the buffer store 6 serves during a transient phase to buffer the sampled values generated by the interpolator 7 that are taken out at the output of the buffer store 6 at the clock fout. The goal of the present invention is to keep the fill level of the buffer store 6 exactly constant and to avoid variations in the fill level of the buffer store 6. The interpolator 7 is thus not regulated on the basis of fill level detection of the buffer store 6 as in the prior art, since such regulation can only intervene when the fill level of the buffer store 6 has changed by at least 1. Instead, regulation in accordance with the invention is based on an estimation of the sampling rate ratio R=fin/fout and an additional estimation of the phase angle φ of the output sampling rate fout with reference to the input sampling rate fin.

[0020] In order to determine the sampling rate ratio R, the input sampling rate fin is fed to a counter 8 whose output is sampled at a sampling element 9 at the output sampling rate fout. The signal thus produced passes through a first-order cascaded integrator-comb filter (CIC filter) 10 in this example. This CIC filter 10 is followed by an estimator 11 for estimating the sampling rate ratio R and the phase angle φ. The estimator 11 evaluates each set of N sampled values, and at the end of each such observation interval of length N generates an estimate Rk for the sampling rate ratio fin/fout and for the phase φk for the phase angle position of the output clock fout. These estimates are fed to a regulating unit 12 which generates a control signal RTC,k therefrom. This control signal RTC,k is fed to a timing control unit 13 that generates a time-shift signal Offset that identifies the sampling times t′1, t′2, . . . t′6 of the output signal string sout relative to the sampling times t1, t2, . . . t10 of the input signal string Sin, and generates an indicator signal E that identifies whether or not a sampling time of the output signal string sout is present during a specific sampling interval of the input signal string Sin.

[0021] The individual elements of the resampler 1 in accordance with the invention shown in FIG. 2 are described in detail below.

[0022] FIG. 3 shows a block diagram of the elements for obtaining the sampling rate ratio R, the CIC filter 10 as well as the estimator 11.

[0023] In the case of down-sampling illustrated in FIG. 2, the input sampling rate fin is fed to the counter 8, which can be structured as a single edge counter or double edge counter. The target values from the counter 8 are fed to a Gray encoder 14, which performs a Gray encoding of the target values. Gray encoding has the known property that only one respective bit changes during an increment or decrement. An error in the subsequent sampling in the sampling element 9 at the output sampling rate fout is thus a maximum of 1 bit. The Gray encoding is reversed in the Gray decoder 15 that follows. The Gray encoder 14 and the Gray decoder 15 are optional and can also be omitted. The sampling rate ratio can also be determined by means other than a counter-sampler. In the case of up-sampling, the functions of fin and fout are exchanged.

[0024] In the embodiment illustrated, the output signal of the Gray decoder 15 is fed to the first-order CIC filter 10. In a first stage including an adder 16 and a delay element 17, the sampled values are continuously totaled. In a sampling converter 18, the sampling rate in the embodiment is decreased by a factor of 6, that is only every sixth value of the output of the adder 16 is selected for further processing. In a second stage including a subtracter 19 and a delay element 28, the first value of each block of length N/6 is subtracted from the last value, which is to say that the values at the output of the CIC filter 10 each represent the blockwise total of N/6 sampled values. These blockwise total values are fed to the estimator 11. N represents the length of the intended observation interval of the estimator 11.

[0025] The estimator 11 includes a chain of a plurality of delay elements 20, 21, 22, 23 and 24. Selected initial, intermediate and final values of this delay chain 20-24 are fed to adders 25, 26 and 27 for calculating the estimated values for the sampling rate ratio and to further adders 28, 29 and 30 for calculating the estimated values for the phase. An appropriate scaling is performed in multipliers 31 and 32 before a reduction of the sampling rate by the remaining value 6 takes place in each sampling converter 33 and 34 so that an estimated value Rk for the sampling rate ratio, and an estimated value normalized to 2π for the phase φk/2π, are available at the output of the estimator 11 after each observation interval including N input values.

[0026] The precise method of operation of the estimator shown in FIG. 3 is described in detail in patent application DE 100 39 666 A1 of the same assignee and the same inventor. The content of this patent application DE 100 39 666 A1 is incorporated by reference in full in the present application.

[0027] FIG. 4 shows a block diagram of the timing control unit 13. The regulating unit 12 produces a control signal RTC,k from the estimates of the sampling rate ratio Rk and of the phase φk in a manner that will be described in detail using FIG. 5; this control signal being fed to the timing control unit 13. The control signal RTC,k is reduced by one in an adder 35. It is the task of the timing control unit 13 to provide the interpolator 7 with a time-shift signal (Offset) that characterizes the sampling times t′1, t′2, . . . t′6 of the output signal string sout relative to the sampling times t1, t2, . . . t10 of the input signal string Sin. In this regard, the sampling period of the input signal string Sin in the embodiment is normalized to one. In the case of a different normalization, the appropriate normalization quantity would be subtracted instead of 1. In addition, the control unit 13 generates an indicator signal E, which indicates to the interpolator 7 whether a sampling time of the output signal string sout is present during the next sampling period of the input signal string Sin.

[0028] The output of the adder 35 is connected to a switching device (multiplexer MUX) 36. When the switching device 36 receives a logic “1” at its switching input 41, it connects its output to the adder 35. Otherwise its output is connected to the other input, which is continuously supplied with the value −1. The output of the switching device 36 is connected to an adder 37. The output of the adder 37 is connected to a delay element 38 that shifts each of the digital values by one sampling period tTC0(n), for example t2-t1, of the input signal string Sin. The output of the delay element 38 is connected to the second input of the adder 37 and to a detector 39. The detector 39 determines whether the current output value of the delay element 38 is greater than or less than 1. If the current output value of the delay element 38 is less than 1, the detector 39 produces a logic “1” at its output 40; otherwise it produces a logic “0”. Hence if the current output value of the delay element 38 (register) is less than 1, the value RTC,k−1 is applied to the input of the adder 37; otherwise the value −1 is applied to the input of the adder 37 via the switching element 36. The output values of the delay element 38 form the time-shift signal Offset, whereas the output values of the detector 39 form the indicator signal E.

[0029] The method of operation of the timing control unit 13 shown in FIG. 4, and that of the interpolator 7, are described below with reference to FIG. 8. FIG. 8 shows a signal of the amplitude A, which is sampled in accordance with the input signal string Sin at times t1, t2, t3, t4, t5, t6, t7, t8, t9 and t10. After resampling in the resampler 1, the signal is sampled at times t′1, t′2, t′3, t′4, t′5 and t′6. The time positions of the sampling times t′1, t′2, . . . t′6 of the output signal string sout relative to the sampling times t1, t2, . . . t10 of the input signal string Sin is indicated to the interpolator 7 by the timing control unit 13 by means of the time-shift signal Offset and the indicator signal E.

[0030] In the example shown in FIG. 8, it is assumed that the control signal RTC,k=5/3. The control signal RTC,k is essentially the sampling rate ratio R=fin/fout that is however regulated according to this invention on the basis of the phase estimate in a manner that will be described in detail using FIGS. 5 through 7. It is further assumed that the starting value in the delay element (register) 38 for the time-shift signal Offset=⅔. Since ⅔<1, the indicator signal E=1. For the interpolator 7, this means that a sampled value of the output signal string sout must be generated by interpolation at a sampling time t′1 that lies ⅔ of a sampling period of the input signal string sin later than the time t1.

[0031] The switching device 36 connects the input of the adder 37 with the adder 35 so that the value RTC,k-1=⅔ is added to the register state of the delay element (register) 38 and the value Offset=4/3 now appears at the output of the delay element (register) 38. Since it is true that 4/3>1, the output of the detector 39 is now “0”, and because of this state of the indicator signal E=0, the interpolator 7 performs no interpolation between t2 and t3. On the following clock, as a result of the logic state “0” of the output of the detector 39, −1 is applied to the input of the adder 37 and the signal Offset at the output of the delay element (register) 38 becomes Offset=⅓. Since it is true that ⅓<1, the indicator signal becomes E=1. The interpolator 7 thus performs an interpolation at a position shifted after the time t3 by ⅓ of the sampling period of the input signal string Sin, hence at the position t2 in FIG. 8, to generate the next value of the output signal string Sout.

[0032] On the next clock pulse, the value RTC,k−1=⅔ is again applied to the adder 37 so that the output of the delay element (register) assumes the value 3/3=1. The output of the detector 39 is hence “0”, and the indicator signal E=0, so no interpolation takes place between the times t4 and t5. On the next clock pulse, −1 is applied to the input of the adder 37 and the output of the delay element (register) 38 becomes 0. Since the indicator signal E is set to “1” by the detector 39, the next interpolation then takes place at time t′3=t5. The sequence continues as shown in FIG. 8. In the timing control unit 13, RTC,k is always used for generating N/Vout output values.

[0033] The structure and operation of an embodiment of the regulating unit 12 are described in more detail below using FIGS. 5 through 7.

[0034] FIG. 5 shows an embodiment of the regulating unit 12. After each observation interval, the regulating unit 12 is supplied with an estimated value for the sampling rate ratio Rk and an estimated value normalized to 2π for the phase φk/2π. The index k indexes the observation intervals that are illustrated in FIG. 7. In the example shown in FIG. 7, each observation interval includes six sampled values on the clock fout of the output signal string Sout. In the embodiment of the estimating unit 11 shown in FIG. 3, the estimation respectively takes place at the midpoint of each observation interval. However, for regulation an estimate is needed at the start of the next observation interval. Consequently, a phase offset of N/2·.Rk must be added to the estimated value φk/2π, which is illustrated in FIG. 7 in the center row.

[0035] In the embodiment shown in FIG. 5, an additional phase offset of N/m·Rk is added, where m can be m=12, for example. The purpose of this additional offset is to ensure, even in the case of the largest regulator deviation that can be expected, that the resulting setpoint phase φset,k does not lie before the beginning of the next observation interval. In the embodiment depicted, the aforementioned phase shift is produced by a multiplier (50), which can also be implemented as a bit shift operation (bit shifter) if the phase shift is chosen appropriately, and an adder 51.

[0036] The phase φset,k/2π, normalized to 2π, is compared with the actual phase φactual,k/2π, normalized to 2π, at the beginning of the next observation interval. The deviation Δφk/2πis determined in a subtracter 52 and is supplied to a regulator 53. Also supplied to the regulator 53 are the estimated values for the sampling rate ratio Rk. The regulator 53 works in such a way that the control signal RTC,k produced at the output of the regulator 53 corresponds essentially to the sampling rate ratio Rk estimated in the preceding observation interval, yet this is slightly modified, based on the control variable Δφk/2π, in such a way that the control signal RTC,k achieves the result that, at the end of the observation interval to be regulated, the actual phase φactual,k agrees with the setpoint phase φset,k. Ideally, in the steady state of the regulator, Rk agrees with the control signal RTC,k.

[0037] The actual phase φactual,k, normalized to 2π, of the output signal string Sout is formed in such a way that the control signal RTC,k, which represents the actual sampling rate ratio used by the timing control unit 13, is multiplied by the observation duration N in a multiplier 54. Here, too, the multiplier 54 can be replaced by a bit shift operation (bit shifter) in order to avoid actual multiplication. In this way, the phase shift is determined during the kth observation interval and supplied to the adder 55, whose output is connected to a delay element 56 (register), which each time effects a shift by the length of one observation interval. Except during initialization, which is described below, the switching element 57 is always switched such that its output is connected to the delay element 56. Consequently, the output of the delay element 56 is returned to one of the inputs of the adder 55. Since the output of the delay element (register) 56 represents the actual phase φactual,k at the start of the kth observation interval, the actual phase φactual,k at the beginning of the k+1st observation interval φactual,k+1/2π is calculated by adding the phase φactual,k at the beginning of the kth observation interval to the phase shift produced during the kth observation interval. The actual phase is thus continually updated by taking into account the phase shift occurring in the respective then-current observation interval.

[0038] At the start of the regulation, the actual phase is not known. Consequently, at the start of regulation during initialization, the output of the adder 51 is connected to the +input of the subtracter 52 through the switching element (multiplexer MUX) 57, so that the control variable Δφk/2π is initially 0 because of the identity of the input signals of the subtracter 52.

[0039] FIG. 6 shows an embodiment of the regulator 53. In this embodiment, the regulator 53 takes the form of a proportional controller, that is, the change made in the estimated sampling rate ratio Rk is proportional to the control variable Δφk/2π, where the proportionality factor in the embodiment shown is ¾N. The proportionality factor and the control variable Δφk/2π are fed to a multiplier 58, which can be implemented as a bit shift operation (bit shifter) if the proportionality factor is chosen appropriately. The actual regulation is accomplished by a subtracter 59, to which are fed the output of the multiplier 58 and the estimated values of the sampling rate ratio Rk.

[0040] The method of operation of the regulating unit 12 shown in FIG. 5 is described in more detail using FIG. 7. In the first row of FIG. 7, the sampling times of the output signal string Sout, which are represented for example by the rising edges of the fout clock pulses, are illustrated by arrows. In the second row, it is indicated in each case that the estimating unit 11 determines an estimate normalized to 2π for the phase Δφk/2π for the midpoint of each observation interval. In order to obtain the phase for the output clock fout at the beginning of each subsequent observation interval, each phase in this example must be shifted by 3.5·Rk. This results in the setpoint phase φset,k at the start of the next observation interval.

[0041] In the first observation interval, no regulation can be performed yet since the estimates R1 and φ1 are determined for the first time during this observation interval. In the second observation interval, the starting phase φstart/2π is established by the switching device (multiplexer) 57 that is used to initialize the actual phase of the regulating device 12. At the end of the second observation interval, the control variable Δφ2/2π, which represents the deviation of the actual phase from the setpoint phase at the end of the second observation interval, can be determined for the first time. In the example illustrated in FIG. 7, the clock fout during the second observation interval was too long. The clock fout is reduced during the third observation interval such that ideally the actual phase agrees exactly with the setpoint phase at the end of the third observation interval.

[0042] The regulation unit in accordance with the invention continuously corrects the sampling rate ratio, especially when there is a change in the input sampling rate fin or the output sampling rate fout. A change in the fill level of the buffer store (FIFO) 6 can be avoided in the steady state of the regulator, so that no relatively large changes in the group propagation-time delay through the resampler 1 occur.

[0043] The invention is not limited to the embodiment shown. In particular, the estimating unit 11 can also be configured differently from that shown in FIG. 3. Other implementations of the regulating unit 12 and the time control unit 13 than those shown in FIGS. 4 and 5 are also conceivable. The invention can also find application for a resampler 1 in up-sampling operation, wherein the functions of fin and fout in FIG. 2 must be exchanged and the buffer store (FIFO) 6 must be placed ahead of the interpolator 7.

Claims

1. Device for converting a digital input signal string (Sin) with an input sampling rate (fin) into a digital output signal string (Sout) with an output sampling rate (fout), including: an estimating unit (11) that estimates a sampling rate ratio (Rk) between the input sampling rate (fin) and the output sampling rate (fout) and a setpoint phase (φset,k) of the output signal string (Sout), a regulating unit (12) that is connected to the estimating unit (11) and which compares the actual phase (φactual,k) of the output signal string (Sout) with the setpoint phase (φset,k) of the output signal string (Sout), and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio (Rk) and the deviation (Δφk) of the actual phase (φactual,k) from the setpoint phase (φset,k), and an interpolator (7) that interpolates the input signal string (Sin) for producing the output signal string (Sout) at the sampling times (t′1, t′2, . . . t′6), whose temporal position is determined by the control signal (RTC,k).

2. Device according to claim 1, wherein the regulating unit (12) includes a regulator (53) that increasingly raises or lowers the sampling rate ratio (Rk) with increasing deviation (Δφk) of the actual phase (φactual,k) from the setpoint phase (φset,k) to generate the control signal (RTC,k).

3. Device according to claim 2, wherein the regulator (53) is a proportional controller that raises or lowers the sampling rate ratio (Rk) proportionately to the deviation (Δφk) of the actual phase (φactual,k) from the setpoint phase (φset,k).

4. Device according to claim 1, wherein the estimating unit (11) estimates the phase (φk) of the output signal string (Sout) at the midpoint of each observation interval upon which the estimate is based, and an adder (51) is provided that adds a phase offset (N/2·Rk) corresponding to half the length (N/2) of the observation interval and another phase offset (N/m·Rk) that is greater than the maximum expected deviation (Δφk) of the actual phase (φactual,k) from the setpoint phase (φset,k).

5. Device according to claim 1, wherein the regulating unit (12) includes a switching device (57) that, during a first regulating period, supplies the setpoint phase (φset,k) to a subtracter, and during subsequent regulating periods supplies the actual phase (φactual,k) delayed by an observation interval in a delay element (56).

6. Device according to claim 1, wherein there is a timing control unit (13) between the regulating unit (12) and the interpolator (7) that generates from the control signal (RTC,k) a time-shift signal (Offset) that identifies sampling times (t′1, t′2, . . . t′6) of the output signal string (sout) relative to sampling times (t1, t2, . . . t10) of the input signal string (sin), and generates an indicator signal (E) that identifies if a sampling time (t′1, t′2, . . . t′6) of the output signal string (sout) is present during a specific sampling interval (t1-t2, t2-t3, . . . t9-t10) of the input signal string (sin).

7. Device according to claim 6, wherein the timing control unit (13) includes an adder (37) whose output is connected to an input of a delay element (38) and whose first input is connected to the output of the delay element (38), wherein the output of the delay element (38) is connected to a detector (39), which determines whether the output value of the delay element (38) is less than a scaled sampling period of the input signal string (Sin), and wherein the control signal (RTC,k), which has been reduced by the scaled sampling period, is fed to the second input of the adder (37) when the detector (39) determines that the output value of the delay element (38) is less than the scaled sampling period of the input signal string (Sin), and the scaled sampling period is supplied to the second input of the adder (37) when the detector (39) determines that the output value of the delay element is greater than or equal to the scaled sampling period of the input signal string (Sin).

8. Device according to claim 7, wherein the time-shift signal (Offset) is taken from the output of the delay element (38) and the indicator signal (E) is taken from the output of the detector (39).

9. Method for converting a digital input signal string (Sin) with an input sampling rate (fin) into a digital output signal string (Sout) with an output sampling rate (fout), having the following process steps: estimating (11) the sampling rate ratio (Rk) between the input sampling rate (fin) and the output sampling rate (fout), and the setpoint phase (φset,k) of the output signal string (Sout), comparing (52) the actual phase (φactual,k) of the output signal string (Sout) with the setpoint phase (φset,k) of the output signal string (Sout), generating (53) a control signal (RTC,k) as a function of the estimated sampling rate ratio (Rk) and the deviation (Δφk) of the actual phase (φactual,k) from the setpoint phase (φset,k), and interpolating (7) the input signal string (Sin) to generate the output signal string (Sout) at sampling times (t′1, t′2, . . . t′6) whose temporal position is specified by the control signal (RTC,k),.

10. Method in accordance with claim 9, wherein the sampling rate ratio (Rk) is increasingly raised or lowered with increasing deviation (Δφk) of the actual phase (φactual,k) from the setpoint phase (φset,k) to generate the control signal (RTC,k).

11. Method in accordance with claim 9, wherein the phase (φk) of the input signal string (Sin) is estimated at the midpoint of each observation interval upon which the estimate is based, and a phase offset (N/2·-Rk) that corresponds to half the length (N/2) of the observation interval, and another phase offset (N/m·Rk) that is greater than the maximum expected deviation (Δφk) of the actual phase (φactual,k) from the setpoint phase (φset,k), are added to the estimated phase (φk).

12. Method in accordance with claim 9, wherein a timing control (13) takes place for controlling the sampling times (t′1, t′2, . . . t′6) of the output signal string (sout), and a time-shift signal (Offset) that identifies the sampling times (t′1, t′2, . . . t′6) of the output signal string (sout) relative to the sampling times (t1, t2, . . . t10) of the input signal string (sin), and an indicator signal (E) that identifies whether a sampling time (t′1, t′2, . . . t′6) of the output signal string (sout) is present during a specific sampling interval (t1-t2, t2-t3, . . . t9-t10) of the input signal string (sin), are generated from the control signal (RTC,k).