BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating an example of a conventional two-point modulator.
FIG. 2 is a block diagram illustrating a two-point modulation device according to an exemplary embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating the second sigma-delta modulator (SDM) in FIG. 2.
FIG. 4 is a flow chart illustrating a method of two-point modulation according to an exemplary embodiment of the present invention.
FIG. 5 is a flow chart illustrating a process of generating a voltage-controlled oscillating frequency signal in FIG. 4.
FIG. 6 is a block diagram illustrating a two-point modulation circuit according to an exemplary embodiment of the present invention.
FIG. 7 is a block diagram illustrating a two-point modulation-based transceiver according to an exemplary embodiment of the present invention.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
Exemplary embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Like reference numerals refer to like elements throughout this application.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present.
FIG. 2 is a block diagram illustrating a two-point modulation device according to an exemplary embodiment of the present invention. Referring to FIG. 2, the two-point modulation device 100 includes a first SDM 110, a second SDM 120, and an analog PLL 130. The first SDM 110 receives channel data and modulation data to provide a division control signal. An adder 115, which combines the channel data and the modulation data, may be included in the first SDM 110. The second SDM 120 receives the modulation data to provide a feedforward path modulation signal. The division control signal and the feedforward path modulation signal may be digital signals.
The analog PLL 130 may include a divider 140, a PFD 150, a charge pump 160, a loop filter 170, and a VCO 180. The divider 140 divides a voltage-controlled oscillating frequency signal Fout provided from the VCO 180 in response to the division control signal from the first SDM 110, and provides the divided voltage-controlled oscillating frequency signal Fout to the PFD 150. The PFD 150 receives a reference frequency signal Fref and the divided voltage-controlled oscillating frequency signal Fout, and detects a phase/frequency difference between the reference signal Fref and the divided voltage-controlled oscillating frequency signal Fout. The charge pump 160 generates a current signal for charging or discharging the loop filter 170 according to an output signal of the PFD 150. The loop filter 170 performs low-pass filtering on an output signal of the charge pump 160. The VCO 180 receives the feedforward path modulation signal and generates the voltage-controlled oscillating frequency signal Fout that oscillates in response to an output signal of the loop filter 170. The VCO may simultaneously perform analog tuning and digital tuning. The analog tuning may be performed based on the output signal provided from the loop filter 170, and the digital tuning may be performed based on the feedforward path modulation signal provided from the second SDM 120. A frequency resolution of the carrier frequency may be controlled by the analog PLL 130, and a frequency resolution of the modulation data may be controlled by the feedforward modulation signal that has a relatively broad margin.
The two-point modulation device 100 may be implemented using a relatively small chip size and system characteristics may be degraded less when the feedback path and the feedforward path are combined. In addition, the two-point modulation device 100 may be used as a frequency synthesizer in a receiver if the feedforward path including the second SDM 120 is deactivated.
FIG. 3 is a circuit diagram illustrating the second SDM in FIG. 2. The second SDM 120 may be implemented with a fourth-order 3-bit modulator as illustrated in FIG. 3. Referring to FIG. 3, the second SDM 120 includes first through fourth sigma-delta modulation units 210, 220, 230, and 240, a quantizer 250, and a control signal generator 260. The first sigma-delta modulation unit includes an adder 214, an accumulator 216, and a feedback coefficient provider 218. The second, third and fourth sigma-delta modulation units 220, 230 and 240 include adders 224, 234 and 244, accumulators 226, 236 and 246, feedback coefficient providers 228, 238 and 248, and weighted coefficient providers 222, 232 and 242, respectively. The sigma-delta modulation units 210, 220, 230 and 240 perform a sigma-delta modulation based on the multi-bit (e.g., 3-bit) modulation data and the feedback coefficients (b1, b2, b3 and b4). The quantizer 250 quantizes the output signal of the fourth sigma-delta modulation unit 240, and provides the quantized signal to the control signal generator 260. The control signal generator 260 generates a control signal, which is fed back to the feedback coefficient providers 218, 228, 238 and 248 respectively included in the sigma-delta modulation units 210, 220, 230 and 240.
FIG. 4 is a flow chart illustrating a method of two-point modulation according to an exemplary embodiment of the present invention. Referring to FIG. 4, in the method of two-point modulation, a division control signal is provided based on channel data and modulation data (step S510). A feedforward path modulation signal is provided based on the modulation data (step S520). A frequency resolution of the modulation data may be controlled in step S520. The division control signal and the feedforward path modulation signal may be digital signals. A voltage-controlled oscillating frequency signal that follows a reference frequency signal is generated based on the division control signal and the feedforward path modulation signal (step S530). A frequency resolution of the voltage-controlled oscillating frequency signal may be controlled in step S530.
FIG. 5 is a flow chart illustrating the process of generating a voltage-controlled oscillating frequency signal in FIG. 4. Referring to FIG. 5, the voltage-controlled oscillating frequency signal may be generated by the following steps. The voltage-controlled oscillating frequency signal is divided based on the division control signal (step S610). A phase/frequency difference between a reference frequency signal and the divided voltage-controlled oscillating frequency signal is detected (step S620). A current signal is generated based on the detected phase/frequency difference (step S630). The current signal is low-pass filtered to provide a control voltage (step S640). The feedforward path modulation signal is received and the voltage-controlled oscillating frequency signal that oscillates in response to the control voltage is generated (step S650).
The operations as described with reference to FIGS. 4 and 5 may be performed by using the two-point modulation device in FIGS. 2 and 3.
FIG. 6 is a block diagram illustrating a two-point modulation circuit according to an exemplary embodiment of the present invention. Referring to FIG. 6, a two-point modulation circuit 600 includes a first SDM 710, a second SDM 720, an analog PLL 730, and a VCO gain control unit 740. The analog PLL includes a divider 750, a PFD 760, a charge pump 770, a loop filter 780, and a VCO 790.
The first SDM 710 receives combined channel data and modulation data, and provides a division control signal to the divider 750. An adder 715, which combines the channel data and the modulation data, may be included in the first SDM 710. The division control signal may be a digital signal.
The second SDM 720 receives combined modulation data and a VCO gain control signal as an output signal of the VCO gain control unit 740, and provides a feedforward path modulation signal to the VCO 790. An adder 725, which combines the modulation data and the VCO gain control signal, may be included in the second SDM 720. The feedforward path modulation signal may be a digital signal. A gain of the VCO 790 may be controlled by using digital codes. The VCO gain control unit 740 receives a reference frequency signal Fref and a voltage-controlled oscillating frequency signal Fout, and provides the VCO gain control signal to the second SDM 740.
Operations of the divider 750, the PFD 760, the charge pump 770, the loop filter 780, and the VCO 790 in FIG. 6 are substantially the same as operations of the divider 140, the PFD 150, the charge pump 160, the loop filter 170, and the VCO 180 in FIG. 2.
FIG. 7 is a block diagram illustrating a two-point modulation-based transceiver according to an exemplary embodiment of the present invention.
Referring to FIG. 7, the two-point modulation-based transceiver 700 includes a transmitter unit 802 and a receiver unit 804. The transmitter unit 802 includes a first SDM 810, a second SDM 820 and an analog PLL 830. The analog PLL includes a divider 832, a PFD 833, a charge pump 834, a loop filter 835, and a VCO 836. A reference frequency generator 837 may be included in the transmitter unit 802. The reference frequency generator 837 generates a reference frequency. The operation and circuit structure of the transmitter unit 830 are similar with those of the two-point modulation device 100 in FIG. 2.
The receiver unit 804 includes a frequency synthesizer 850, a demodulator 860, a frequency multiplier 870, and a post-processor 880. The frequency synthesizer 850 down-converts the voltage-controlled oscillating frequency signal to provide an intermediate frequency signal. The demodulator 860 demodulates the intermediate frequency signal to provide a demodulation signal (i.e., a demodulated intermediate frequency signal) to the post-processor 880. The post-processor 880 processes the demodulation signal to a baseband signal. The frequency multiplier 870 multiplies the reference frequency signal by a predetermined factor M, and provides a multiplied reference frequency signal to the frequency synthesizer 850.
While exemplary embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the scope of the invention.
Patent Application
20080074208
