Device and system with global tamper resistance

Description

FIELD OF THE DISCLOSURE

This disclosure relates generally to hardware verification, and in particular but not exclusively, to binding authentication to protect against tampering and subversion by substitution.

BACKGROUND

A desirable characteristic of PUF-enabled systems is tamper resistance: modifying hardware changes the unique physical characteristics that influence the PUF input-output mapping. If a device's identity is based on the PUF, then modifications to the device's hardware will also result in modifications to the device's digital identity.

SUMMARY OF THE DISCLOSURE

Various approaches have been presented to prevent the extraction of shares that compose a device's local identity based on hardware intrinsic properties. Approaches also exist for constructing an identity for a set of two or more devices by allocating each device shares of the joint identity. It is realized that such constructions do not prevent an adversary from systematically extracting the share of the joint identity from each device after the shares are generated. Thus, the local tamper resistance can be improved to extend to tamper resistance of the larger system composed of two or more devices.

According to an embodiment of an authentication system, multiple PUF-enabled devices or components are able to jointly perform cryptographic operations. Some embodiments may be implemented such that the cryptographic operation will be computed successfully so long as no adversarial tampering occurs on more than a threshold number of the devices. In one example, each PUF-enabled device or component is equipped with at least two shares of a threshold cryptosystem, and at least t devices must each use at least two of their shares in order to successfully compute the cryptographic operation. This construction can be employed to mitigate adversarial tampering attacks, which attempt to extract shares from a device in the authentication system.

According to one aspect, an authentication system including a plurality of components for jointly executing cryptographic operations based on a shared global identity is provided. The system comprises at least a first component and a second component having respective hardware intrinsic identity circuits configured to generate hardware specific outputs responsive to input challenges, and at least one processor configured to: combine outputs of threshold operations on a plurality of shares associated with a first component identity and map to at least a first and a second share of a global identity comprising a public encryption key and associated secret, combine outputs of threshold operations on a plurality of shares associated with a second component identity and map to at least a third and a fourth share of the global identity, and enable execution of a cryptographic operation based on shares of the global identity, the global identity comprising the public encryption key and associated secret.

According to one embodiment, at least the first and second components comprise discrete or separate systems that collaborate to enable the cryptographic operation based on the global identity. According to one embodiment, the hardware intrinsic identity circuit comprises a physically unclonable function circuit (a “PUF”). In other embodiments, other circuits can be used that exhibit properties of PUFs. For example, a circuit having a physically unclonable property can be used. In another example, a circuit having tamper resistance can be used. In various embodiments, the properties of unclonability and tamper resistance are provided to increase security and resistance to attack. According to one embodiment, the system components can be discrete or separate systems that collaborate to use global identity for cryptographic operations (e.g., digital signature, encryption, decryption, component validation, etc.). According to another embodiment, the system components can be components of a discrete system, and the components internal to the discrete system can collaborate to use the global identity as a whole system identity for cryptographic operations.

According to one embodiment, the at least one processor is configured to combine the outputs of threshold operations on a plurality of shares associated with a first component identity and map to at least a first and a second share of a global identity based on the outputs of the threshold operations on the plurality of shares associated with the first component identity. In further embodiments, mapping to the first and second share of the global identity can include further threshold operations or obscured operations to limit the presence of the shares in memory. In other embodiments, mapping to the first and second share of the global identity can include recovering the actual shares.

According to one embodiment, the at least one processor is configured to map challenges and respective helper values to the plurality of shares of a secret associated with the first component identity. According to one embodiment, the first component identity comprises a public key and a secret associated with the first component.

According to one embodiment, the at least one processor is configured to map challenges and respective helper values to shares of the plurality of shares of the second component identity. According to one embodiment, the second component identity comprises a public key and secret associated with the second component.

According to one embodiment, only one share of an associated identity is in memory at a time. According to one embodiment, shares corresponding to an identity are used or recovered one at a time to prevent capture of multiple shares by an adversary. Threshold operations can be executed on the individual shares and combined with threshold operations on later used or recovered shares to enable the operations on the secret without actually constructing the secret in memory or having the underlying shares associated with the secret in memory at any given time period. According to one embodiment, the first component includes a first hardware intrinsic identity circuit, a first processor, and a first communication interface.

According to one embodiment, the second component includes a second hardware intrinsic identity circuit, a second processor, and a second communication interface. According to one embodiment, the at least one processor is configured to enroll at least the first component and the second component into the global identity, and encode respective shares of the global identity based on respective identities of the first and the second component. According to one embodiment, the at least one processor is configured to define, during enrollment, a threshold sharing of the global identity between at least the first component and the second component that requires a minimum of two shares from a minimum of two devices to enable cryptographic operations based on the threshold sharing of the global identity.

According to one embodiment, the at least one processor during enrollment defines a threshold sharing of the global identity that requires a minimum of two shares from one component to enable cryptographic operations with the associated secret of the threshold sharing of the global identity. According to one embodiment, the system further comprises a memory connected to the at least one processor, wherein the at least one processor is configured to store challenge values and corresponding helper values in the memory. According to one embodiment, the respective hardware intrinsic identity circuits include a physically unclonable function circuit (PUF).

According to one aspect, a computer implemented method for jointly executing cryptographic operations based on a global identity is provided. The method comprises generating at least a first and a second hardware intrinsic identity circuit respective hardware specific outputs responsive to input challenges, combining, by at least one processor, outputs of threshold operations on a plurality of shares associated with a first component identity, mapping, by the at least one processor, challenges to at least a first and a second share of a global identity comprising a public encryption key and associated secret, combining, by the at least one processor, outputs of threshold operations on a plurality of shares associated with a second component identity, mapping, by the at least one processor, challenges to at least a third and a fourth share of the global identity, and enabling execution of a cryptographic operation associated with the global identity, the global identity comprising the public encryption key and associated secret.

According to one embodiment, the method further comprises mapping by the at least one processor challenges and respective helper values to the plurality of shares of the first component identity. According to one embodiment, the first component identity comprises a public key and secret associated with the first component. According to one embodiment, the method further comprises mapping by the at least one processor challenges and respective helper values to shares of the plurality of shares of the second component identity. According to one embodiment, the second component identity comprises a public key and secret associated with the second component.

According to one embodiment, wherein only one share of an associated identity is in memory at a time. According to one embodiment, the first component includes a first hardware intrinsic identity circuit, a first processor, and a first communication interface, and act of combining, by at least one processor, outputs of threshold operations on a plurality of shares associated with a first component identity is executed on the first processor of the first component. According to one embodiment, the second component includes a second hardware intrinsic identity circuit, a second processor, and a second communication interface, and the act of combining, by the at least one processor, outputs of threshold operations on plurality of shares associated with a second component identity is executed on the second processor of the second component.

According to one embodiment, the method further comprises enrolling, by the at least one processor, at least the first component and the second component into the global identity; and encoding, by the at least one processor, respective shares of the global identity based on respective identities of the first and the second component. According to one embodiment, the act of enrolling includes defining, by the at least one processor, a threshold sharing of the global identity between at least the first component and the second component to require a minimum of two shares from a minimum of two devices to enable cryptographic operations based on the associated secret of the threshold sharing of the global identity. According to one embodiment, the act of enrolling includes defining, by the at least one processor, a threshold sharing of the global identity to require a minimum of two shares from one component to enable cryptographic operations based on the associated secret of the threshold sharing of the global identity.

According to one embodiment, the method further comprises accessing from a memory connected to the at least one processor, stored challenge values and corresponding helper values in the memory; and communicating the challenge values to respective hardware intrinsic identity circuits. According to one embodiment, the hardware intrinsic identity circuit includes a physically unclonable function circuit (PUF).

According to one aspect, an authentication device including a plurality of components for jointly executing cryptographic operations based on a global identity is provided. The system comprises a plurality of components having hardware intrinsic identity circuits configured to generate respective hardware specific outputs responsive to input challenges, and at least one processor configured to: combine outputs of threshold operations on a plurality of shares associated with respective ones of the plurality of components and map to at least two respective shares of a global identity from at least two respective ones of the plurality of components, and enable execution of a cryptographic operation associated with the global identity, wherein the global identity comprises a public encryption key and associated secret.

According to one embodiment, the at least one processor defines is configured to define a threshold sharing of the global identity between the plurality of components that requires a minimum of two shares from a minimum of two devices to enable cryptographic operations based on the threshold sharing of the global identity.

According to one aspect, at least one non-transitory storage medium storing processor-executable instructions that, when executed, perform a method is provided. The method comprises generating using at least a first and a second hardware intrinsic identity circuit respective hardware specific outputs responsive to input challenges, combining outputs of threshold operations on a plurality of shares associated with a first component identity, recovering at least a first and a second share of a global identity, combining outputs of threshold operations on plurality of shares associated with a second component identity, recovering at least a third and a fourth share of the global identity, and enabling execution of a cryptographic operation associated with the global identity, wherein the global identity comprises a public encryption key and associated secret.

According to various embodiments of the at least one non-transitory medium, the method executed by the processor-executable instructions includes executing any of the preceding method steps.

According to one aspect, least one non-transitory storage medium storing processor-executable instructions that, when executed, perform a method is provided. The method comprises generating using a plurality of components having hardware intrinsic identity circuits respective hardware specific outputs responsive to input challenges, combining outputs of threshold operations on a plurality of shares associated with respective ones of the plurality of components recovering at least two shares of a global identity from at least two of the plurality of components, and enabling execution of a cryptographic operation associated with the global identity based on the at least two shares from the at least two of the plurality of system components, wherein the global identity comprises a public encryption key and associated secret.

According to various embodiments of the at least one non-transitory medium, the method executed by the processor-executable instructions includes executing any of the preceding method steps.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional diagram of a system where each device has one external threshold share;

FIG. 2 is a functional diagram of a system where each device has two or more external threshold shares;

FIGS. 3A and 3B are a flow chart of global PUF distributed key generation; and

FIG. 4 illustrates an example process flow for using a global identity, according to one embodiment.

DETAILED DESCRIPTION

According to one aspect, to securely store shares of the joint system identity, a PUF-enabled device or system component uses hybrid encryption to store sensitive values. Algorithm 1 provides an example of a hybrid encryption approach. According to some embodiments, various devices can employ already established local identities. For example, each device can have a local identity based on hardware intrinsic properties of the device. U.S. application publication number 2017/0063559 (incorporated herein by reference in its entirety) describes examples of encoding a hardware intrinsic identity and may be used to generate a local identity for respective devices or components to support a tamper resistant global identity as discussed herein.

Algorithm 1 PUF-Store-External

Goal: Store external value V_i

for PUF Device p_ido

Sample symmetric key k uniformly and randomly from 2^λ

(where λ is the security parameter of a symmetric cipher)

Write E_k(V_i) to non-volatile memory

(where E is a symmetric cipher)

Write E(p_i^pub, k) to non-volatile memory

(where E is an asymmetric cipher using public key p_i^pubto encrypt value

k)

end for

In Algorithm 1, a device begins storing a value V_iby encrypting it with a symmetric encryption algorithm E(·) and a uniformly and randomly generated symmetric encryption key k. The security parameter of the symmetric encryption algorithm (number of bits in the key) is denoted λ, and thus the key is sampled from the space 2^λ. E_k(V_i) denotes the symmetric encryption of V₁with key k, which is written to the device's memory.

Next, the device's public identity (e.g., asymmetric public identity key p_i^pub(with corresponding private key p_i^privlinked to the device's PUF)) is used to encrypt (e.g., asymmetrically) the encryption key k. This is denoted E(p_i^pub,k), where E(·,·) is an asymmetric encryption algorithm using public key p_i^pubto encrypt value k.

When the value V_iis to be recovered by the device, the process is reversed. This is summarized in Algorithm 2.

Algorithm 2 PUF-Retrieve-External

Goal: Retrieve external value V_i

for PUF Device d do

Read E(p_i^pub, k) from non-volatile memory

k ← ( custom character

= decrypt, E(p_i^pub, k))

V_i← D_k(E_k(V_i))

end for

First, the symmetric key k is recovered by performing asymmetric decryption as ( custom character =decrypt, E(p_i^pub, k)) using Algorithm 3. Then, symmetric decryption is performed using k as D_k(E_k(V_i)) to recover the value V_i.

Algorithm 3 Internal-PUF-Threshold-OP-Staggered

Goal: Perform threshold operation custom character

at time τ

One-Time Setup Stage

for each Threshold Share r_ido

Run Algorithm 11: Enrollment, Publicize p_i^pub

end for

Run (2, 2)-PUF-DKG Protocol, Publicize custom character

^pub

Evaluation Stage

for each Threshold Share r_ido

PUF-Share-Update-Preparation

end for

for each Threshold Share r_ido

Recover share r_i^(τ)←PUF-Retrieve(c_i^(τ), helper_i^(τ))

custom character

←

(r_i^(τ)), Local threshold operation

Update share

r_i^(τ+1)← PUF-Share-Update-Application(r_i^(τ))

Store r_i^(τ+1)and update PUF challenge:

{c_i^(τ+1), helper_i^(τ+1)} ← PUF-Store(r_i^(τ+1))

end for

return custom character

← Combine({ custom character

})

Algorithms 1 and 2 will be used to securely store and retrieve a device's shares of a joint identity representing a set of two or more devices. Algorithm 12 describes how this set of devices generates a joint public identity custom character ^puband allocates each of two (or more) shares {r_i,r_2i} of the joint identity to each device p_i.

FIG. 1 illustrates a set of devices that have been allocated only a single share of the joint public identity custom character ^pub. In this configuration, an adversary may wait until the device recovers its share of the joint identity, and then probe the device to extract the share. Although the device will never be able to recover the share in the future, the adversary may now masquerade as the device to this external system. An adversary can masquerade as the entire group by iteratively extracting the share from each device after each device recovers its share until t shares are recovered.

FIG. 2 illustrates a set of devices that have been allocated two (or more) shares of the joint public identity custom character ^pub. In this configuration, an adversary may wait until the device recovers one of its shares, and then probe the device to extract the share. However, neither the adversary nor the device will be able to recover the device's remaining shares, as the PUF mapping will have been altered by the act of tampering. Thus, by allocating two (or more) shares to each device and setting the threshold to 2t (rather than t), the external system and its global identity retains the same degree of tamper detection as each individual device.

According to some embodiments, various circuit constructions can be employed that provide challenge response functionality. In some examples, a hardware intrinsic identity circuit provides for a hardware based identity, which can include PUFs. In other examples, the hardware intrinsic identity circuit can provide tamper resistance and/or unclonability properties to improve the security of the system.

In one embodiment of the present invention, the shares of the joint external identity may be refreshed. Algorithm 5 describes how each device p_iprepares to update their shares of the joint external identity custom character ^pub.

Algorithm 4 PUF-DKG-Global

Goal: Generate global shares of master private key custom character

for 1 ≤ i ≤ n do

Select random polynomial f_i(·) = c₀⁽ⁱ⁾+ . . . + c_2t−1⁽ⁱ⁾x^2t−1mod q

Compute f_i(j), ∀j ϵ [1, . . . , 2n]/{i, 2i}

Privately send f_i(j), f_i(2j) to particiant p_j, ∀j ϵ [1, . . . , n]/i

Broadcast coefficient commitments {c_k⁽ⁱ⁾· G mod p}_{kϵ[0, . . . , 2t-1]}

Broadcast share commitments {f_i(j) · G mod p}_{jϵ[1, . . . , 2n]}

for 1 ≤ i ≤ n do

Verify

f_{j} (i) \cdot G \overset{?}{=} \sum_{k = 0}^{2 t - 1} i^{k} (c_{k}^{(j)} \cdot G) \mod p

Verify

f_{j} (2 i) \cdot G \overset{?}{=} \sum_{k = 0}^{2 t - 1} {(2 i)}^{k} (c_{k}^{(j)} \cdot G) \mod p

Verify

c_{0}^{(j)} \cdot G \overset{?}{=} \sum_{k = 1}^{2 t} ((\prod_{\underset{k \neq j}{k = 1}}^{2 t} \frac{- j}{k - j}) f_{j} (k) \cdot G) \mod p

end for

Recover shares

r_{i} = \sum_{j = 1}^{n} ((\prod_{\underset{j \neq i}{j = 1}}^{2 t} \frac{- j}{i - j}) f_{j} (i)) \mod q

PUF-Store-External(r_i)

r_{2 i} = \sum_{j = 1}^{n} ((\prod_{\underset{j \neq 2 i}{j = 1}}^{2 t} \frac{- j}{2 i - j}) f_{j} (2 i)) \mod q

PUF-Store-Externa1(r_2i)

Recover public key

𝒫^{pub} = r \cdot G = \sum_{j = 1}^{n} \sum_{i = 1}^{2 n} ((\prod_{\underset{j \neq i}{j = 1}}^{2 t} \frac{- j}{i - j}) f_{j} (i) \cdot G) \mod p

end for

Algorithm 5 External-Share-Update-Preparation

Goal: Prepare update to construct external share r_i^(τ+1)

for all Participants p_i∈ custom character

do

Select random polynomial of degree (2t − 1) such that δ_i(0) = 0:

δ_i(•) = Δ₁⁽ⁱ⁾x + • • • + Δ_m⁽ⁱ⁾x^2t−1

Compute

{ϵ_im= Δ_m⁽ⁱ⁾• G}_{m∈[1...2t−1]}

{u_ij= δ_i(j)}_j∈[1...2n]

{e_ij= ENC_j(u_i(j), u_i(2j))}_j∈[1...n]

Broadcast

VSS_i^(τ)= custom character

i, τ, {ϵ_im}, {e_ij} custom character

,

SIG_i(VSS_i^(τ))

end for

Next, each participant verifies the update information received from other participants and applies the update to its shares as set forth in Algorithm 6.

Algorithm 6 External-Share-Update-Application

Goal: Apply external share update to construct {r_i^(τ+1), r_2i^(τ+1)}

for all Participants p_iϵ custom character

do

Recover share r_i^(τ)

r_i^(τ) ← PUF-Retrieve-External (E(p_i^pub, k), E_k(r_i))

Verify ∀j ≠ i

{DEC}_{i} ({ENC}_{i} (u_{ji})) \cdot G \overset{?}{=} \sum_{ℓ = 1}^{t} i^{ℓ} ϵ_{j ℓ}

Update share as:

r_{i}^{(τ + 1)} \leftarrow r_{i}^{(τ)} + (\sum_{j = 1}^{2 n} u_{ji} \mod q)

Recover share r_2i^(τ)

r_2i^(τ) ← PUF-Retrieve-Externa1 (E(p_i^pub, k), E_k(r_2i))

Verify ∀j ≠ 2i

{DEC}_{i} ({ENC}_{i} (u_{j (2 i)})) \cdot G \overset{?}{=} \sum_{ℓ = 1}^{t} {(2 i)}^{ℓ} ϵ_{j ℓ}

Update share as:

r_{2 i}^{(τ + 1)} \leftarrow r_{2 i}^{(τ)} + (\sum_{j = 1}^{2 n} u_{j (2 i)} \mod q)

end for

The dynamic nature of shares in this construct also permits an embodiment in which the number of participants n participating in a group can be varied dynamically so that participants may join or leave the set of participants in the (t, n) threshold system. In this case, up to n−t participants can be removed from the set custom character simply by leaving them out of the next share refresh protocol. To add a participant p_jto the set of participants, each current participant p_igenerates an extra share u_ijfrom their share update polynomial δ_i(·).

To add a new participant p_newwith ID new to the set of participants, their share f(new) must be generated by t members with existing shares. This is performed by each of the t members contributing their share interpolated for p_new, and blinding these sub-shares with a sharing of zero distributed among the t members. The blinding by a sharing of zero prevents recovery of the t shares r_ifrom the sub-shares. That is, as the t participants are known, distributing a sub-share as

$(r_{i} \cdot (\prod_{\underset{j \neq i}{j = 1}}^{t} \frac{new - j}{i - j})) \mod q$

allows the participant p_newto remove the Lagrangian interpolation term

$(\prod_{\underset{j \neq i}{j = 1}}^{t} \frac{new - j}{i - j})$

and recover p_i's share r_i, as the t members that contribute sub-shares are known to p_new. To prevent p_newfrom recovering an existing share r_ifrom the sub-share, each sub-share is blinded using separate shares of a sharing of 0 among the t members. Algorithm 7 describes how shares of 0 are generated and distributed to the other existing t members.

Algorithm 7 Share-Blinding

Goal: Prepare a sharing of 0

for all Participants p_i∈ custom character

do

Select random polynomial of degree (t − 1) such that δ_i(0) = 0:

δ_i(•) = Δ₁⁽ⁱ⁾x + • • • + Δ_m⁽ⁱ⁾x^t−1

Compute

{ϵ_im= Δ_m⁽ⁱ⁾• G}_{m∈[1...t−1]}

{u_ij= δ_i(j)}_j∈[1...t]

{e_ij= ENC_j(u_ij)}_j∈[1...t]

Broadcast

VSS_i^(τ)= custom character

i, τ, {ϵ_im}, {e_ij} custom character

SIG_i(VSS_i^(τ))

end for

First, each participant p_i∈ custom character , ||≥t generates a polynomial δ_i(·) where the free coefficient Δ₀⁽ⁱ⁾=0, and consequently δ_i(0)=0. Each participant then distributes shares of their polynomial δ_i(j) to the other players p_j,j≠i∈ to complete a verifiable sharing of 0. Thus, these shares can be used to blind another sharing without changing the secret being shared.

Upon receiving the sharing of 0, each participant will verify the shares and use them to blind their sub-shares for new participant p_new. Algorithm 41 describes how the sharing of 0 is verified, the local sub-share of p_new's share is constructed, and how it is blinded before being distributed to p_new.

Algorithm 8 Share-Construction

Goal: Enable new participant p_newto construct a new share r_new

for all Participants p_iϵ custom character

do

Recover share r_i^(τ)

r_i^(τ) ← PUF-Retrieve(c_i^(τ), helper_i^(τ))

Verify ∀j ≠ i

{DEC}_{i} ({ENC}_{i} (u_{ji})) \cdot G \overset{?}{=} \sum_{k = 1}^{t} i^{k} ϵ_{j k}

Construct sub-share r_newⁱfor p_new

r_{new}^{i} \leftarrow (r_{i}^{(t)} \cdot (\prod_{\underset{j \neq i}{j = 1}}^{t} \frac{new - j}{i - j})) \mod q

Blind sub-share with sharing of 0 from Algorithm 7: Share-Blinding

r_{new}^{i} \leftarrow r_{new}^{i} + \sum_{i = 1}^{t} (u_{ji} \cdot (\prod_{\underset{j \neq i}{j = 1}}^{t} \frac{- j}{i - j})) \mod q

p_new← ENC_pnew(r_newⁱ)

Update share

r_i^(τ+1)← PUF-Share-Update-Application(r_i^(τ))

Store r_i^(τ+1)and update PUF challenge:

{c_i^(τ+1), helpler_i^(τ+1)} ← PUF-Store(PUF_i, r_i^(τ+1))

end for

First, each of the t participants p_i∈ custom character

begins by recovering their share r_i^(τ)and verifying

for New Participant p_newdo

for all i ∈ custom character

do

r_newⁱ← DEC_p_new(ENC_p_new(r_newⁱ))

end for

r_new^(τ)= Σ_i=1^tr_newⁱmod q

r_new^(τ+1)← PUF-Share-Update-Application(r_new^(τ))

{c_new^(τ+1), helper_new^(τ+1)} ← PUF-Store(PU F_new, r_new^(τ+1))

end for

the sharing of 0 they received from Algorithm 7. The sub-share r_newⁱgenerated by participant p_iis then constructed by performing their portion of Lagrangian interpolation for f(new), where new is the ID of the new participant. This sub-share is subsequently blinded using the sharing of 0 to prevent the new participant p_newfrom recovering the share r_iof participant p_iby removing the Lagrangian interpolation term. After sending their sub-share to p_new, participant p_iupdates their share to the new time period (τ+1) and stores this value using a PUF. All of the received sub-shares are combined by the new participant p_newto form their share r_new^(τ), which is finally updated for time period (τ+1) and stored using a PUF.

In other embodiments, the players may perform the operations of Algorithm 41 in a different order. For example, first each of the t participants p_i∈ custom character recover their share r_i^(τ)and verify the sharing of 0 they received from Algorithm 7. Then p_iupdates their share to the new time period (τ+1), which is subsequently used to generate the replacement sub-share r_newⁱby performing their portion of Lagrangian interpolation for f(new), where new is the ID of the new participant. Participant p_istores their updated share r_i^(τ+1)using the PUF, and sends the sub-share r_new^(τ+1)to p_new. All of the received sub-shares are combined by the new participant p_newto form their share r_new^(τ+1), which is then stored using a PUF.

Algorithm 13 illustrates an example of a subset of component devices D ⊆ D,|D|=m≤n constructing a joint threshold proof for the verifier V. Although in this example the verifier combines partial proofs (thus, implying O(n) work for V as the number of partial proofs is 2n), a secretary could instead combine the partial shares and forward the result to the verifier. As another alternative, the components could form a ring, and pass their partial shares to the next component, which combines their own partial proof before forwarding on to the next component. First, we review the Enrollment Algorithm, Distributed Key Generation Algorithm, and PUF-Retrieve Algorithms.

Algorithms 9 and 10 below can be used to allow a PUF-enabled device to locally store and retrieve a sensitive value without storing any sensitive information in non-volatile memory. Algorithm 9 illustrates the storing of a sensitive value V_iusing a PUF, and Algorithm 10 illustrates the dynamic regeneration of V_i. The challenge c_iand helper data helper, can be public, as neither reveals anything about the sensitive value V_i. While the present example uses encryption of V_iby exclusive-or, ⊕, V_icould also be used as a key to other encryption algorithms (e.g., AES) to enable storage and retrieval of arbitrarily sized values.

Algorithm 9 PUF-Store

Goal: Store value V_i

for PUF Device d do

Select finite field custom character

_nof order n

Select E, an elliptic curve over custom character

_n

Find G ∈ E/ custom character

_n, a group generator

Select challenge c_i∈ custom character

_n

x = H(c_i, E, G, n)

O = PU F(x)

helper_i= P_i= O ⊕ ECC(V_i)

Write {c_i, helper_i} to non-volatile memory

end for

Algorithm 10 PUF-Retrieve

Goal: Retrieve value V_i

for PUF Device d do

Read {c_i, helper_i} from non-volatile memory

x ← H(c_i, E, G, n)

O′ = PU F(x)

V_i← D((ECC(V_i) ⊕ O) ⊕ O′)

end for

Whenever O and O′ are t-close, the error correcting code ECC can be passed to a decoding algorithm D which will recover the sensitive value V_i.

Using Algorithm 11, a local device can perform an enrollment protocol using the PUF. This allows each PUF circuit to generate a local public key p_i^pub, which is useful for bootstrapping more complex key setup algorithms (e.g., the distributed key generation protocol in Algorithm 12). When the key setup algorithm is performed internal to the device (rather than externally among a set of distinct devices), this bootstrap process may not be necessary.

Algorithm 11 Enrollment

for Device d do

c_i∈ custom character

_p, a group element

x = H(c_i, E, G, p, q)

O = PU F(x)

helper_i= O ⊕ ECC(p_i^privmod q)

p_i^pub= A_i= p_i^priv• G mod p

Store {p_i^pub, c_i, helper_i}

end for

In accordance with the invention, PUF-based cryptographic primitives are adapted to secret sharing to permit threshold cryptography founded on PUF or other root of trust. Using the example of an embodiment employing elliptic curve cryptography, distributed key generation is used to generate a number of shares (for example, two: r₁, r₂) of a master private key custom character ^priv=(r₁+r₂) mod q), which itself is never generated or constructed. (It is also possible to work directly with a message (e.g., as described by Ertaul) rather than a private key). The protocol is summarized in Algorithm 12: PUF-DKG, where an exemplary implementation would choose (t, n) as (2, 2).

Algorithm 12 PUF-DKG

Goal: Generate shares of master private key custom character

for 1 ≤ i ≤ n do

Select random polynomial f_i(·) = c₀⁽ⁱ⁾+ . . . + c_t−1ⁱx^t−1mod q

Compute f_i(j), ∀j ϵ [1, . . . , n]/i

Store coefficient commitments {c_k⁽ⁱ⁾· G mod p}_{kϵ[0, . . . , t-1]}

Store share commitments {f_i(j) · G mod p}_{jϵ[0, . . . , n]}

for 1 ≤ i ≤ n do

Verify

f_{j} (j) \cdot G \overset{?}{=} \sum_{k = 0}^{t - 1} j^{k} (c_{k}^{(j)} \cdot G) \mod p

Verify

c_{0}^{(j)} \cdot G \overset{?}{=} \sum_{i = 1}^{t} ((\prod_{\underset{j \neq i}{j = 1}}^{t} \frac{- j}{i - j}) f_{i} (j) \cdot G) \mod p

end for

Recover shares

r_{i} = \sum_{j = 1}^{n} ((\prod_{\underset{j \neq i}{j = 1}}^{t} \frac{- j}{i - j}) f_{j} (i)) \mod q

Recover Public key

𝒫^{pub} = r \cdot G = \sum_{j = 1}^{n} \sum_{i = 1}^{n} (((\prod_{\underset{j \neq i}{j = 1}}^{t} \frac{- j}{i - j}) f_{j} (i)) \cdot G) \mod p

end for

Algorithm 13 Interactive Threshold Proof Construction

Goal: Perform threshold zero knowledge proof at τ

One-Time Setup Stage

for each System Device d_iϵ custom character

do

Run Enrollment Algorithm

Run Distributed Key Generation Algorithm

end for

Evaluation Stage

for Verifier custom character

do

Broadcast ephemeral nonce N to all d₁ϵ custom character

end for

for all Participants p_iϵ custom character

do

for Share index custom character

ϵ {i, 2i} do

Choose a random custom character

_q

Compute and broadcast custom character

· G mod p to all d_iϵ custom character

end for

for Share index custom character

ϵ {i, 2i} do

Recover share custom character

← PUF-Retrieve-External(E(p_i^pub, k), E_k( custom character

))

Compute

B = 𝓎 \cdot G = \sum_{i = 1}^{2 t} B_{i} \mod p

e = Hash(G, B, custom character

^pub, N)

M_{ℓ} = 𝓎_{ℓ} + r_{ℓ} e (\prod_{\underset{j \neq i}{j = 1}}^{2 t} \frac{- j}{ℓ - j}) \mod q

Send (B_i, M_i, B_2i, M_2i) to verifier custom character

end for

end for

Similarly, Algorithm 13 can be performed non-interactively. This is accomplished by replacing the verifier's nonce N with a timestamp τ generated by the components, as illustrated in Algorithm 14. The timestamp serves as a replacement for the server's randomness N, and prevents replay attacks by adding a temporal requirement to the proof. That is, the timestamp is monotonically increasing, and the verifier simply checks that the timestamp used in the proof is reasonably (e.g., second granularity) current.

Algorithm 14 Non-Interactive Threshold Proof Construction

Goal: Perform threshold zero knowledge proof at τ

One-Time Setup Stage

for each System Device d_iϵ custom character

do

Run Enrollment Algorithm

Run Distributed Key Generation Algorithm

end for

Evaluation Stage

for all Participants p_iϵ custom character

do

fix current timestamp τ

for Share index custom character

ϵ {i, 2i} do

Choose a random custom character

_q

Compute and broadcast custom character

· G mod p to all d_iϵ custom character

end for

for Share index custom character

ϵ {i, 2i} do

Recover share custom character

← PUF-Retrieve-External(E(p_i^pub, k), E_k( custom character

))

Compute

B = 𝓎 \cdot G = \sum_{i = 1}^{2 t} B_{i} \mod p

e = Hash(G, B, custom character

^pub, τ)

M_{ℓ} = 𝓎_{ℓ} + r_{ℓ} e (\prod_{\underset{j \neq i}{j = 1}}^{2 t} \frac{- j}{ℓ - j}) \mod q

Send (B_i, M_i, B_2i, M_2i,τ) to verifier custom character

end for

end for

FIG. 4 begins at 402 with sequentially recovering shares of a local identify for a first device. In various embodiments, shares are received are described above. In one example, challenges are issues to a PUF circuit or other hardware identity circuit to recover a first share of a private key or secret. The challenges triggers a PUF response that is use with a helper value to map to shares of the local identity. The operations to recover the shares can be staggered so only one share of the local identity is memory at a time (e.g., a compute cycle, a few processor ticks, etc.). A threshold operation can be executed on the first share (e.g., at 404) and the results of the operations stored in memory to be combined with subsequent threshold operations so to prevent any share for being in memory longer than needed to compute the threshold operation. Algorithm 3 illustrates an example approach for using threshold operations.

Further challenges are issued to the PUF circuit or other hardware identity circuit (“HIC”) to recover a second share (e.g., at 402) and executed threshold operations (e.g., at 404). The output of the threshold operations is used to sequentially recover shares of a global identity, again the execution can be constrained to limit shares in memory to one global share. According to one embodiment, by limiting shares in memory, the best an adversary can accomplish is to capture one share of an identity and by capturing the one share prevent recovery of the second share owing to the properties of PUF or HIC circuits. In further embodiments, a global identity can be shared across any number of devices, and for example steps 402-404 can be executed for each device holding shares of the global identity. Various embodiments use 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and even hundreds of devices holding multiple shares of a global identity.

At 406 and 408 the steps for local and global identity recovery are executed on a second device to recover shares of the global identity held by the second device. In some embodiments, the execution can occur at a first device and then at a second device, however, no ordering is required between the first and second device. In further embodiments, recovery at the first and second device can proceed in parallel. Once enough shares of the global identity are recovered, at 410 any cryptographic operations can be performed. Again, rather than store shares of the global identity in memory, threshold operations can be executed on each global shares as it is recover and the outputs of the threshold operations used to enable the cryptographic operation (e.g., encrypt, decrypt, digitally sign, etc.) at 410.

Various embodiments can implement a global identity across a plurality of devices, where each device also has its own identity (e.g., public key and shared secret). Further embodiments can implement a global identity across a plurality of components that make up a singular system or a distributed system. In some examples, the components can use a common processor and/or memory. In other examples, each component can be a device with a processor, memory, and network interface for interacting with other components. The individual component can encode multiple shares of the global identity using respective local identities associated with the respective components.

It is to be appreciated that embodiments of the methods and apparatuses discussed herein are not limited in application to the details of construction and the arrangement of components set forth in the following description or illustrated in the accompanying drawings. The methods and apparatuses are capable of implementation in other embodiments and of being practiced or of being carried out in various ways. Examples of specific implementations are provided herein for illustrative purposes only and are not intended to be limiting. In particular, acts, elements and features discussed in connection with any one or more embodiments are not intended to be excluded from a similar role in any other embodiments.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. Any references to embodiments or elements or acts of the systems and methods herein referred to in the singular may also embrace embodiments including a plurality of these elements, and any references in plural to any embodiment or element or act herein may also embrace embodiments including only a single element. References in the singular or plural form are not intended to limit the presently disclosed systems or methods, their components, acts, or elements. The use herein of “including,” “comprising,” “having,” “containing,” “involving,” and variations thereof is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. References to “or” may be construed as inclusive so that any terms described using “or” may indicate any of a single, more than one, and all of the described terms.

Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.

Claims

1. An authentication system including a plurality of components for jointly executing cryptographic operations based on a shared encoded global identity, the system comprising: at least a first component and a second component having respective hardware intrinsic identity circuits for generating hardware specific outputs, wherein the hardware intrinsic identity circuits are constructed such that physical tampering changes properties of hardware and the hardware specific outputs; andat least one processor configured to: obtain a first plurality of shares associated with a first encoded local identity of the first component using a first hardware intrinsic identity circuit of the first component;recover at least a first and a second share of the encoded global identity based on combining outputs of threshold operations on the first plurality of shares;obtain a second plurality of shares associated with a second encoded local identity of the second component using a second hardware intrinsic identity circuit of the second component;recover at least a third and a fourth share of the encoded global identity based on combining outputs of threshold operations on the second plurality of shares; andenable execution of a cryptographic operation that employs the encoded global identity based on combining outputs of threshold operations on recovered shares of the encoded global identity, wherein the threshold operations obscure the recovered shares of the encoded global identity, and wherein compromise of a threshold number of local identity shares prevents recovery of the encoded global identity.
2. The system of claim 1, wherein the at least one processor is configured to map challenges and respective helper values to at least some of the first plurality of shares associated with the first encoded local identity of the first component.
3. The system of claim 1, wherein the at least one processor is configured to map challenges and respective helper values to at least some of the second plurality of shares associated with the second encoded local identity of the second component.
4. The system of claim 1, wherein only one share of an associated identity is in memory at a time.
5. The system of claim 1, wherein the first component includes a first processor, and a first communication interface.
6. The system of claim 5, wherein the second component includes a second processor, and a second communication interface.
7. The system of claim 1, wherein the at least one processor is configured to enroll at least the first component and the second component into the encoded global identity, and encode respective shares of the encoded global identity based on the first encoded local identity of the first component and the second encoded local identity of the second component.
8. The system of claim 7, wherein the at least one processor is configured to define, during enrollment, a threshold sharing of the encoded global identity between at least the first component and the second component that requires a minimum of two shares from a minimum of two devices to enable execution of cryptographic operations that employ the encoded global identity.
9. The system of claim 7, wherein the at least one processor is configured to: during enrollment, define a threshold sharing of the encoded global identity that requires a minimum of two shares from one component to enable cryptographic operations that employ the encoded global identity.
10. A computer implemented method for jointly executing cryptographic operations based on an encoded global identity, the method comprising: obtaining, by at least one processor, a first plurality of shares associated with a first encoded local identity of a first component using a first hardware intrinsic identity circuit of the first component, wherein tampering with the first hardware intrinsic identity circuit changes properties of hardware of the first hardware intrinsic identity circuit;recovering, by the at least one processor, at least a first share and a second share of the encoded global identity based on combining outputs of threshold operations on the first plurality of shares;obtaining, by the at least one processor, a second plurality of shares associated with a second encoded local identity of a second component using a second hardware intrinsic identity circuit of the second component, wherein tampering with the second hardware intrinsic identity circuit changes properties of hardware of the second hardware intrinsic identity circuit;recovering, by the at least one processor, at least a third share and a fourth share of the encoded global identity based on combining outputs of threshold operations on the second plurality of shares; andenabling execution of a cryptographic operation that employs the encoded global identity based on combining outputs of threshold operations on recovered shares of the encoded global identity, wherein the threshold operations obscure the recovered shares of the encoded global identity, and wherein compromise of a threshold number of local identity shares prevents recovery of the encoded global identity.
11. The method of claim 10, further comprising mapping, by the at least one processor, challenges and respective helper values to the first plurality of shares associated with the first encoded local identity of the first component.
12. The method of claim 10, further comprising mapping, by the at least one processor, challenges and respective helper values to the second plurality of shares associated with the second encoded local identity of the second component.
13. The method of claim 10, wherein only one share of an associated identity is in memory at a time.
14. The method of claim 10, wherein the first component includes the first hardware intrinsic identity circuit, a first processor, and a first communication interface, and an act of combining outputs of threshold operations on the first plurality of shares is executed on the first processor.
15. The method of claim 14, wherein the second component includes the second hardware intrinsic identity circuit, a second processor, and a second communication interface, and an act of combining, outputs of threshold operations on the second plurality of shares is executed on the second processor.
16. The method of claim 10, further comprising: enrolling, by the at least one processor, at least the first component and the second component into the encoded global identity; andencoding, by the at least one processor, respective shares of the encoded global identity based on the first encoded local identity of the first component and the second encoded local identity of the second component.
17. The method of claim 16, wherein the act of enrolling includes defining, by the at least one processor, a threshold sharing of the encoded global identity between at least the first component and the second component to require a minimum of two shares from a minimum of two devices to enable cryptographic operations that employ the encoded global identity.
18. The method of claim 17, wherein the act of enrolling includes defining, by the at least one processor, a threshold sharing of the encoded global identity to require a minimum of two shares from one component to enable cryptographic operations that employ the encoded global identity.
19. An authentication device including a plurality of components for jointly executing cryptographic operations based on an encoded global identity, the system comprising: a plurality of components having hardware intrinsic identity circuits configured to generate respective hardware specific outputs, wherein the hardware intrinsic identity circuits are constructed such that physical tampering changes properties of hardware and the hardware specific outputs; andat least one processor configured to: for each of respective ones of the plurality of components, obtain a respective plurality of shares associated with a respective encoded local identity of the respective component using a respective hardware intrinsic identity circuit of the respective component;recover a plurality of shares of the encoded global identity based on combining outputs of threshold operations on pluralities of shares obtained for the respective components; andenable execution of a cryptographic operation that employs the encoded global identity based on combining outputs of threshold operations on the plurality of shares of the encoded global identity, wherein the threshold operations obscure the plurality of shares of the encoded global identity, and wherein compromise of a threshold number of local identity shares prevents recovery of the encoded global identity.
20. The device of claim 19, wherein the at least one processor is configured to define a threshold sharing of the encoded global identity between the plurality of components that requires a minimum of two shares from a minimum of two devices to enable cryptographic operations that employ the encoded global identity.

US Referenced Citations (134)

Number	Name	Date	Kind
6501390	Chainer et al.	Dec 2002	B1
7564345	Devadas et al.	Jul 2009	B2
7581248	Atkins et al.	Aug 2009	B2
7653197	Van Dijk	Jan 2010	B2
7702927	Devadas et al.	Apr 2010	B2
7839278	Devadas et al.	Nov 2010	B2
7926089	Tulshibagwale et al.	Apr 2011	B2
7962516	Bahrs et al.	Jun 2011	B2
8032760	Tuyls et al.	Oct 2011	B2
8281127	Hayes	Oct 2012	B2
8290150	Erhart et al.	Oct 2012	B2
8346951	Hayes	Jan 2013	B2
8379856	Potkonjak	Feb 2013	B2
8386990	Trimberger et al.	Feb 2013	B1
8418006	Trimberger et al.	Apr 2013	B1
8446250	Kursawe et al.	May 2013	B2
8458489	Beckmann et al.	Jun 2013	B2
8463813	Siress et al.	Jun 2013	B2
8468186	Yu	Jun 2013	B2
8510608	Futa et al.	Aug 2013	B2
8516269	Hamlet et al.	Aug 2013	B1
8525169	Edelstein et al.	Sep 2013	B1
8566579	Armstrong et al.	Oct 2013	B2
8577091	Ivanov et al.	Nov 2013	B2
8625788	Pendakur et al.	Jan 2014	B2
8667265	Hamlet et al.	Mar 2014	B1
8752155	Lauper	Jun 2014	B2
8782396	Ziola et al.	Jul 2014	B2
8844009	Walsh et al.	Sep 2014	B2
8848477	Schrijen	Sep 2014	B2
8848905	Hamlet et al.	Sep 2014	B1
8868923	Hamlet et al.	Oct 2014	B1
8912817	Wang et al.	Dec 2014	B2
8918647	Wallrabenstein	Dec 2014	B1
8995660	Kobayashi et al.	Mar 2015	B2
9018972	Gurrieri et al.	Apr 2015	B1
9032476	Potkonjak	May 2015	B2
9038133	Chellappa et al.	May 2015	B2
9158906	Guajardo Merchan et al.	Oct 2015	B2
9225512	Trimberger	Dec 2015	B1
9292692	Wallrabenstein	Mar 2016	B2
9672342	Walsh et al.	Jun 2017	B2
9681302	Robinton et al.	Jun 2017	B2
9690927	Chellappa et al.	Jun 2017	B2
9705854	Khazan et al.	Jul 2017	B2
9715590	Gardner et al.	Jul 2017	B2
9806718	Wallrabenstein	Oct 2017	B2
9946858	Wallrabenstein	Apr 2018	B2
10013543	Walsh et al.	Jul 2018	B2
20030081785	Boneh et al.	May 2003	A1
20030088782	Forrest	May 2003	A1
20030204743	Devadas et al.	Oct 2003	A1
20050149496	Mukherjee et al.	Jul 2005	A1
20050222896	Rhyne et al.	Oct 2005	A1
20060023887	Agrawal et al.	Feb 2006	A1
20060045262	Orlando	Mar 2006	A1
20060210082	Devedas et al.	Sep 2006	A1
20070036353	Reznik et al.	Feb 2007	A1
20070044139	Tuyls et al.	Feb 2007	A1
20070206786	Chakraborty	Sep 2007	A1
20080069341	Relyea	Mar 2008	A1
20080133912	Yamamoto et al.	Jun 2008	A1
20080181398	Pappu	Jul 2008	A1
20080256549	Liu et al.	Oct 2008	A1
20080256600	Schrijen et al.	Oct 2008	A1
20090063860	Barnett et al.	Mar 2009	A1
20090083833	Ziola et al.	Mar 2009	A1
20100037056	Follis et al.	Feb 2010	A1
20100122093	Tuyls	May 2010	A1
20100127822	Devedas	May 2010	A1
20100176920	Kursawe et al.	Jul 2010	A1
20100272255	Devedas et al.	Oct 2010	A1
20100293384	Potkonjak	Nov 2010	A1
20100293612	Potkonjak	Nov 2010	A1
20110002461	Erhart et al.	Jan 2011	A1
20110033041	Yu et al.	Feb 2011	A1
20110099117	Schepers et al.	Apr 2011	A1
20110113392	Chakraborty et al.	May 2011	A1
20110138475	Gordon et al.	Jun 2011	A1
20110191837	Guajardo Merchan et al.	Aug 2011	A1
20110215829	Guajardo Merchan et al.	Sep 2011	A1
20110299678	Deas et al.	Dec 2011	A1
20120072717	Hayes	Mar 2012	A1
20120072737	Schrijen et al.	Mar 2012	A1
20120124385	Klasen et al.	May 2012	A1
20120131340	Teuwen et al.	May 2012	A1
20120137137	Brickell et al.	May 2012	A1
20120183135	Paral	Jul 2012	A1
20120233674	Gladstone et al.	Sep 2012	A1
20120321077	Shiota et al.	Dec 2012	A1
20130046990	Fahrny	Feb 2013	A1
20130051552	Handschuh et al.	Feb 2013	A1
20130094649	Tomlinson et al.	Apr 2013	A1
20130114810	Kobayashi et al.	May 2013	A1
20130138710	Yamamoto et al.	May 2013	A1
20130142329	Bell et al.	Jun 2013	A1
20130198838	Schmidt et al.	Aug 2013	A1
20130246809	Beckmann et al.	Sep 2013	A1
20130272521	Kipnis et al.	Oct 2013	A1
20140047565	Baek et al.	Feb 2014	A1
20140093074	Gotze et al.	Apr 2014	A1
20140108786	Kreft	Apr 2014	A1
20140140513	Brightley et al.	May 2014	A1
20140189890	Koeberl et al.	Jul 2014	A1
20140205089	Irwin	Jul 2014	A1
20140225639	Guo et al.	Aug 2014	A1
20140279532	Tremlet	Sep 2014	A1
20150058928	Guo et al.	Feb 2015	A1
20150071432	Zhu et al.	Mar 2015	A1
20150095655	Sherman	Apr 2015	A1
20150134966	Wallrabenstein	May 2015	A1
20150143130	Ducharme et al.	May 2015	A1
20150192637	Falk et al.	Jul 2015	A1
20150195088	Rostami et al.	Jul 2015	A1
20150234751	Van der Sluis et al.	Aug 2015	A1
20150242620	Newell et al.	Aug 2015	A1
20150278505	Lu et al.	Oct 2015	A1
20150317480	Gardner et al.	Nov 2015	A1
20150317481	Wallrabenstein	Nov 2015	A1
20150318994	Walsh et al.	Nov 2015	A1
20150341792	Wallrabenstein et al.	Nov 2015	A1
20160021096	Wallrabenstein	Jan 2016	A1
20160154981	Wesselhoff	Jun 2016	A1
20160170907	Walsh et al.	Jun 2016	A1
20160261409	French et al.	Sep 2016	A1
20160269186	Wallrabenstein	Sep 2016	A1
20160378983	Spurlock et al.	Dec 2016	A1
20170063559	Wallrabenstein et al.	Mar 2017	A1
20170132434	Wang et al.	May 2017	A1
20170149572	Wallrabenstein	May 2017	A1
20170270288	Walsh et al.	Sep 2017	A1
20180248706	Wallrabenstein	Aug 2018	A1
20180351753	Gardner et al.	Dec 2018	A1
20180351754	Wallrabenstein et al.	Dec 2018	A1

Foreign Referenced Citations (7)

Number	Date	Country
2320344	Nov 2006	EP
2 320 344	Jul 2011	EP
20090104421	Oct 2009	KR
WO 2010105993	Sep 2010	WO
WO 2014037812	Mar 2014	WO
WO 2015200196	Dec 2015	WO
WO 2016141386	Sep 2016	WO

Non-Patent Literature Citations (128)

Entry
Asaeda, “Structuring Proactive Secret Sharing in Mobile Ad-hoc Networks,” Jan. 18, 2006, International Symposium on Wireless Pervasive Computing.
Asaeda, “Structuring Proactive Secret Sharing in Mobile Ad-hoc Networks,” Jan. 18, 2006, International Symposium on Wireless Pervasive Computing, 6 pages.
Extended European Search Report dated Jan. 18, 2018 in connection with European Application No. 15811003.1.
Duren et al., Resilient Device Authentication System (RDAS) through Siometrics. Eighth Annual Cyber Security and Information Intelligence Workshop. ACM. 2012; pp. 1-4.
Eiroa, Hardware authentication based on PUFs and SHA-3 2nd round candidates. IEEE. 2009; pp. 1-4.
Shpantzer, Implementing Hardware Roots of Trust: The Trusted Platform Module Comes of Age. A SANS Whitepaper. Jun. 2013, pp. 1-17.
Zhao et al., Providing Root of Trust for ARM TrustZone using On-Chip SRAM. TrustED '14. ACM. Nov. 3, 2014; pp. 25-36.
International Search Report and Written Opinion dated Sep. 16, 2015 for Application No. PCT/US2015/036937.
International Preliminary Report on Patentability dated Jun. 16, 2016 for Application No. PCT/US2015/036937.
International Preliminary Report on Patentability dated Sep. 14, 2017 in connection with International Application No. PCT/US2016/021275.
Abercrombie et al., Secure Cryptographic Key Management System (CKMS) Considerations for Smart Grid Devices. CSIIRW '11 Proceedings of the Seventh Annual Workshop on Cyber Security and Information Intelligence Research, Oak Ridge, TN. Article No. 59. Oct. 12-14, 2011. 4 pages.
Goldwasser et al., One-time programs, Proceedings of the 28th Annual conference on Cryptology: Advances in Cryptology. Crypto 2008. 2008;39-56.
Guajardo et al., FPGA intrinsic PUFs and Their Use for IP Protection. Proceedings of the 9th Cryptographic Hardware and Embedded Systems Workshop (CHES). 2007;4727. 22 pages.
Guajardo et al., Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection. International Conference on Field Programmable Logic and Applications. 2007. 8 pages.
Horstmeyer et al., Physically secure and fully reconfigurable data storage using optical scattering. IEEE International Symposium on Hardware Oriented Security and Trust (HOST). 2015;157-62. 6 pages.
Kerr et al., PEAR: A Hardware Based Protocol Authentication System. Springl '10 Proceedings of the 3rd ACM 3IGSPATIAL International Workshop on Security and Privacy in GIS and LBS. 2010. 8 pages.
Kerr, Secure Physical System Design Leveraging Puf Technology. Purdue University. Thesis. May 2012. 87 pages.
Khandavilli, A Mobile Role Based Access Control System Using Identity Based Encryption With Non-Interactive 7ero Knowledge Proof of Authentication. Dalhousie University Repository, Faculty of Graduate Studies. Thesis. Apr. 5, 2012. 65 pages.
Kirkpatrick et al., Enforcing Physically Restricted Access Control for Remote Data. Proceedings of Codaspy. 2011. 10 pp.
Kirkpatrick et al., Physically Restricted Authentication and Encryption for Cyber-physical Systems. DHS Workshop on Future Directions in Cyber-physical Systems Security. 2009. 5 pages.
Kish et al., Physical Uncloneable Function Hardware Keys Utilizing Kirchhoff-Law Johnson-Noise Secure Key Exchange and Noise-Based Logic. Fluctuation Noise Lett. 2013;12. 9 pages.
Lao et al., Reconfigurable architectures for silicon physical unclonable functions. IEEE International Conference on Electro/Information Technology (EIT). 2011;1-7.
Maes et al., Intrinsic PUFs from flip-flops on reconfigurable devices. 3rd Benelux Workshop on Information and System Security (WISSec 2008). 2008. 17 pages.
Maiti et al., Physical Unclonable Function and True Random Number Generator: a Compact and Scalable implementation. GLSVLSI '09 Proceedings of the 19th ACM Great Lakes Symposium on VLSI. 2009. 4 pages.
Potkonjak et al., Differential Public Physically Unclonable Functions: Architecture and Applications. DAC '11 Proceedings of the 48th Design Automation Conference. 2011. 7 pages.
Rust, ed., D1.1: Report on use case and architecture requirements. Seventh Framework Programme. Holistic Approaches for Integrity of ICT-Systems. ICT-317930. Feb. 28, 2013. 50 pages.
Tuyls et al., Capacity and Examples of Template Protecting Biometric Authentication Systems. Biometric Authentication. 2004;3087:158-70. 13 pages.
Yu et al., Secure and robust error correction for physical unclonable functions. IEEE Des Test. Jan. 2010;27(1):48-65.
Zhang et al., Exploiting Process Variation and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions. IEEE Trans Info Forensics Sec. 2014;9(6):921-32.
International Search Report and Written Opinion dated Jun. 3, 2016 for Application No. PCT/US2016/021264.
International Search Report and Written Opinion dated Jun. 3, 2016 for Application No. PCT/US2016/021275.
[No Author Listed], D6.5: Publishable Summary. HINT. Seventh Framework Programme. Project 317930. Dec. 11, 2013.5 pages.
Abe et al., Adaptively Secure Feldman VSS and Applications to Universally-Composable Threshold Cryptography. Advances in Cryptology. Crypto 2004. 2004;3152:317-34.
Al Ibrahim et al., Cyber-Physical Security Using System-Level PUFs. 7th International IEEE Wireless Communications and Mobile Computing Conference (IWCMC). 2011. 5 pages.
Armknecht et al., A Formal Foundation for the Security Features of Physical Functions. Proceedings of the 2011 IEEE Symposium on Security and Privacy, SP '11. 2011;397-412.
Asaeda et al., Structuring Proactive Secret Sharing in Mobile Ad-hoc Networks. 2006 1st International Symposium on Wireless Pervasive Computing. Jan. 18, 2006. 6 pages.
Asim et al., Physical Unclonable Functions and Their Applications to Vehicle System Security. Vehicular Technology Conference, VTC Spring 2009. 10 pages.
Becker et al., Stealthy Dopant-Level Hardware Trojans. Crytographic Hardware and Embedded Systems, CHES 2013. 2013;8086:197-214. 18 pages.
Bilgin et al., A More Efficient AES Threshold Implementation. Cryptology ePrint Archive. Report 2013/967. 2013. 17 pages.
Blakley, Safeguarding cryptographic keys. Proceedingsof the 1979 AFIPS National Computer Conference. 1979;313-7.
Brzuska et al., Physically Uncloneable Functions in the Universal Composition Framework. Advances in Cryptology—Crypto 2011—31st Annual Cryptology Conference. 2011;6841:51-70.
Changgen et al., Threshold Signcryption Scheme Based on Elliptic Curve Cryptosystem and Verifiable Secret Sharing. International Conference on Wireless Communications, Networking and Mobile Computing. 2005;2:1136-9.
Chen et al., An efficient threshold group signature scheme. IEEE Region 10 Conference Tencon. 2004;2(B):13-6.
Coron, Resistance Against Differential Power Analysis for Elliptic Curve Cryptosystems. Crytpographic Hardware and Embedded Systems. 1999;1717:292-302.
Dodis et al., Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data. Eurocrypt 2004. 2004;3027:523-40.
Duc et al., A survey on RFID security and provably secure grouping-proof protocols. Int J Internet Tech Secured Trans. 2010;2(3/4):222-249.
Dwoskin et al., Hardware-rooted Trust for Secure Key Management and Transient Trust. Proceedings of the 14th ACM Conference: Computer & Communications Security. Nov. 2, 2007;389-400.
Eichhorn et al., Logically Reconfigurable PUFs: Memory-based Secure Key Storage. Proceedings of the Sixth ACM Workshop on Scalable Trusted Computing, STC '11. Oct. 17, 2011;59-64. 6 pages.
Ertaul et al., ECC Based Threshold Cryptography for Secure Data Forwarding and Secure Key Exchange in MANET (I). Networking 2005, Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communications Systems. 2005;3462:102-13.
Feiri et al., Efficient and Secure Storage of Private Keys for Pseudonymous Vehicular Communication. ACM CyCAR '13. Nov. 4, 2013;9-18.
Feldman, A Practical Scheme for Non-interactive Verifiable Secret Sharing. Proceedings of the 28th Annual Symposium on Foundations of Computer Science, SFCS '87. 1987;427-37.
Frankel et al., Optimal-Resilience Proactive Public-Key Cryptosystems. 38th Annual Symposium on Foundations of Computer Science. 1997;384-93. 12 pages.
Frikken et al., Robust Authentication using Physically Unclonable Functions. Information Security, ISC. 2009;5735:262-77.
Garcia-Alfaro et al., Security Threat Mitigation Trends in Low-cost RFID Systems. Data Privacy Management and Autonomous Spontaneous Security. 2010. 15 pages.
Gardner et al., Toward Trusted Embedded Systems. 2nd Annual NSA Trusted Computing Conference and Exposition. Orlando, FL. Sep. 20, 2011. 25 pages.
Gassend et al., Silicon Physical Random Functions. Proceedings of the 9th ACM Conference on Computer and Communications Security, CCS '02. 2002;148-60.
Gennaro et al., Secure Applications of Pedersen's Distributed Key Generation Protocol. Topics in Cryptology. CT-RSA 2003. 2003;2612:373-90.
Gennaro et al., Secure Distributed Key Generation for Discrete-Log Based Cryptosystems. Advances in Cryptology. Eurocrypt 99. Apr. 19, 1999;1592:295-310. 15 pages.
Handschuh et al., Hardware Intrinsic Security from Physically Unclonable Functions. Towards Hardware-Intrinsic Security, Information Security and Cryptography. 2010;39-53.
Herzberg et al., Proactive Public Key and Signature Systems. Proceedings of the 4th ACM Conference on Computer and Communications Security. CCS '97. 1997;100-10. 11 pages.
Herzberg et al., Proactive Secret Sharing or: How to Cope With Perpetual Leakage. Advances in Cryptology. Crypto 95. 1995;963:339-52.
Holcomb et al., Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags. Proceedings of the Conference on RFID Security. 2007. 12 pages.
Hori et al., Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. 2010 International Conference on Reconfigurable Computing and FPGAs (ReCon-Fiq). 2010;298-303. 6 pages.
Huang et al., To verify embedded system software integrity with TCM and FPGA. IEEE. Aug. 2010;65-70.
Hua-Qun et al., Verifiable (t, n) Threshold Signature Scheme based on Elliptic Curve. Wuhan Univ J Nat Sci. 2005;10(1):165-8.
Ibrahim et al., A Robust Threshold Elliptic Curve Digital Signature Providing a New Verifiable Secret Sharing Scheme. IEEE 46th Midwest Symposium on Circuits and Systems. 2003;1:276-80. 5 pages.
Jarecki et al., Adaptively Secure Threshold Cryptography: Introducing Concurrency, Removing Erasures (Extended Abstract). Advances in Cryptology. Eurocrypt 2000. 2000;1807:223-45.
Juels et al., A Fuzzy Commitment Scheme. Proceedings of the 6th ACM Conference on Computer and Communications Security, CCS '99. 1999;28-36. 9 pages.
Karakoyunlu et al., Differential template attacks on PUF enable cryptographic devices. IEEE International Workshop on Information Forensics and Security (WIFS). Dec. 12-15, 2010;1-6.
Katzenbeisser et al., PUFs: Myth, Fact or Busted? A Security Evaluation of Physically Unclonable Functions (PUFs) Cast in Silicon (Extended Version). Cryptographic Hardware and Embedded Systems—CHES '12. 2012;283-301. 18 pages.
Katzenbeisser et al., Recyclable PUFs: logically reconfigurable PUFs. J Cryto Eng. 2011;1(3):177-86. 15 pages.
Khoshroo, Design and Evaluation of FPGA-Based Hybrid Physically Unclonable Functions. Thesis. Graduate Program in Electrical and Computer Engineering. Western University. London, Ontario, Canada. May 2013. 107 pages.
Kim et al., Threshold Signature Schemes for ElGamal Variants. Comp Stan Interf. 2011;33(4):432-7.
Kirkpatrick et al., PUF ROKs: A Hardware Approach to Read-Once Keys. Proceedings of the 6th ACM Symposium on Information, Computer and Communications Security, ASIACCS '11. 2011;155-64.
Kirkpatrick et al., Software Techniques to Combat Drift in PUF-based Authentication Systems. Workshop on Secure Component and System Identification. 2010. 9 pages.
Kocher et al., Differential Power Analysis. Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology, Crypto '99. 1999;388:97. 10 pages.
Kocher et al., Introduction to Differential Power Analysis. J Cryptogr Eng. Mar. 3, 2011;1:5-27.
Krzywiecki et al., Coalition Resistant Anonymous Broadcast Encryption Scheme Based on PUF. TRUST 2011. 2011;6740:48-62.
Krzywiecki et al., Collusion Resistant Anonymous Broadcast Encryption Scheme Based on PUF. TRUST 2011. Jun. 22-24, 2011. 93 pages.
Kumar et al., Extended abstract: The Butterfly PUF Protecting IP on Every FPGA. IEEE International Workshop on Hardware-Oriented Security and Trust. 2008;67-70. 4 pages.
Kursawe et al., Reconfigurable Physical Unclonable Functions—Enabling Technology for Tamper-Resistant Storage. 2009 IEEE International Hardware-Oriented Security and Trust, HOST '09. 2009;22-9.
Langheinrich et al., Practical Minimalist Cryptography for RFID Privacy. IEEE Sys J. Dec. 2007;1(2). 19 pages.
Langheinrich et al., RFID Privacy Using Spatially Distributed Shared Secrets. International Symposium on Ubiquitous Computing Systems (UCS). 2007;1-16.
Lee et al., A technique to build a secret key in integrated circuits for identification and authentication applications. IEEE Symposium on VLSI Circuits: Digest of Technical Papers. 2004;176-9. 4 pages.
Libert et al., Adaptively Secure Non-Interactive Threshold Cryptosystems. Automata, Languages and Programming. 2011;588-600. 23 pages.
Maiti et al., The Impact of Aging on an FPGA-Based Physical Unclonable Function. International Conference on Field Programmable Logic and Applications (FPL). 2011;151-6.
Maiti, A Systematic Approach to Design an Efficient Physical Unclonable Function. Virginia Polytechnic Institute and State University. Dissertation. Apr. 30, 2012. 166 pages.
Majzoobi et al., Techniques for Design and Implementation of Secure Reconfigurable PUFs. ACM Trans Reconfig Tech Sys. Mar. 2009;2(1):5.1-33.
Merli et al., Semi-invasive EM Attack on FPGA RO PUFs and Countermeasures. Proceedings of the Workshop on Embedded Systems Security, WESS '11. 2011;2.1-9.
Merli et al., Side-Channel Analysis of PUFs and Fuzzy Extractors. Trust and Trustworthy Computing. 2011;6740:33-47.
Moradi et al., Pushing the Limits: A Very Compact and a Threshold Implementation of AES. Advances in Cryptology. Eurocrypt 2011. 2011;6632:69-88.
Nabeel et al., Authentication and key management for advanced metering infrastructures utilizing physically unclonable function. IEEE Third International Conference on Smart Grid Communications (SmartGridComm). 2012;324-9. 6 pages.
Nikova et al., Threshold Implementations Against Side-Channel Attacks and Glitches. Information and Communications Security. 2006;4307:529-45. 17 pages.
Owusu et al., OASIS: On Achieving a Sanctuary for Integrity and Secrecy on Untrusted Platforms. Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security. ACM. 2013;13-24. 12 pages.
Paral et al., Reliable and Efficient PUF-based Key Generation using Pattern Matching. IEEE International Symposium on Hardware-Oriented Security and Trust (HOST). 2011;128-33.
Pedersen, A Threshold Cryptosystem without a Trusted Party (Extended Abstract). Advances in Cryptology. Eurocrypt 91. 1991;547:522-6.
Pedersen, Non-Interactive and Information-Theoretic Secure Verifiable Secret Sharing. Advances in Cryptology, Crypto 91. 1992;576:129-40.
Peeters et al., Towards More Secure and Reliable Access Control. Perv Comp. 2011;11(3). 8 pages.
Peeters, Security Architecture for Things That Think. Department of Electrical Engineering. Arenberg Doctoral School of Science, Engineering and Technology. Dissertation. Jun. 2012. 150 pages.
Pfaffhauser, Protocols for MPC based on Unclonability. Department of Computer Science, ETH Zurich. Master Thesis. Apr. 12, 2011. 53 pages.
Ravikanth, Physical one-way functions. Massachusetts Institute of Technology. Dissertation. Mar. 2001. 154 pages.
Rigaud, ed., D3.1: Report on Protocol choice and implementation. HINT. Project 317930. Aug. 4, 2014. 35 pages.
Ruan et al., Elliptic curve EIGamal Threshold-based Key Management Scheme against Compromise of Distributed RSUs for VANETs. J Info Proc. 2012;20(4). 8 pages.
Rührmair et al., Applications of High-Capacity Crossbar Memories in Cryptography. IEEE Trans Nanotechnol. May 2011;10(3):489-98.
Rührmair et al., Modeling Attacks on Physical Unclonable Functions. Proceedings of the 17th ACM Conference on Computer and Communications Security, CCS '10. 2010;237-49.
Rührmair et al., Power and Timing Side Channels for PUFs and their Efficient Exploitation. IACR Cryptology ePrint Archive 2013;851. 14 pages.
Rührmair et al., PUFs in Security Protocols: Attack Models and Security Evaluations. 2013 IEEE Symposium on Security and Privacy. 2013;286-300.
Sadeghi et al., Short Paper: Lightweight Remote Attestation Using Physical Functions. ACM. Jun. 2011;109-14.
Sardar et al., Zero Knowledge Proof in Secret Sharing Scheme Using Elliptic Curve Cryptography. Global Trends in Computing and Communication Systems. 2012;269:220-6.
Schuster, Side-Channel Analysis of Physical Unclonable Functions (PUFs). Technische Universitat Munchen. Thesis. 2010. 57 pages.
Shamir, How to Share a Secret. Comm ACM. 1979;22(11):612-3.
Shao, Repairing Efficient Threshold Group Signature Scheme. Int J Netw Sec. Sep. 2008;7(2):218-22.
Suh et al., Aegis: A Single-Chip Secure Processor. IEEE Des Test Comp. 2007;570-80.
Suh et al., Physical Unclonable Functions for Device Authentication and Secret key Generation. Proceedings of the 44th annual Design Automation Conference, DAC '07. 2007;9-14.
Tang, ECDKG: A Distributed Key Generation Protocol Based on Elliptic Curve Discrete Logarithm. University of Southern California, Department of Computer Science. Technical Report 04-838. 2004. 20 pages.
Tuyls et al., Read-Proof Hardware from Protective Coatings. Proceedings of the 8th International Conference on Cryptographic Hardware and Embedded Systems. CHES '06. 2006;4249:369-83. 15 pages.
Van Dijk et al., Physical Unclonable Functions in Cryptographic Protocols: Security Proofs and Impossibility Results. Cryptolgoy ePrint Archive. Report 2012/228. Apr. 25, 2012. 36 pages.
Wu et al., On Foundation and Construction of Physical Unclonable Functions. IACR Cryptology ePrint Archive. 2010;171. 18 pages.
Yu et al., Lightweight and Secure PUF Key Storage Using Limits of Machine Learning. Proceedings of the 13th International Conference on Cryptographic Hardware and Embedded Systems, CHES '11. 2011;6917:358-73.
Yu et al., Recombination of Physical Unclonable Functions. GOMACTech. 2010. 4 pages.
Zheng et al., How to Construct Efficient Signcryption Schemes on Elliptic Curves. Inf Proc Lett. 1998;68(5):227-33.
Zheng, Digital Signcryption or How to Achieve Cost(Signature & Encryption) « Cost(Signature) + Cost(Encryption). Advances in Cryptology. Crypto '97. 1997;1294:165-79.
International Search Report and Written Opinion dated Sep. 20, 2018 in connection with International Application No. PCT/US2018/036014.
International Search Report and Written Opinion dated Sep. 20, 2018 in connection with International Application No. PCT/US2018/036023.
Extended European Search Report dated Sep. 6, 2018 in connection with European Application No. 18175600.8.
Chen, Reconfigurable physical unclonable function based on probabilistic switching of RRAM. Electron Lett. Apr. 12, 2015;51(8):615-7.
Wang et al., Verifiable (t, n)Threshold Signature Scheme based on Elliptic Curve. Wuhan Univ J Natural Sci. 2005;10(1):165-8.
Extended European Search Report dated Sep. 28, 2018 in connection with European Application No. EP 16759655.0.

Related Publications (1)

	Number	Date	Country
	20180351752 A1	Dec 2018	US

Device and system with global tamper resistance

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

Field of Search

CPC

International Classifications

Term Extension

Abstract

Description

Claims

US Referenced Citations (134)

Foreign Referenced Citations (7)

Non-Patent Literature Citations (128)

Related Publications (1)