Patent Application
20190050366
The present disclosure relates generally to serial communication and input/output pin configuration and, more particularly, to optimizing a register set configured for serial messaging and virtual general-purpose input/output state.
Mobile communication devices may include a variety of components including circuit boards, integrated circuit (IC) devices and/or System-on-Chip (SoC) devices. The components may include processing devices, user interface components, storage and other peripheral components that communicate through a shared data communication bus, which may include a serial bur or a parallel bus. General-purpose serial interfaces known in the industry, including the Inter-Integrated Circuit (I2C or I2C) serial bus and its derivatives and alternatives, including interfaces defined by the Mobile Industry Processor Interface (MIPI) Alliance, such as the I3C interface, the system power management interface (SPMI), and the Radio Frequency Front-End (RFFE) interface.
In one example, the I2C serial bus is a serial single-ended computer bus that was intended for use in connecting low-speed peripherals to a processor. Some interfaces provide multi-master buses in which two or more devices can serve as a bus master for different messages transmitted on the serial bus. In another example, the RFFE interface defines a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifier (PA), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices may be collocated in a single integrated circuit (IC) device, or provided in multiple IC devices. In a mobile communications device, multiple antennas and radio transceivers may support multiple concurrent RF links.
In many instances, a number of command and control signals are employed to connect different component devices in mobile communication devices. These connections consume precious general-purpose input/output (GPIO) pins within the mobile communication devices and it would be desirable to replace the physical interconnects with signals carried in information transmitted over existing serial data links.
As mobile communication devices continue to include a greater level of functionality, improved serial communication techniques are needed to support low-latency transmissions between peripherals and application processors.
Certain aspects of the disclosure relate to systems, apparatus, methods and techniques that can provide optimized low-latency communications between different devices such that GPIO signals may be carried as virtual signals. A virtual GPIO finite state machine (VGI FSM) operates on a register configuration that maintains GPIO state information from multiple sources and bus structures, and that enables the state information to be translated to device-specific register formats for transmission to one or more devices over a data communication bus.
In various aspects of the disclosure, a method performed at a device coupled to a serial bus includes determining that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register that has a first bit width and includes information identifying one or more devices associated with the event register, and exchanging the GPIO state information with the one or more devices over the serial bus. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The configuration information may include an address identifying the one or more devices. The configuration information may include addressing information identifying a target register in the one or more devices. The configuration information may include information identifying a mode of communication for transmitting the GPIO state information.
In certain aspects, the GPIO state information may be stored in a first device register, and the contents of the first device register may be transmitted over the serial bus. An address identifying the one or more devices may be stored in a second device register, and the content of the second device register may be transmitted with the first device register over the serial bus. An address identifying the target register may be stored in a third device register, and the content of the third device register may be transmitted with the first device register over the serial bus. The first device register may have a second bit width that is different from the first bit width.
In some aspects, the mode of communication defines whether certain transmissions over the serial bus are to be encrypted. In one example, the mode of communication defines whether the GPIO state information is encrypted when transmitted. In another example, the mode of communication defines whether messages transmitted over the serial bus are to be encrypted. The mode of communication may define whether the GPIO state information is retransmitted after an error is detected in a first transmission. The mode of communication may define whether the GPIO state information is transmitted in multiple transmission. The mode of communication may define a format of the addressing information identifying the target register in the one or more devices. The mode of communication may identify a priority of the GPIO state information.
In one aspect, exchanging the GPIO state information includes transmitting or receiving a data packet in accordance with an SPMI protocol. Exchanging the GPIO state information may include transmitting or receiving a data packet in accordance with an RFFE, protocol.
In various aspects of the disclosure, an apparatus has a set of event registers, each event register storing GPIO state information corresponding to a physical GPIO pin or signal and configuration information corresponding to the GPIO state information, a bus interface configured to communicate virtual GPIO information over a serial bus, and a finite state machine coupled to the set of event registers and the bus interface. The finite state machine may be configured to determine that GPIO state information corresponding to a physical GPIO pin or signal has changed in a first event register, and exchange the GPIO state information with the one or more devices over the serial bus. The configuration information may include an address identifying the one or more devices, addressing information identifying a target register in the one or more devices and information identifying a mode of communication for transmitting the GPIO state information. The first event register may have a first bit width and may include information identifying one or more devices associated with the event register. The GPIO state information is transmitted over the serial bus in accordance with the configuration information stored in the first event register.
In various aspects of the disclosure, an apparatus includes means for determining that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register, and means for exchanging the GPIO state information with the one or more devices over a serial bus. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The event register may have a first bit width and may include information identifying one or more devices associated with the event register. The configuration information may include an address identifying the one or more devices, addressing information identifying a target register in the one or more devices and information identifying a mode of communication for transmitting the GPIO state information.
In various aspects of the disclosure, a processor-readable storage medium stores instructions that, when executed by at least one processor or state machine of a processing circuit, cause the processing circuit or state machine to determine that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register, and exchange the GPIO state information with the one or more devices over a serial bus. The event register may have a first bit width and may include information identifying one or more devices associated with the event register. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The configuration information may include an address identifying the one or more devices, addressing information identifying a target register in the one or more devices and information identifying a mode of communication for transmitting the GPIO state information.
The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
Several aspects of the invention will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.
Devices that include multiple SoC and other IC devices often employ a shared communication interface that may include a serial bus or other data communication link to connect processors with modems and other peripherals. The serial bus or other data communication link may be operated in accordance with multiple standards or protocols defined. In various examples, a serial bus may be operated in accordance in with a I2C protocol, I3C protocol, SPMI protocol and/or RFFE protocol. According to certain aspects disclosed herein, GPIO pins and signals may be virtualized into GPIO state information that may be transmitted over a data communication link Virtualized GPIO state information that may be transmitted over a variety of communication links, including links that include wired and wireless communication links. For example, virtualized GPIO state information can be packetized or otherwise formatted for transmission over wireless networks including Bluetooth, WLAN, cellular networks, etc. Examples involving wired communication links are described herein to facilitate understanding of certain aspects. These aspects invariably apply to implementations in which transmission of GPIO state information includes transmission over wireless networks.
A number of different protocol schemes may be used for communicating messaging and data over communication links Existing protocols have well-defined and immutable structures in the sense that their structures cannot be changed. In some examples, a serial communication bus that is operated in accordance with I2C, I3C, SPMI, RFFE, or other standards or protocols may be used to tunnel different protocols with different register and data format requirements, different data transmission volumes and/or different transmission schedules.
Certain aspects disclosed herein provide methods, circuits and systems that are adapted to enable a device to provide a uniform register format for GPIO state information that supports multiple interfaces connecting the device and to one or more other devices. According to certain aspects disclosed herein, a register configuration may be defined that enables a state machine to manage virtual GPIO state information for a wide variety of physical GPIO configurations, bus architectures associated with the physical GPIO and protocols controlling the operation of a bus used to communicate virtual GPIO information. The register configuration can enable the state machine to operate autonomously. The state machine may be adapted to use the register configuration when target devices operate with different register widths. In one example, the state machine may be adapted to map 32-bit wide virtual GPIO registers to 8-bit registers and/or 16-bit registers in devices targeted to receive virtual GPIO information. Other mappings may be implemented according to preference or requirement of certain architectures. Bit definitions and bit position in the register may be altered based on architectural convenience. The register configuration enables an atomic approach to register definition, thereby ensuring maximum flexibility, and expandability.
Examples of Apparatus that Employ Serial Data Links
According to certain aspects, a serial data link may be used to interconnect electronic devices that are subcomponents of an apparatus such as a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a smart home device, intelligent lighting, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multicopter, or any other similar functioning device.
The ASIC 104 may have one or more processors 112, one or more modems 110, on-board memory 114, a bus interface circuit 116 and/or other logic circuits or functions. The processing circuit 102 may be controlled by an operating system that may provide an application programming interface (API) layer that enables the one or more processors 112 to execute software modules residing in the on-board memory 114 or other processor-readable storage 122 provided on the processing circuit 102. The software modules may include instructions and data stored in the on-board memory 114 or processor-readable storage 122. The ASIC 104 may access its on-board memory 114, the processor-readable storage 122, and/or storage external to the processing circuit 102. The on-board memory 114, the processor-readable storage 122 may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The processing circuit 102 may include, implement, or have access to a local database or other parameter storage that can maintain operational parameters and other information used to configure and operate the apparatus 100 and/or the processing circuit 102. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, soft or hard disk, or the like. The processing circuit 102 may also be operably coupled to external devices such as the antenna 124, a display 126, operator controls, such as switches or buttons 128, 130 and/or an integrated or external keypad 132, among other components. A user interface module may be configured to operate with the display 126, external keypad 132, etc. through a dedicated communication link or through one or more serial data interconnects.
The processing circuit 102 may provide one or more buses 118a, 118b, 120 that enable certain devices 104, 106, and/or 108 to communicate. In one example, the ASIC 104 may include a bus interface circuit 116 that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, the bus interface circuit 116 may be configured to operate in accordance with communication specifications or protocols. The processing circuit 102 may include or control a power management function that configures and manages the operation of the apparatus 100.
In one example, a master device 202 may include an interface controller 204 that may manage access to the serial bus, configure dynamic addresses for slave devices 2220-222N and/or generate a clock signal 228 to be transmitted on a clock line 218 of the serial bus 220. The master device 202 may include configuration registers 206 or other storage 224, and other control logic 212 configured to handle protocols and/or higher level functions. The control logic 212 may include a processing circuit such as a state machine, sequencer, signal processor or general-purpose processor. The master device 202 includes a transceiver 210 and line drivers/receivers 214a and 214b. The transceiver 210 may include receiver, transmitter and common circuits, where the common circuits may include timing, logic and storage circuits and/or devices. In one example, the transmitter encodes and transmits data based on timing in the clock signal 228 provided by a clock generation circuit 208. Other timing clocks 226 may be used by the control logic 212 and other functions, circuits or modules.
At least one device 2220-222N may be configured to operate as a slave device on the serial bus 220 and may include circuits and modules that support a display, an image sensor, and/or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. In one example, a slave device 2220 configured to operate as a slave device may provide a control function, module or circuit 232 that includes circuits and modules to support a display, an image sensor, and/or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. The slave device 2220 may include configuration registers 234 or other storage 236, control logic 242, a transceiver 240 and line drivers/receivers 244a and 244b. The control logic 242 may include a processing circuit such as a state machine, sequencer, signal processor or general-purpose processor. The transceiver 210 may include receiver, transmitter and common circuits, where the common circuits may include timing, logic and storage circuits and/or devices. In one example, the transmitter encodes and transmits data based on timing in a clock signal 248 provided by clock generation and/or recovery circuits 246. The clock signal 248 may be derived from a signal received from the clock line 218. Other timing clocks 238 may be used by the control logic 242 and other functions, circuits or modules.
The serial bus 220 may be operated in accordance with I2C, I3C, SPMI, RFFE, and/or other protocols. At least one device 202, 2220-222N may be configured to operate as a master device and a slave device on the serial bus 220. Two or more devices 202, 2220-222N may be configured to be operable as a master device on the serial bus 220.
In an example where the serial bus 220 is operated in accordance with an I3C protocol, devices that communicate using the I3C protocol can coexist on the same serial bus 220 with devices that communicate using I2C protocols. The I3C protocols may support different communication modes, including a single data rate (SDR) mode that is compatible with I2C protocols. High-data-rate (HDR) modes may provide a data transfer rate between 6 megabits per second (Mbps) and 16 Mbps, and some HDR modes may be provide higher data transfer rates. I2C protocols may conform to de facto I2C standards providing for data rates that may range between 100 kilobits per second (kbps) and 3.2 Mbps. I2C and I3C protocols may define electrical and timing aspects for signals transmitted on the serial bus 220, in addition to data formats and aspects of bus control. In some aspects, the I2C and I3C protocols may define direct current (DC) characteristics affecting certain signal levels associated with the serial bus 220, and/or alternating current (AC) characteristics affecting certain timing aspects of signals transmitted on the serial bus 220. In some examples, a 2-wire serial bus 220 transmits data on a data line 216 and a clock signal on the clock line 218. In some instances, data may be encoded in the signaling state, or transitions in signaling state of the data line 216 and the clock line 218.
In various examples, the device 302 may be implemented with a baseband processor 306, modem 304, RFIC 312, multiple communications links 310, 336, multiple RFFE buses 330, 332, 334 and/or other types of buses. The device 302 may include other processors, circuits, modules and may be configured for various operations and/or different functionalities. In the example illustrated in
Bus latency can affect the ability of a serial bus to handle high-priority, real-time and/or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may relate to sensor status, device-generated real-time events and virtualized general-purpose input/output (GPIO). In one example, bus latency may be measured as the time elapsed between a message becoming available for transmission and the delivery of the message or, in some instances, commencement of transmission of the message. Other measures of bus latency may be employed. Bus latency typically includes delays incurred while higher priority messages are transmitted, interrupt processing, the time required to terminate a datagram in process on the serial bus, the time to transmit commands causing bus turnaround between transmit mode and receive mode, bus arbitration and/or command transmissions specified by protocol.
In certain examples, latency-sensitive messages may include coexistence messages. Coexistence messages are transmitted in a multisystem platform to prevent or reduce instances of certain device types impinging on each other, including for example, switches 324, LNAs 326, 328, PAs 320 and other types of device that operate concurrently in a manner that can generate inter-device interference, or that could potentially cause damage to one or more devices. Devices that may interfere with one another may exchange coexistence management (CxM) messages to permit each device to signal imminent actions that may result in interference or conflict. CxM messages may be used to manage operation of shared components including a switch 324, LNA 326, 328, PA 320 and/or an antenna.
Multi-drop interfaces such as I3C, SPMI, RFFE, etc. can reduce the number of physical input/output (I/O) pins used to communicate between multiple devices. Protocols that support communication over a multi-drop serial bus define a datagram structure used to transmit command, control and data payloads. Datagram structures for different protocols define certain common features, including addressing used to select devices to receive or transmit data, clock generation and management, interrupt processing and device priorities. In this disclosure, the example of SPMI and RFFE protocols may be employed to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards. Some similarities exist between SPMI and RFFE datagram structures.
In the illustrated example, the system 400 includes three SoCs 402, 404, 406 and two power management integrated circuits (PMICs 408, 410). Other types of peripheral devices may be coupled to a serial bus 424, 426 operated in accordance with SPMI protocols. In the illustrated system 400, a first serial bus 424 couples a bus master 412, 414, 416 on each SoC 402, 404, 406 and a bus slave 418 on a first PMIC 408, with a second serial bus 426 couples a bus slave 420 in a second PMIC 410 to an additional bus master 422 provided in one SoC 402.
Mobile communication devices, and other devices that are related or connected to mobile communication devices, increasingly provide greater capabilities, performance and functionalities. In many instances, a mobile communication device incorporates multiple IC devices that are connected using a variety of communications links
GPIO provides generic pins/connections that may be customized for particular applications. For example, a GPIO pin may be programmable to function as an output, input pin or a bidirectional pin, in accordance with application needs. In one example, the Application Processor 502 may assign and/or configure a number of GPIO pins to conduct handshake signaling or inter-processor communication (IPC) with a peripheral device 504, 506, 508 such as a modem. When handshake signaling is used, sideband signaling may be symmetric, where signaling is transmitted and received by the Application Processor 502 and a peripheral device 504, 506, 508. With increased device complexity, the increased number of GPIO pins used for IPC communication may significantly increase manufacturing cost and limit GPIO availability for other system-level peripheral interfaces.
According to certain aspects of this disclosure, the state of GPIO, including GPIO associated with a communication link, may be captured, serialized and transmitted over a data communication link. In one example, captured GPIO may be transmitted in packets over a serial bus operated in accordance with an I2C, I3C, SPMI, RFFE and/or another protocol. In the example of a serial bus operated in accordance with I3C protocols, common command codes may be used to indicate packet payload and/or destination.
In another example, the communication link 722 may be a provided by a radio frequency transceiver that supports RF communication using, for example, a Bluetooth protocol, a WLAN protocol, a cellular wide area network, and/or another RF communication protocol. When the communication link 722 includes an RF connection, messages and virtual GPIO signals may be encoded in packets, frames, subframes, or other structures that can be transmitted over the communication link 722, and the receiving peripheral device 724 may extract, deserialize and otherwise process received signaling to obtain the messages and virtual GPIO state. Upon receipt of messages and/or virtual GPIO state, the VGI FSM 726 or another component of the receiving device may interrupt its host processor to indicate receipt of messages and/or any changes in physical GPIO signals.
In an example in which the communication link 722 is provided as a serial bus, messages and/or virtual GPIO state may be transmitted in packets configured for an I2C, I3C, SPMI, RFFE or another standardized serial interface. In the illustrated example, VGI techniques are employed to accommodate I/O bridging between an Application Processor 702 and a peripheral device 724. The Application Processor 702 may be implemented as an ASIC, SoC or some combination of devices. The Application Processor 702 includes a processor (central processing unit or CPU 704) that generates messages and GPIO associated with one or more communications channels 706. GPIO signals, events and/or other messages produced by the communications channels 706 may be monitored by respective monitoring circuits 712, 714 in a VGI FSM 726. In some examples, a GPIO monitoring circuit 712 may be adapted to produce virtual GPIO state representative of the state of physical GPIO signals and/or changes in the state of the physical GPIO signals. In some examples, other circuits are provided to produce the virtual GPIO state representative of the state of physical GPIO signals and/or changes in the state of the physical GPIO signals.
An estimation circuit 718 may be configured to estimate latency information for the GPIO signals and messages, and may select a protocol, and/or a mode of communication for the communication link 722 that optimizes the latency for encoding and transmitting the GPIO signals and messages. The estimation circuit 718 may maintain protocol and mode information 716 that characterizes certain aspects of the communication link 722 to be considered when selecting the protocol, and/or a mode of communication. The estimation circuit 718 may be further configured to select a packet type for encoding and transmitting the GPIO signals and messages as virtual GPIO state. The estimation circuit 718 may provide configuration information used by a packetizer 720 to encode the GPIO signals and messages as virtual GPIO state. In one example, the configuration information is provided as a command that may be encapsulated in a packet such that the type of packet and/or a type of payload data (e.g., VGI state) can be determined at a receiver. The configuration information may also be provided to physical layer circuits (PHY 708). The PHY 708 may use the configuration information to select a protocol and/or mode of communication for transmitting the associated packet. The PHY 708 may then generate the appropriate signaling to transmit the packet.
The peripheral device 724 may include a VGI FSM 726 that may be configured to process data packets received from the communication link 722. The VGI FSM 726 at the peripheral device 724 may extract messages and may map bit positions in virtual GPIO state onto physical GPIO pins in the peripheral device 724. In certain embodiments, the communication link 722 is bidirectional, and both the Application Processor 702 and a peripheral device 724 may operate as both transmitter and receiver.
The PHY 708 in the Application Processor 702 and a corresponding PHY 728 in the peripheral device 724 may be configured to establish and operate the communication link 722. The PHY 708 and 728 may be coupled to, or include an RF transceiver 108 (see
VGI tunneling, as disclosed herein, can be implemented using existing or available protocols configured for operating the communication link 722, and without the full complement of physical GPIO pins. VGI FSMs 710, 726 may handle GPIO signaling without intervention of a processor in the Application Processor 702 and/or in the peripheral device 724. The use of VGI can reduce pin count, power consumption, and latency associated with the communication link 722.
At the receiving device virtual GPIO state can be converted into physical GPIO signals. Certain characteristics of the physical GPIO pins may be configured using the virtual GPIO state or messages. For example, slew rate, polarity, drive strength, and other related parameters and attributes of the physical GPIO pins may be configured using the virtual GPIO state or messages. Configuration parameters used to configure the physical GPIO pins may be stored in configuration registers associated with corresponding GPIO pins. These configuration parameters can be addressed using a proprietary or conventional protocol such as I2C, I3C, SPMI or RFFE. In one example, configuration parameters may be maintained in addressable registers. Certain aspects disclosed herein relate to reducing latencies associated with the transmission of configuration parameters and corresponding addresses (e.g., addresses of registers used to store configuration parameters).
The VGI interface enables transmission of virtual GPIO state and other messages, whereby virtual GPIO state, messages, or both can be sent in the serial data stream over a communication link 722. In one example, a serial data stream may be transmitted in packets and/or as a sequence of transactions over a serial bus operated in accordance with an I2C, I3C, SPMI or RFFE protocol. The presence of virtual GPIO data in frame transmitted over the serial bus may be signaled using a special command code to identify the frame as a VGI frame. VGI frames may be transmitted as broadcast frames or addressed frames. In some implementations, a serial data stream may be transmitted in a form that resembles a universal asynchronous receiver/transmitter (UART) signaling protocol, in what may be referred to as VGI_UART mode of operation.
The application processor 802 may be coupled to each of the peripherals 8041-804N using multiple communication links 812, 814 and GPIO 816. For example, the application processor 802 may be coupled to the first peripheral 8041 using a high-speed bus 812, a low-speed bus 814 and input and/or output GPIO 816. In one example, the high-speed bus 812 may be operated as an Advanced High-performance Bus (AHB). As disclosed herein, GPIO signals may be virtualized and transferred over certain serial interfaces, including the SPMI 818, 820, and I2C or I3C interface, and/or an RFFE interface. The transfer of the GPIO signals is facilitated using command codes.
According to certain aspects disclosed herein, GPIO may be consolidated for multiple communication links and devices.
The system 900 may include an application processor 902 that can serve as a host device on various communication links, including the serial bus 910. One or more power management integrated circuits (PMICs 906, 908) may be included in the system 900. In the illustrated system 900, at least a first peripheral 9041 may include a modem.
Virtualizing GPIO can result in a reduced number of input/output pins, reduce IC package size, and reduces printed circuit board routing complexity. The serial bus 910 may be operated in accordance with SPMI protocols. In some examples, other protocols may be used for transferring VGI at high speed, and with low latency. In one example the RFFE bus may be employed for communicating VGI. As disclosed herein, GPIO signals may be virtualized and transferred over the serial bus 910. The transfer of the GPIO signals may be accomplished without modifying the protocols used on the serial bus 910. In some examples, GPIO consolidation may be implemented using a state machine to control virtualization of GPIO. In many examples, no modification of communication protocol is required. For example, additions, modifications and/or deletions of protocol-defined command and/or common command codes are not required to control virtual GPIO state transmission.
According to certain aspects, multiple GPIO ports can be virtualized such that the GPIO state information transmitted over the serial bus 910 may relate to consolidated state for multiple GPIO ports. In one example, multiple GPIOs may be supported for each port. The state machine may be configured to automatically identify when GPIO state information should be transmitted, and to which devices 902, 9041-904N, 914N virtualized GPIO state information should be addressed. In some examples, virtual GPIO state information related to one output GPIO may be transmitted and/or routed by the host application processor 902 (for example) to modify input GPIO of two or more of the peripherals 9041-904N.
In a complex smartphone or tablet system, the host application processor 902 may be coupled to multiple devices 9041-904N, 914N, and may use a serial bus 910 to signal virtual GPIO information, and thereby obtain a significant reduction in the number of physical I/O pins. The serial bus 910 may be used for the additional purpose of virtualizing a conventional serial bus (UART, I2C, etc.).
Conventional techniques for defining a virtual GPIO environment involve a non-coherent register set definition that includes significant individualized descriptors and device and message parameter association. Virtual GPIO configuration may vary considerably between implementations. The configuration of physical GPIO pins and signals typically varies between applications and the selection of bus used to communicate virtual GPIO information can restrict register and/or data transmission formats. In one example, certain communication protocols may not provide device and register addressing to adequately support virtual GPIO in multi-drop environments. In another example, certain communication protocols may not provide a mechanism to report errors detected during transmission of virtual GPIO information. In another example, certain communication protocols may lack the queuing capability that permits identification of quantities of data to be transmitted. The use of virtual GPIOs can necessitate various register level definitions required to facilitate communication of a complex set of virtual GPIO. These conventional techniques are not atomic in nature, in terms of the configuration, and are not easily scaled. Consequently, conventional implementations result in increased state machine and software architecture complexity.
Certain aspects disclosed herein provide optimized register definitions that may be used to accommodate complex virtual GPIO implementations. Certain aspects ensure atomicity while binding the devices involved along with the parameters required for event-related datagrams transmitted between one or more devices in a multi-drop serial bus. A multi-drop serial bus may be operated, for example, in accordance with SPMI or RFFE, protocols. Certain aspects provide optimized techniques for handling high-speed serial links 918, 920, 922, 924 including for example an AHB, such that 32-bit AHB bus-mapped register bits may be transposed, transformed or otherwise manipulated to enable representation in registers of another bus standard that provides registers addressable in 8-bit or 16-bit widths.
According to certain aspects, certain register bit configurations are defined that enable a VGI state machine to operate autonomously, with the ability to interface with registers of different widths. In some examples, the state machine may be adapted to map 32-bit wide AHB registers to 8-bit registers and/or 16-bit register. Other mappings may be implemented according to preference or requirement of certain architectures.
Bit definitions for the first byte 1002 may include:
In the event register 1000 illustrated in
Bit definitions for the third byte 1006 may include:
Priority values may be used to queue multiple events for transmission to a single target device.
Bit definitions for the fourth byte 1008 may include:
The configuration of the event register 1000 illustrated in
Other configurations of the event register 1000 may be used in some implementations. Different register configurations may include similar information is different formats. The information may include:
Some bit locations may be reserved for future expansion, and/or for application-specific information.
In one example, the 32-bit event registers 1112 may be configured for a transmit-event operation as follows:
At block 1206, the addressing mode associated with the event is determined. In one mode, direct register addressing is configured at block 1208. In a second mode, offset addressing is configured at block 1210. At block 1212, the security setting associated with the event is configured. For one setting, event-related information is transmitted by secured transmission at block 1214. Secured transmission may include encryption of the event information. For another setting, event-related information is transmitted in a standard, normal, unencrypted and/or otherwise unsecured transmission at block 1216.
At block 1218, the RONE setting is examined to determine if retransmission is indicated. Retransmission of the event-related information may be performed to enhance integrity of the virtual GPIO implementation. At block 1220, the ERR bit is checked to determine if a communication error occurred. The ERR bit may be set in response to receipt of a NACK, for example. In another example, the ERR bit may be set when an ACK is not received. If an error is indicated, retransmission may occur at block 1222 in accordance with the RONE parameter. If no error is indicated, the STAT bit may be cleared at block 1224, and the process may be terminated.
In some examples, the 32-bit event registers 1112 may be configured for a receive-event operation as follows:
In this example, the USID/GSID {Byte-3.[D3. . . . D0]}, ROE {Byte-1.[D6 . . . D5]}, PRIORITY {Byte-1.[D1 . . . D0]} and VAL {Byte-0.[D0]} are ignored.
At block 1306, the security setting associated with the event is determined. For one setting, event-related information is decoded at block 1308 when a secured transmission was used to transmit the event-related information. The event information may be decrypted at block 1308. For another setting, event-related information was transmitted in a standard, normal, unencrypted and/or otherwise unsecured transmission, and the event information may be received normally at block 1310.
At block 1312, it may be determined whether a communication error occurred. Communication errors may be detected through the use of parity checking, cyclic redundancy checking, differences between information received after multiple duplicate transmissions, and so on. If an error occurred, a NACK may be transmitted at block 1314. If no error occurred, additional transmissions of the evet information may be received at block 1316 in accordance with the RONE parameter.
A message flow for a master-originated message may proceed as follows:
A message flow for a slave-originated message may proceed as follows:
In the illustrated example, the processing circuit 1702 may be implemented with a bus architecture, represented generally by the bus 1710. The bus 1710 may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 1702 and the overall design constraints. The bus 1710 links together various circuits including the one or more processors 1704, and storage 1706. Storage 1706 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media.
In some examples, the storage 1706 includes registers used to communicate virtual GPIO information. One set of registers may be configured to maintain address, management and payload information corresponding to a physical GPIO and one or more devices to which virtual GPIO information is transmitted. Another set of registers may maintain information in a format corresponding to the one or more devices to which the virtual GPIO information is transmitted.
The bus 1710 may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface 1708 may provide an interface between the bus 1710 and one or more transceivers 1712a, 1712b. A transceiver 1712a, 1712b may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver 1712a, 1712b. Each transceiver 1712a, 1712b provides a means for communicating with various other apparatus over a transmission medium. In one example, a transceiver 1712a may be used to couple the apparatus 1700 to a multi-wire bus. In another example, a transceiver 1712b may be used to connect the apparatus 1700 to a radio access network. Depending upon the nature of the apparatus 1700, a user interface 1718 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus 1710 directly or through the bus interface 1708.
A processor 1704 may be responsible for managing the bus 1710 and for general processing that may include the execution of software stored in a computer-readable medium that may include the storage 1706. In this respect, the processing circuit 1702, including the processor 1704, may be used to implement any of the methods, functions and techniques disclosed herein. The storage 1706 may be used for storing data that is manipulated by the processor 1704 when executing software, and the software may be configured to implement any one of the methods disclosed herein.
One or more processors 1704 in the processing circuit 1702 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage 1706 or in an external computer-readable medium. The external computer-readable medium and/or storage 1706 may include a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a “flash drive,” a card, a stick, or a key drive), RAM, ROM, a programmable read-only memory (PROM), an erasable PROM (EPROM) including EEPROM, a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or storage 1706 may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Computer-readable medium and/or the storage 1706 may reside in the processing circuit 1702, in the processor 1704, external to the processing circuit 1702, or be distributed across multiple entities including the processing circuit 1702. The computer-readable medium and/or storage 1706 may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.
The storage 1706 may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 1716. Each of the software modules 1716 may include instructions and data that, when installed or loaded on the processing circuit 1702 and executed by the one or more processors 1704, contribute to a run-time image 1714 that controls the operation of the one or more processors 1704. When executed, certain instructions may cause the processing circuit 1702 to perform functions in accordance with certain methods, algorithms and processes described herein.
Some of the software modules 1716 may be loaded during initialization of the processing circuit 1702, and these software modules 1716 may configure the processing circuit 1702 to enable performance of the various functions disclosed herein. For example, some software modules 1716 may configure internal devices and/or logic circuits 1722 of the processor 1704, and may manage access to external devices such as the transceivers 1712a, 1712b, the bus interface 1708, the user interface 1718, timers, mathematical coprocessors, and so on. The software modules 1716 may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit 1702. The resources may include memory, processing time, access to the transceivers 1712a, 1712b, the user interface 1718, and so on.
One or more processors 1704 of the processing circuit 1702 may be multifunctional, whereby some of the software modules 1716 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 1704 may additionally be adapted to manage background tasks initiated in response to inputs from the user interface 1718, the transceivers 1712a, 1712b, and device drivers, for example. To support the performance of multiple functions, the one or more processors 1704 may be configured to provide a multitasking environment, whereby each of a plurality of functions is implemented as a set of tasks serviced by the one or more processors 1704 as needed or desired. In one example, the multitasking environment may be implemented using a timesharing program 1720 that passes control of a processor 1704 between different tasks, whereby each task returns control of the one or more processors 1704 to the timesharing program 1720 upon completion of any outstanding operations and/or in response to an input such as an interrupt. When a task has control of the one or more processors 1704, the processing circuit is effectively specialized for the purposes addressed by the function associated with the controlling task. The timesharing program 1720 may include an operating system, a main loop that transfers control on a round-robin basis, a function that allocates control of the one or more processors 1704 in accordance with a prioritization of the functions, and/or an interrupt driven main loop that responds to external events by providing control of the one or more processors 1704 to a handling function.
At block 1802, the finite state machine may determine that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register. The event register may have a first bit width. The event register may include information identifying one or more devices associated with the event register.
At block 1804, the finite state machine may exchange the GPIO state information with the one or more devices over a serial bus. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The configuration information may include an address identifying the one or more devices. The configuration information may include addressing information identifying a target register in the one or more devices. The configuration information may include information identifying a mode of communication for transmitting the GPIO state information.
In certain examples, the finite state machine may store the GPIO state information in a first device register, and transmit the first device register over the serial bus. The finite state machine may store an address identifying the one or more devices in a second device register, and transmit the second device register with the first device register over the serial bus. The finite state machine may store an address identifying the target register in a third device register, and transmit the third device register with the first device register over the serial bus. The first device register may have a second bit width that is different from the first bit width.
In one example, the mode of communication defines whether the GPIO state information is encrypted when transmitted. In another example, the mode of communication defines whether messages are encrypted when transmitted over the serial bus. In another example, the mode of communication defines whether the GPIO state information is retransmitted after an error is detected in a first transmission. In another example, the mode of communication defines whether the GPIO state information is transmitted in multiple transmission. In another example, the mode of communication defines a format of the addressing information identifying the target register in the one or more devices. In another example, the mode of communication identifies a priority of the GPIO state information.
In one example, the finite state machine may exchange the GPIO state information by transmitting or receiving a data packet in accordance with a SPMI protocol. In another example, the finite state machine may exchange the GPIO state information by transmitting or receiving a data packet in accordance with an RFFE protocol.
The processor 1916 is responsible for general processing, including the execution of software, code and/or instructions stored on the processor-readable storage medium 1918. The processor-readable storage medium may include a non-transitory storage medium. The software, when executed by the processor 1916, causes the processing circuit 1902 to perform the various functions described supra for any particular apparatus. The processor-readable storage medium may be used for storing data that is manipulated by the processor 1916 when executing software. The processing circuit 1902 further includes at least one of the modules 1904, 1906 and 1908. The modules 1904, 1906 and 1908 may be software modules running in the processor 1916, resident/stored in the processor-readable storage medium 1918, one or more hardware modules coupled to the processor 1916, or some combination thereof. The modules 1904, 1906 and 1908 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.
In one configuration, the apparatus 1900 includes modules and/or circuits 1908 configured to decode information maintained in a GPIO event register, modules and/or circuits 1906 configured to translate the information maintained in the GPIO event register to populate one or more device registers, and modules and/or circuits 1904 configured to transmit a packet comprising the GPIO word.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”
This application claims priority to and the benefit of U.S. Provisional Patent Application Ser. No. 62/545,422 filed in the U.S. Patent Office on Aug. 14, 2017, the entire content of this application being incorporated herein by reference as if fully set forth below in its entirety and for all applicable purposes.
| Number | Date | Country | |
|---|---|---|---|
| 62545422 | Aug 2017 | US |
