DEVICE FOR COMPARING THE PEAK VALUE OF AT LEAST ONE VOLTAGE SIGNAL WITH A REFERENCE VOLTAGE

Abstract

A device for comparing the peak value of a periodic voltage signal or a linear combination of periodic voltage signals with a reference voltage includes a reference transconductor element for converting the reference voltage into a reference current, respective transconductor elements for converting each of the periodic voltage signals into respective periodic current signals, a current-comparison node for comparing the respective periodic current signals with the reference current, generating a comparison current as a difference between the sum of the aforesaid periodic current signals and the reference current, a current rectifier supplied with the comparison current, a hold capacitor charged with the output current of the current rectifier, and a discharge-current generator in parallel to the hold capacitor. The voltage across the capacitor indicates of the outcome of the comparison between the peak value of the periodic voltage signal or the linear combination of periodic voltage signals and the reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described, by way of non-limiting example, with reference to the figures of the annexed drawings, in which:

FIG. 1, FIG. 2, and FIGS. 3A, 3B and 3C, corresponding to the known art, have already been described previously;

FIG. 4 is a block diagram representing the functions of peak detection and comparison according to the invention;

FIG. 5 shows a circuit embodiment of the system FIG. 4; and

FIGS. 6, 7, 8 and 9 show some possible variants of the circuit embodiment of FIG. 5.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 4 is a schematic illustration of a block diagram of the functions of peak detection and comparison according to the invention for implementing Eq. 1 given above.

In the solution described herein, the signal processing occurs in current rather than in voltage.

For this purpose, the periodic voltage signals v₁(t), v₂(t), . . . , v_N(t) to be processed and the reference voltage V_REF are converted into as many respective currents i₁(t), i₂(t), . . . , i_N(t) via appropriate transconductor elements G_m1, G_m2, . . . , G_mN. Likewise, the reference voltage V_REF is converted into a corresponding reference current I_REF via a further transconductor element G_m0. Thus we have:

$\begin{array}{cc}\begin{array}{c}{i}_1\left(t\right)=G_{m1}v_1\left(t\right)\\ i_2\left(t\right)=G_{m2}v_2\left(t\right)\\ \cdots \\ i_N\left(t\right)=G_{\mathrm{mN}}v_N\left(t\right)\\ I_{\mathrm{REF}}=G_{m0}V_{\mathrm{REF}}\end{array}& \left(2\right)\end{array}$

All the currents in question converge towards a single current-comparison node 100 where the comparison effectively takes place.

The current I_REF is generated in such a way that its contribution to the node present with negative sign, and hence, on the direct branch downstream, a comparison current i_I(t) is obtained, given by:

$\begin{array}{cc}{i}_I\left(t\right)=\sum _{k=1}^Ni_k\left(t\right)-I_{\mathrm{REF}}& \left(3\right)\\ i.e.,& \\ i_I\left(t\right)=G_{m0}\left(\sum _{k=1}^N\frac{G_{\mathrm{mk}}}{G_{m0}}v_k\left(t\right)-V_{\mathrm{REF}}\right)& \left(4\right)\end{array}$

Said comparison current is sent to a current rectifier 110, the function of which is to reproduce at output only the positive portion of the input current waveform.

Consequently, the output current i_O(t) at output from the current rectifier can be expressed symbolically as

i _o(t)=pos{i_I(t)}  (5)

where the function pos{·} is defined as follows:

$\begin{array}{cc}\mathrm{pos}\left\{x\right\}=\{\begin{array}{cc}x& \mathrm{per}x\ge 0\\ 0& \mathrm{per}x<0\end{array}& \left(6\right)\end{array}$

As long as the input current i_I(t) is maintained always negative, the output current i_O(t) is zero and the output voltage v_O(t) on the hold capacitor C_O remains low as a result of the discharge-current generator I_DIS.

Instead, if the input current presents positive during part of the period or for the entire duration thereof, also the output current is accordingly positive and tends to charge the capacitor C_O, increasing the output voltage v_O(t).

Assuming that the capacitor C_O is of a value that is sufficiently high as to enable the ripple of the output voltage to be neglected, just the d.c. component V_O of the voltage v_O(t) can be considered.

Said d.c. component V_O can be calculated by performing the balancing of the currents at the output node and evaluating the average thereof over a period. By so doing, the following expression is obtained:

$\begin{array}{cc}\begin{array}{c}{V}_O=R_O\stackrel{\_}{\left(i_O\left(t\right)-I_{\mathrm{DIS}}\right)}\\ =R_O\stackrel{\_}{\mathrm{pos}\{i_I\left(t\right)}-R_OI_{\mathrm{DIS}}\end{array}& \left(7\right)\end{array}$

where R_O is the total impedance at the output node (resulting from the parallel between the output impedance of the current rectifier and the impedance that in the real circuit is inevitably associated to the generator I_DIS), and the sign · designates the time average of the argument periodic function.

When approximating Eq. 7, the quantity pos{i_I(t)} is proportional to max{i_I(t)} for values of max{i_I(t)} positive and small. Hence, if Δ indicates the constant of proportionality, from Eq. 7 we can derive:

$\begin{array}{cc}\begin{array}{c}{V}_O=\Delta R_O\max \left\{i_I\left(t\right)\right\}-R_OI_{\mathrm{DIS}}\\ =\Delta R_O\max \left\{G_{m0}\left[\sum _{k=1}^N\frac{G_{\mathrm{mk}}}{G_{m0}}v_k\left(t\right)-V_{\mathrm{REF}}\right]\right\}-R_OI_{\mathrm{DIS}}\\ =\Delta G_{m0}R_O\left[\max \left\{\sum _{k=1}^N\frac{G_{\mathrm{mk}}}{G_{m0}}v_k\left(t\right)\right\}-V_{\mathrm{REF}}\right]-R_OI_{\mathrm{DIS}}\end{array}& \left(8\right)\end{array}$

Furthermore, assuming that the discharge current I_DIS will determine in steady-state conditions a negligible contribution on V_O, Eq. 8 can be approximated as follows:

$\begin{array}{cc}{V}_O=\Delta G_{m0}R_O\left[\max \left\{\sum _{k=1}^N\frac{G_{\mathrm{mk}}}{G_{m0}}v_k\left(t\right)\right\}-V_{\mathrm{REF}}\right]& \left(9\right)\end{array}$

which is formally equivalent to Eq. 1 that was to be implemented.

Eq. 9 confirms that a current comparison followed by a current rectifier closed, with high impedance, on a capacitor is equivalent to a voltage peak detector followed by a voltage comparison. In particular, it is to be noted that the diagram proposed in FIG. 4 reverses the order with which the operations of peak detection and comparison are carried out as compared to the solution of FIG. 2 corresponding to the known art.

From Eq. 9 it may incidentally be noted that the need for a high comparison gain results, in a circuit embodiment, in the need for a high impedance at the output node in FIG. 4.

As regards the discharge-current generator I_DIS, it is to be noted that, in spite of the error term R_OI_DIS caused thereby in Eq. 8, its presence proves indispensable to prevent the discharge times of C_O from becoming too long with respect to the requirements of the application in question.

A possible circuit embodiment of FIG. 4 is shown in FIG. 5. In this embodiment, the current-comparison node 100 and the current rectifier 110 of FIG. 4 are obtained via a differential-amplifier stage to the inputs of which the voltage signal and the reference voltage are fed back, via the resistances R₁ and R₂, respectively. The reference voltage V_REF is supplied to the inverting input of the differential stage.

In the detail, the amplifier stage comprises four bipolar transistors (BJTs) T₁, T₂, T₃, and T₄.

Of these, the transistors T₁ and T₃, both with their base (i.e., their control terminal, represented by the gate in the case of a FET implementation) short-circuited on their collector (i.e., their current-inflow terminal or current-collection terminal, represented by the drain in the case of a FET implementation), are cascaded (i.e., set in series) between the supply voltage V_CC and ground so as to have their respective collector-emitter paths traversed by one and the same current I₁. The voltage V_I undergoing comparison is supplied via a resistor R₁ at the point of connection between the collector of the “bottom” transistor T₁ and the emitter of the “top” transistor T₃.

The transistors T₂ and T₄, the bases of which are not short-circuited on the collectors, are also cascaded (i.e., set in series) between the supply voltage V_CC and ground so as to have their respective collector-emitter paths traversed by one and the same current I₂. The reference voltage V_REF is supplied via a resistor R₂ at the point of connection between the collector of the “bottom” transistor T₂ and the emitter of the “top” transistor T₄, coming under which is the hold capacitor C₀, across which the output voltage V₀ is taken. The hold capacitor C₀ is thus driven via the second pair of transistors T₂, T₄.

The embodiment of FIG. 5 relates to the simple case in which only one input voltage v_I(t), in addition to the reference voltage V_REF, is processed.

Operation of said circuit can be explained by analogy with the schematic circuit diagram described previously: the capacitor C_O and the current generator I₂ in FIG. 5 play a role similar to that of C_O and I_DIS, respectively, in FIG. 4.

The current rectifier 110 of FIG. 4 is implemented, in the circuit form, via the transistor T₄ in FIG. 5, exploiting the fact that its collector current can flow only in the descending direction.

The current-comparison node 100 in FIG. 4 corresponds to the emitter node of the transistor T₄ in FIG. 5.

Finally, the voltage-to-current conversion provided by the scheme in FIG. 4 is obtained via the two resistors R₁, R₂ and the mirror formed by the transistors T₁-T₂ in FIG. 5. In particular, the mirror T₁-T₂ causes the current contribution deriving from v_I(t) to reach the current-comparison node 100 with opposite sign with respect to the current contribution deriving from V_REF.

For an understanding of the function of the transistor T₃ and of the generator I₁ in FIG. 5, the following is to be considered: when T₄ is on, the balancing of the currents at the output node (neglecting for simplicity the base currents) yields

$\begin{array}{cc}{i}_{\mathrm{Co}}\left(t\right)=\frac{V_{\mathrm{REF}}-v_{C2}\left(t\right)}{R_2}+I_2-\frac{A_{E2}}{A_{E1}}\left(\frac{v_I\left(t\right)-v_{C1}\left(t\right)}{R_1}+I_1\right)& \left(10\right)\end{array}$

where i_Co(t) is the current that flows through the capacitor C_O, whilst v_C1(t) and v_C2(t) are the voltages at the collectors of the transistors T₁ and T₂, respectively. If the following condition is satisfied:

$\begin{array}{cc}\frac{A_{E2}}{A_{E1}}=\frac{R_1}{R_2}=\frac{I_2}{I_1}& \left(11\right)\end{array}$

where A_E1 and A_E2 are the emitter areas of the transistors T₁ and T₂, then

$\begin{array}{cc}{i}_{\mathrm{Co}}\left(t\right)=-\frac{v_I\left(t\right)-V_{\mathrm{REF}}+v_{C2}\left(t\right)-v_{C1}\left(t\right)}{R_2}& \left(12\right)\end{array}$

Thanks to the presence of the transistor T₃, the voltages v_C1(t) and v_C2(t) are approximately the same as one another and cancel out (since v_C1−v_C2=v_BE4−v_BE3 and v_BB4≅v_BE3), to obtain

$\begin{array}{cc}{i}_{\mathrm{Co}}\left(t\right)=-\frac{v_I\left(t\right)-V_{\mathrm{REF}}}{R_2}& \left(13\right)\end{array}$

Hence, it may be stated that the use of the transistor T₃ (and of the generator I₁ necessary for biasing it) is functional for eliminating the offset terms that arise in the voltage-to-current conversion performed by the resistances R₁ and R₂.

We note incidentally that, on account of the natural direction of the current rectifier T₄ and of the generator I₂, the response of the circuit in FIG. 5 has a sign opposite to that of the scheme in FIG. 4; i.e., v_O(t) remains at a high value as long as v_I(t) is always lower than V_REF and drops to a low value when the peak of v_I(t) exceeds V_REF. This is confirmed by the negative sign in the second member of Eq. 13.

FIG. 6 shows an improved version of the circuit of FIG. 5. It may be noted that the simple mirror T₁-T₂ in FIG. 5 has been replaced with a Wilson mirror comprising the transistors T₁, T₂ and T_2X. This modification improves the accuracy in the transfer of the signal from the input v_I(t) to the current-comparison node 100 since it reduces the systematic error associated to the current gain of the mirror. It will be appreciated moreover that, whereas in the embodiment of FIG. 5 (and of FIG. 7, which will be described hereinafter), the transistors of the first pair T₁, T₃ both have their control terminal (base) short-circuited with the current-inflow terminal (collector), in the embodiment of FIG. 6, said short-circuit arrangement between the control terminal and the current-inflow terminal is adopted for the “top” transistor T₃ of the first pair T₁, T₃, referenced to the supply voltage V_CC, and the “bottom” transistor T₂ of the second pair T₂, T₄, referenced to ground, associated to which is the further transistor T_2X of the Wilson mirror.

In an implementation with MOSFETs, a similar improvement can be obtained by replacing the simple mirror T₁-T₂ in FIG. 5 with a cascode mirror.

FIG. 7 shows another improved version of the circuit of FIG. 5. In this case, the output has been cascoded by adding a further transistor T_4X in common-base configuration downstream of the current rectifier T₄.

This modification achieves the effect of increasing significantly the output impedance of the rectifier and therewith the comparison gain of the circuit (see Eq. 9).

It should be noted that the improvements that can be obtained via the versions illustrated in FIGS. 6 and 7 present a cost. In both cases, in fact, the capacity of the circuit to work with low supply voltages is reduced.

FIG. 8 shows a more general version of the circuit able to process multiple input periodic voltage signals by performing a linear combination thereof. The inputs v_P1(t), v_P2(t) . . . v_PN(t) contribute with a positive sign to the linear combination, whilst the inputs v_N1(t), V_N2(t), . . . , v_NM(t) contribute with a negative sign.

In fact, the function implemented by the circuit in FIG. 8 can be symbolically expressed as follows:

$\begin{array}{cc}{V}_O=\Delta \frac{R_O}{R_{\mathrm{REF}}}\left[\max \left\{\sum _{k=1}^N\frac{R_{\mathrm{REF}}}{R_{P_k}}v_{P_k}\left(t\right)-\sum _{k=1}^M\frac{R_{\mathrm{REF}}}{R_{N_k}}v_{N_k}\left(t\right)\right\}-V_{\mathrm{REF}}\right]& \left(14\right)\end{array}$

which is true, provided that the following rule is respected:

$\begin{array}{cc}\frac{R_{P_0}//R_{P_1}//R_{P_2}//\dots //R_{P_N}}{R_{\mathrm{REF}}//R_{N_0}//R_{N_1}//R_{N_2}//\dots //R_{N_M}}=\frac{A_{E2}}{A_{E1}}& \left(15\right)\end{array}$

The reason why the condition of Eq. 15 must be satisfied can be reduced to what has already been noted with reference Eq. 12 as regards the possibility that the offset terms (v_C1(t) and v_C2(t)) cancel out. In fact, if we write the balancing of the currents at the current-comparison node 100, we realize that said simplification occurs only if Eq. 15 is satisfied.

FIG. 9 shows a last circuit variant characterized by the addition of the pnp common-emitter stage T₅ downstream of the circuit previously described. The advantage obtained with this modification (in addition to the obvious increase in the gain) lies in the fact that it enables compensation of the loop of which the circuit in FIG. 9 forms part, without introducing any further low-frequency poles.

In fact, via the capacitor C_M, it is possible to carry out a compensation by the Miller effect. As is known, the pole splitting associated to said compensation displaces the high-frequency pole at the output node, and hence the single low-frequency node that survives is the one at the collector of T₄. As has already been noted, limiting the number of low-frequency poles of the loop gain proves advantageous in terms of closed-loop bandwidth and/or phase margin.

All the circuit schemes described can function also by replacing the current generators I₁ and I₂ with as many resistors, thus obtaining even simpler topologies, even though characterized by a smaller comparison gain.

With reference to what has been described up to now, we can state that the method and the circuits proposed present various advantages as compared to the known art.

In the first place, the devices proposed enable implementation of Eq. 1 with a number of poles that is lower as compared to the known art. In fact, if the classic solution shown in FIG. 2 presents a number of significant poles equal to two (one on the peak detector and the other on the comparator for loop compensation), the solution described herein enables reduction in the number of said poles to one because the peak-hold node and the node in which the compensation is performed coincide (see FIG. 9). Reducing in the number of poles of the loop gain enables a wider closed-loop bandwidth to be obtained given the same phase margin or else, alternatively, an improved phase margin given the same bandwidth.

Observation of the circuit diagrams provided confirms, then, that the solution described herein is characterized by an extreme topological simplicity. In an integrated embodiment, the topological simplicity conveniently results in a reduced area occupation.

In addition, in the circuit diagrams proposed, the input voltage-to-current conversion is implemented via resistors. This approach enables input voltages to be handled that are even higher than the supply level (Vcc) or lower than the ground reference. Consequently, the circuits proposed are characterized by an excellent input voltage dynamics.

Finally, it is worthwhile noting that the solution described enables an improved accuracy in peak detection as compared to the classic open-loop solutions (see FIGS. 3A and 3B) in so far as it is not affected by the error due to the voltage drop on the rectifier device.

It should noted that, although the present invention has been described with reference to circuit diagrams using BJTs, it must be understood as being independent of the reference technology, it being possible for the aforesaid circuits to be implemented either by bipolar transistors or by field-effect transistors.

In addition, the present invention is not limited to the circuit implementations shown. Different topological modifications can, in effect, be made (such as, for example, replacement of the npn transistors with pnp transistors, and vice versa) without departing from the idea underlying the invention.

Even though the present invention has been described in relation to applications for telecommunications, it can find use in all the fields where closed-loop control is required of the peak of a periodic signal (or of a combination of periodic signals), irrespective of the nature, frequency and level of the signals involved.

Consequently, without prejudice to the principle of the invention, the details of construction and the embodiments may vary, even significantly, with respect to what is described and illustrated herein, purely by way of non-limiting example, without thereby departing from the scope of the invention, as defined in the annexed claims.

Claims

1. A device for comparing the peak value of at least one voltage signal with a reference voltage, the device comprising: a reference transconductor element for converting said reference voltage into a reference current;at least one respective transconductor element for converting said at least one voltage signal into at least one respective current signal;a current-comparison node for comparing said at least one respective current signal with said reference current, generating a comparison current as a difference between said at least one respective current signal and said reference current;a current rectifier supplied with said comparison current; anda hold capacitor, charged with the output current of said current rectifier, the voltage across said capacitor indicating the outcome of the comparison between said peak value of at least one voltage signal and said reference voltage.

2. The device according to claim 1, wherein said reference transconductor element comprises a resistor.

3. The device according to claim 1, wherein said at least one respective transconductor element comprises a resistor.

4. The device according to claim 1, further comprising a discharge-current generator.

5. The device according to claim 1, wherein said current rectifier comprises a transistor.

6. The device according to claim 1, wherein said current-comparison node and said current rectifier are obtained via a differential stage, supplied to the inputs of which are said voltage signal and said reference voltage.

7. The device according to claim 6, further comprising respective resistors for supplying said at least one voltage signal and said reference voltage to the inputs of the differential stage.

8. The device according to claim 6, wherein said differential stage comprises: a first pair of transistors cascaded between a supply voltage and ground and traversed by a first current, with said at least one voltage signal applied to the point of connection between the transistors of said first pair; anda second pair of transistors cascaded between a supply voltage and ground and traversed by a second current, with said reference voltage applied to the point of connection between the transistors of said second pair.

9. The device according to claim 8, wherein said hold capacitor is driven via said second pair of transistors.

10. The device according to claim 8, wherein the transistors of said first pair have their control terminal short-circuited with their current-inflow terminal.

11. The device according to claim 8, wherein the transistor of said first pair referenced to the supply voltage and the transistor of said second pair referenced to ground have their control terminal short-circuited with their current-inflow terminal.

12. The device according to claim 6, wherein said differential stage comprises a Wilson current mirror.

13. The device according to claim 6, wherein said differential stage comprises a cascode current mirror.

14. The device according to claim 6, wherein said differential stage comprises an output cascode configuration.

15. The device according to claim 1, further comprising, downstream of said current rectifier and of said comparator, a stage chosen between a common-emitter stage and a common-source stage with compensation by the Miller effect in order to produce as output signal of the device a signal indicating the voltage across said capacitor.

16. The device according to claim 1, further comprising a plurality of said respective transconductor elements for converting a plurality of voltage signals into a plurality of current signals supplied to said current-comparison node.

17. A device for comparing the peak value of at least one voltage signal with a reference voltage, the device comprising: a first current mirror having an input for receiving an input current, an output for receiving a reference current, and a power terminal coupled to ground;a second current mirror having a first power terminal coupled to the input of the first current mirror, a second power terminal coupled to the output of the first current mirror, an input for receiving a first bias current, and an output for receiving a second bias current; anda capacitor coupled to the output of the second current mirror for providing a peak detect output voltage.

18. The device of claim 17 wherein the first and second current mirror each comprise a simple current mirror.

19. The device of claim 17 wherein the first current mirror comprises a Wilson current mirror.

20. The device of claim 17 wherein the second current further comprises a cascode output transistor.

21. The device of claim 17 further comprising a plurality of resistors coupled to the input of the first current mirror.

22. The device of claim 17 further comprising a plurality of resistors coupled to the output of the first current mirror.

25. The device of claim 17 wherein the first and second current mirrors comprise NPN transistor current mirrors.

23. The device of claim 17 further comprising an output transistor coupled to the output of the second current mirror.

24. The device of claim 23 wherein the output transistor comprises a PNP transistor.

25. A peak detector comprising: a first current mirror having an input for receiving an input current, and an output for receiving a reference current;a second current mirror having a first power terminal coupled to the input of the first current mirror, a second power terminal coupled to the output of the first current mirror, an input for receiving a first bias current, and an output for receiving a second bias current; anda capacitor coupled to the output of the second current mirror for providing a peak detect output voltage.