Not applicable.
Not applicable.
The present invention relates to a device for compensating temperature drift of a voltage controlled oscillator (VCO) of a phased-locked loop (PLL) system, and to a method thereof.
The PLL is commonly integrated on integrated circuits to generate frequency signals or clocks for on-chip or external systems. As an essential part of PLL, the VCO is also required to be integrated in the same chip. Due to the physical property of semiconductor components, the oscillating frequency will drift over temperature. When working in PLL, the VCO is locked to a certain frequency by negative feedback mechanism, which in turn modulates the control voltage of the VCO according to temperature variation.
In the PLL system, the control voltage of VCO always has limited range, and this range becomes narrower and narrower as the semiconductor technology evolves. If the control voltage goes out of the desired range, the negative feedback loop will go out of order and finally lose lock.
In communication systems, such as Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and Long Term Evolution (LTE), the PLL works as either the frequency source for radio frequency modules or the reference clock for data converters or baseband processors. The transmission will terminate if the PLL goes out of lock, which is disastrous for communication equipment. Some PLL systems have an implemented automatic recover circuit, which can pull the PLL back to lock state when it goes out of lock. But this kind of recover circuit is usually a reactive circuit and the PLL still fails to give correct output in a short time interval. For the communication system having very strict throughput requirements, even 100 microseconds (μs) interruption of transmission is intolerable.
According to a first prior art solution (U.S. 2008/0150641 A1), a temperature dependent voltage source is introduced as the preset bias point for coarse tuning. That means that the PLL is initially locked at a point which had relatively large headroom to tolerate the drift induced by temperature variation. Although this solution can bring PLL into an initial condition with quite a big margin to tolerate the temperature change, it is still not enough. Firstly, as the integrated circuit technology scales down, the VCO has to work under lower and lower supply voltage. Secondly, state-of-the-art low phase noise VCO often implements very low VCO gain, which means relatively large voltage range is required to compensate for specified frequency change. So, this solution is not suitable especially for low-voltage designs.
According to a second prior art solution (U.S. 2009/0261917 A1), an auxiliary varactor is employed which is controlled by a temperature dependent voltage source. As the temperature changes, the capacitance of the auxiliary varactor is also changed, and consequently the VCO frequency changes. The characteristic of the temperature dependent voltage source and auxiliary varactor is designed to pull the VCO frequency to the inversed direction of drifting induced by temperature, and helps to stabilize the control voltage of the main varactor of VCO. This solution works on the assumption that the temperature characteristic of VCO is already known. But it is quite difficult to accurately predict temperature property of VCO. This problem becomes even worse for wide band designs. Modern integrated wide band VCOs usually have multi sub-band topologies, and the temperature characteristics are much different from high-end to low-end frequencies. A lot of design effort is required to get the proper compensation coefficient for the whole frequency range, and because it works in open loop mode, this solution still suffers from the coefficient error due to the process spreading. In addition, the temperature dependent voltage source might be quite noisy influencing the VCO in the negative.
Hence, there is a need in the art for an improved solution to the problem of temperature drift of VCOs of PLLs.
An object of the present invention is to provide a solution which mitigates or solves the drawbacks and problems of prior art solutions. Another object of the invention is to provide a low cost, energy effective solution to the problem of temperature drift.
According to a first aspect of the invention, the above mentioned objects are achieved with a device for compensating temperature drift of a VCO in a PLL, said VCO having at least one varactor arranged for controlling an output frequency fOut of said VCO by applying a tuning voltage VTune and simultaneously applying a bias voltage VBias on a cathode and an anode of said at least one varactor, respectively; said device comprising a monitoring circuit and a tuning circuit: said monitoring circuit having an input arranged to receive said tuning voltage VTune and being arranged to monitor said tuning voltage VTune and further being arranged to activate said tuning circuit based on a value of said tuning voltage VTune; and said tuning circuit having an output connected to said anode and being arranged to output said bias voltage VBias, wherein said tuning circuit further is arranged to tune said VCO by changing said bias voltage VBias so as to compensate for a temperature drift of said VCO.
Different embodiments of the above device are disclosed in the appended dependent claims.
According to a second aspect of the invention, the above mentioned objects are achieved by a method for compensating temperature drift of a VCO in a PLL, said VCO having at least one varactor arranged for controlling an output frequency fOut of said VCO by applying a tuning voltage VTune and simultaneously applying a bias voltage VBias on a cathode and an anode of said at least one varactor, respectively; said method comprising the steps of:
a) monitoring said tuning voltage VTune; and
b) tuning said VCO by changing said bias voltage VBias based on a value of said monitored tuning voltage VTune so as to compensate for a temperature drift of said VCO.
The present invention solves the temperature drifting problem of VCO in PLL systems with less size of integrated circuit chip area, less power consumption, and less sacrifice of phase noise to prior solutions. The present solution also means that the cost for producing the chip can be held low. Moreover, the present solution is more reliable compared to prior art solutions.
Further applications and advantages of the invention will be apparent from the following detailed description.
The appended drawings are intended to clarify and explain different embodiments of the present invention in which:
To achieve the aforementioned and other objects, the present invention relates to a device for compensating temperature drift of a VCO in a PLL. The VCO is of the type having at least one varactor arranged for controlling an output frequency fOut of the VCO by the application of a tuning voltage VTune and simultaneous application of a bias voltage VBias on a cathode and an anode of the at least one varactor, respectively. The device further comprises a monitoring circuit and a tuning circuit. The monitoring circuit has an input arranged to receive the tuning voltage VTune and is arranged to monitor the tuning voltage VTune. The monitoring circuit is further arranged to activate the tuning circuit based on a value of the monitored tuning voltage VTune. The tuning circuit has an output connected to the anode of the varactor and is arranged to output the bias voltage VBias. The tuning circuit is further arranged to tune the VCO by changing the bias voltage VBias so as to compensate for a temperature drift of the VCO.
Thereby, a closed loop solution to the problem of temperature drift of VCOs is provided. Since the present temperature compensation circuit works in closed loop, as it monitors the VTUNE and tune according to the value of VTUNE, it provides a more reliable solution compared to open-loop solutions. The present invention can therefore advantageously prevent the PLL from losing of lock due the ambient temperature variation, and guarantee the normal operation of the communication equipment in various working conditions. Furthermore, with the present invention the chip size needed can be held small which means that the cost of the chip is also low. Moreover, the compensation circuit can be formed of comparators and low-current charge-pump resulting in low power consumption.
The state-of-the-art low phase noise consists of inductor-capacitor (LC) resonate tank and loss compensation circuits. The frequency of the VCO is controlled by tuning the capacitance of the resonant tank, i.e. the relative voltage between anode and cathode of the varactor. Usually, the anode of the varactor is tied to a fixed potential, such as ground, and the cathode is tuned by the output voltage of Loop Filter in PLL, i.e. VTUNE in
In principle, the negative feedback mechanism of PLL will force VTUNE to a certain voltage that can make VCO output required frequency. With the help of state-of-the-art wide band VCO techniques, the VTUNE voltage can be set to some ideal value. Actually, the capacitance and parasitic capacitance of varactor or other semiconductor components is variable over temperature. That means, with fixed VTUNE voltage, the VCO frequency will be drifting over temperature. But the feedback loop will force frequency to be stable, in other words, the VTUNE voltage has to drift to keep this stability as temperature is changing. If this voltage goes out of limited range, the PLL will fail to lock.
An embodiment of the compensation circuit is shown in
As seen in
Depending on which of the switches that is activated, the capacitor C0 of the tuning circuit is charged or discharged, thereby controlling VBIAS. The charging or discharging is performed by a so called charge pump circuit of the tuning circuit. In
As mentioned, generally the voltage of VBIAS is controlled by injecting or dissipating charges on capacitor C0. This charge domain operation is accomplished by a charge pump circuit controlled by the hysteretic comparators.
During acquisition process of the PLL (starts operating before the coarse tuning system), the VBIAS voltage is preset to a certain voltage by the use of the preset voltage circuit shown in
By well designed IUP and IDN current and C0 capacitance, the bandwidth of this compensation circuit will be controlled low enough to keep the PLL tracking this variation. Since it can be controlled by current, the size of the capacitor can be cut down significantly which is advantageous. When the tuning circuit is active, the charge pump will charge or discharge the capacitor C0, thereby changing the bias voltage VBIAS. The changing speed of VBIAS is proportional to the charge pump current IUP or IDN, and anti-proportional to the capacitance of capacitor C0. In the PLL system, it is important to keep the changing speed of VBIAS to a reasonable low level, in order not to disturb the operation of the whole system. Here, this characteristic can be described as bandwidth: the wider the bandwidth, the faster the changing speed of VBIAS, and vice versa. In order to keep the changing speed of VBIAS low either the charge pump current IUP or IDN can be lowered, or the capacitance C0, can be increased. Usually, it is desired to lower down the current value in order to make the capacitance C0 as small as possible, because the capacitor will take relatively large area on the chip, and therefore increase the cost. However, the minimum current of IUP and IDN is limited by the semiconductor device's property, and hence the capacitance C0 must have a proper value to keep the changing speed of VBIAS low enough.
According to another embodiment of the invention when the PLL works as desired, the charge pump is not active which means that the noise contributed by the compensation circuit is null. Hence, the tuning circuit is arranged to operate in an active mode or in a passive mode in which the charge pump circuit is not active. When the circuit works in charging or discharging active mode, the noise from current source or current sink is very low if the IUP/IDN are designed very small to reduce the size of C0 . In addition, the capacitor C0 works as an integrator of current, and the noise at high frequency will be attenuated. Since the PLL can attenuate the low frequency noise of VCO, noise at high frequency offset is more attractive for VCO design.
For some VCO designs, the back side of the varactor needs to be connected to some fixed potential point, for instance ground or power supply. If this is the case, an auxiliary varactor can be introduced to tuning the capacitance of the resonate tank, as shown in
To verify the functionality of the present solution, system level simulations have been performed with the behavior model constructed by Verilog-A language. The simulation result is given in
Furthermore, the invention also relates to a corresponding method comprising the steps of: monitoring a tuning voltage VTune for a VCO of a PLL; and tuning the VCO by changing the bias voltage VBias based on a value of the monitored tuning voltage VTune so as to compensate for a temperature drift of the VCO. The method can be modified to e.g. comprise further steps corresponding to different embodiments, mutatis mutandis, of the device described above.
Finally, it should be understood that the present invention is not limited to the embodiments described above, but also relates to and incorporates all embodiments within the scope of the appended independent claims.
This application is a continuation of International Application No. PCT/EP2012/055931, filed on Apr. 2, 2012, which is hereby incorporated by reference in its entirety.
Number | Date | Country | |
---|---|---|---|
Parent | PCT/EP2012/055931 | Apr 2012 | US |
Child | 14461596 | US |