Patent Application
20240235678
The present invention relates to a control device intended to be provided in an access point of an optical wireless communication network.
Some optical wireless communication (OWC) networks, possibly of the LiFi (“Light Fidelity”) type, comprise a communication bus to which access points are connected. These access points enable communication equipment (such as cell phones (possibly smartphones), electronic tablets, or computers (possibly laptops)), coupled to OWC interface equipment (generally accessories (or “dongles”)), to communicate by means of intensity- and/or frequency-modulated light signals representative of data.
In this type of OWC network, each access point comprises an input/output interface connected to the communication bus, a transmitting stage suitable for converting a signal from the input/output interface into a transmitted light signal, and a receiving stage suitable for converting a received light signal into a signal which is communicated to the input/output interface.
Since all access points connected to the same communication bus must be able to communicate with each other one after the other, the greater the number of access points, the greater the sensitivity of their receiving stage must be (typically between −30 dB and −40 dB in the presence of more than twenty access points). As a result of this high sensitivity of the receiving stage, the light signal emitted by the receiving stage of an access point may be received a little later by the transmitting stage of the same access point, following at least one reflection (against a surface, for example). In this case, the data contained in the light signal received by an access point after reflection(s) returns to the communication bus via this same access point, and will therefore be retransmitted by the latter, which generates disturbances on the frame and can render the communication bus inoperative, since the same data can loop a large number of times, or even infinitely, at the same access point, and this loop can only be interrupted by physically cutting the optical link between the receiving and transmitting stages.
It may therefore be desirable to provide a control device which avoids at least part of the above-mentioned disadvantage.
In particular, a control device is proposed for equipping an access point comprising an input/output interface connected to a communication bus using a communication protocol, a transmitting stage suitable for converting a first signal from the input/output interface into a transmitted light signal, and a receiving stage suitable for converting a received light signal into a second signal passed on to the input/output interface.
This control device is characterized by the fact that it is arranged either to disable the receiving stage when the input/output interface receives a first signal from the communication bus, and to enable the receiving stage when the input/output interface no longer receives a first signal from the communication bus, or to disable the transmitting stage when the receiving stage receives a light signal, and to enable the transmitting stage when the receiving stage no longer receives a light signal.
This limits, or even prevents, the probability of loops and therefore disturbances to communication bus operation.
The control device according to the invention may comprise other features which may be taken separately or in combination, and in particular:
The invention also proposes an access point comprising an input/output interface suitable for connection to a communication bus using a communication protocol, a transmitting stage suitable for converting a first signal from the input/output interface into a transmitted light signal, a receiving stage suitable for converting a received light signal into a second signal passed on to the input/output interface, and a control device of the type presented above.
For example, this access point can be part of a Light Fidelity (or LiFi) optical wireless network.
The invention will be better understood with the aid of the following description, given solely by way of example and with reference to the appended drawings in which:
One of the purposes of the invention is to provide a control device 1 intended to form part of an access point 2-n (n=1 à N), itself intended to equip a communication bus 3 of an optical wireless communication (or OWC) network. N can take any value greater than or equal to one. For example, N can be between ten and thirty.
In the following, it is assumed that the optical wireless communication network is of the Light Fidelity (or LiFi) type. However, the invention is not limited to this type of optical wireless communication (or OWC) network. It concerns any type of optical wireless communication network based on time and/or frequency multiplexing.
As illustrated in
The input/output interface 4 is bidirectionally connected to the communication bus 3, which uses a selected communication protocol, such as CANBUS or MIL-STD-1553.
The transmitting stage 5 is designed to convert a first signal s1 from the input/output interface 4 into a light signal sle transmitted to at least one piece of communications equipment (not shown) to which an OWC interface device (usually an accessory (or dongle)) is coupled. For example, a piece of communication equipment could be a cell phone (possibly smart (or smartphone)), a tablet computer, a computer (possibly a laptop), a sensor, an on-board computer, or any other piece of communications equipment that can be connected to the communication bus 3.
The receiving stage 6 is able to convert a received light signal slr (from a communication device, via an OWC interface device) into a second signal s2, which it passes on to the input/output interface 4.
The control device 1, according to the invention, is arranged either to disable the receiving stage 6 when the input/output interface 4 receives a first signal s1 from the communication bus 3, and to enable the receiving stage 6 when the input/output interface 3 no longer receives a first signal s1 from the communication bus 3, or to disable the transmitting stage 5 when the receiving stage 6 receives a light signal, and to enable the transmitting stage 5 when the receiving stage 6 no longer receives a light signal.
In other words, when an access point 2-n has to transmit a light signal sle, its receiving stage 6 is disabled to prevent it from receiving this same light signal sle, after reflection(s), and when an access point 2-n receives a light signal slr, its transmitting stage 5 is disabled to prevent it from re-transmitting this light signal slr. This limits, or even prevents, the probability of loops and therefore disturbances to the operation of communication bus 3.
For example, and as illustrated non-limitatively in
The transmitting optoelectronic module 7 comprises at least one light source 9 responsible for generating the intensity- and/or frequency-modulated light signals sle representative of the data to be transmitted. This light source 9 may, for example, comprise at least one light-emitting diode (or LED) or at least one laser diode or at least one Vertical Cavity Surface-Emitting Laser (or VCSEL) diode.
The transmitting optoelectronic module 7 is responsible for carrying out the above-mentioned modulation and injecting the current required for data transmitting by the light source 9. It is in this transmitting optoelectronic module 7 that the electrical power supplied to light source 9 for data transmission is adjusted according to various constraints (maximum and minimum optical transmitting distances and power consumption, for example). Modulation and injection are provided by what is sometimes referred to as an AFE (“Analog Front-End”) device by those skilled in the art, which may include the light source 9 (as illustrated but not limited to).
Also by way of example, and as illustrated non-limitatively in
The receiving optoelectronic module 10 comprises at least one photoreceiver 12 responsible for capturing (or receiving) the light signals slr in order to convert them into an electrical signal of the current (or photocurrent) type. This photoreceiver 12 may, for example, comprise at least one photodiode or at least one avalanche photodiode or at least one Single-Photon Avalanche Diode (SPAD).
The receiving optoelectronic module 10 is responsible for filtering and amplifying the photocurrent delivered by photoreceiver 12, which generally has a very low amplitude (typically a few mV at most). It is in this receiving optoelectronic module 10 that reception sensitivity and dynamic range can be adjusted. Filtering and amplification are provided by an AFE (Analog Front-End) device, which may optionally include the photoreceiver 12 (as illustrated non-limitatively).
At least two embodiments can be envisaged for the control device 1. These two embodiments are described below with reference to
In a first embodiment illustrated in
For example, and as shown non-limitatively in
The first signal detector 13 is arranged to detect each first signal s1 (from the input/output interface 4) in the first conditioning module 8 and to enable/disable the receiving optoelectronic module 10 as required. It will be understood that when the first signal detector 13 detects a first signal s1 in the first conditioning module 8, it triggers the disabling of the receiving optoelectronic module 10, for example by transmitting to it a dedicated signal with a first value, and when the first signal detector 13 no longer detects a first signal s1 in the first conditioning module 8, it triggers the enabling of the receiving optoelectronic module 10, for example by transmitting to it this dedicated signal but with a second value. As shown non-limitatively in
The second signal detector 14 is arranged to detect each digital signal sn supplied by the receiving optoelectronic module 10 in the second conditioning module 11 and to enable/disable the transmitting optoelectronic module 7 as required. It will be understood that when the second signal detector 14 detects a digital signal sn in the second conditioning module 11, it triggers the disabling of the transmitting optoelectronic module 7, for example by transmitting to it a dedicated signal having a first value, and when the second signal detector 14 no longer detects a digital signal sn in the second conditioning module 11, it triggers the enabling of the transmitting optoelectronic module 7, for example by transmitting to it this dedicated signal but with a second value. As shown non-limitatively in
By way of example, the first 13 and second 14 signal detectors may each comprise a monostable multivibrator.
In a non-limiting embodiment illustrated in
For example, this controller 15 can be arranged to enable/disable the transmitting optoelectronic module 7 and receiving optoelectronic module 10 as required.
Also by way of example, and as illustrated non-limitatively in
It will be noticed that the controller 15 comprises at least one processor (or processing unit) and at least one memory cooperating together. The processor (or processing unit) may, for example, be a digital signal processor (or DSP). The memory stores data files and computer program(s) whose instructions are intended to be executed by the processor (or processing unit). This memory may, for example, be RAM (“Random Access Memory”), but it could be of another type. This processor and memory are arranged to perform detection and enabling/disabling operations together within their access point 2-n. The controller 15 may also comprise an input interface for receiving at least the first signals s1 and digital signals sn for use in calculations or processing, possibly after shaping and/or demodulating and/or amplifying them, in a manner known per se, by means of a digital signal processor. In addition, this controller 15 may also comprise an output interface, in particular for delivering enabling/disabling messages, and/or a mass memory. This controller 15 can, for example, be implemented in the form of a combination of electrical or electronic circuits or components (or “hardware”), possibly micro-programmed or micro-wired, software modules (or “software”), FPGA-type integrated circuits (“Field Programmable Gate Array”) and specialized integrated circuits (or ASIC (“Application-Specific Integrated Circuit”)).
In a second embodiment illustrated in
This second embodiment is used when the time taken by a light signal sle emitted by an access point 2-n to return to the latter (2-n) is shorter than the second duration dd2 required for disabling the receiving stage 6, and/or when the duration of internal processing and propagation of a signal sn, s2 resulting from a received light signal slr is shorter than the first duration dd1 required for disabling the transmitting stage 5. This guarantees that there will be no interference or echoes between the transmitting stage 5 and the receiving stage 6, despite the high sensitivity of the latter (6), but also that the latencies introduced (notably by internal propagations) will not create too great an offset in relation to the communication speeds and latencies imposed by the various protocols.
In this second embodiment, the control device 1 may, for example, be able to act on (“enable/disable”) the first 8 and second 11 conditioning modules. In this case, the first sum ps of the first time shift dt1 and a first propagation time tp1 of the first signal s1 in the first conditioning module 8 added to the second sum ss of the second time shift dt2 and a second propagation time tp2 of the digital signal sn representative of a second signal s2 in the second conditioning module 11 is preferably less than half the period (T/2) of the communication protocol of the communication bus 3 (i.e., ps (=dt1+tp1)+ss (=dt2+tp2)<T/2, with dt1>dd2 and dt2>dd1). For example, if the communication protocol operates at 1 MHz, then T/2=500 ns, and therefore ps+ss<500 ns. This is the case, for example, when dd1=dd2=100 ns, dt1=dt2=180 ns and tp1=tp2=18 ns (it can be verified that then ps+ss=(180+18)*2=396 ns<500 ns.
For example, and as shown non-limitatively in
The first signal detector 16 is arranged to detect each first signal s1 (from the input/output interface 4) and to enable/disable the second conditioning module 11 as required. It will be understood that when the first signal detector 16 detects a first signal s1 downstream of the input/output interface 4, it triggers the disabling of the second conditioning module 11, for example by transmitting to it a dedicated signal having a first value, and when the first signal detector 16 no longer detects a first signal s1 downstream of the input/output interface 4, it triggers the enabling of the second conditioning module 11, for example by transmitting to it this dedicated signal but with a second value. As shown non-limitatively in
The second signal detector 17 is arranged to detect each second signal s2 supplied by the second conditioning module 11 and to enable/disable the first conditioning module 8 as required. It will be understood that when the second signal detector 17 detects a second signal s2 supplied by the second conditioning module 11, it triggers the disabling of the first conditioning module 8, for example by transmitting to it a dedicated signal having a first value, and when the second signal detector 17 no longer detects a second signal s2 supplied by the second conditioning module 11, it triggers the enabling of the first conditioning module 8, for example by transmitting to it this dedicated signal but with a second value. As shown non-limitatively in
By way of example, the first 16 and second 17 signal detectors may each comprise a monostable multivibrator.
Also, by way of example, and as illustrated non-limitatively in
As shown non-limitatively in
The use of comparators 18, 19 is particularly interesting when the time offsets dt1, dt2 to be introduced are typically greater than a hundred nanoseconds. When the time offsets dt1, dt2 to be introduced are less than a hundred nanoseconds, they can be implemented by “lower-level” analog electronics (typically transistors and filters) coupled with a routing technique enabling the propagation times of the various signals to be controlled, so as to enable finer adjustment of the enabling times (for example, by adjusting the lengths of the tracks propagating the signals).
In a non-limiting embodiment illustrated in
For example, this controller 20 can be arranged to enable/disable the first conditioning module 8 and second conditioning module 11 as required.
Also, by way of example, and as illustrated non-limitatively in
Also, for example, the controller 20 can be arranged to introduce the first dt1 and second dt2 time offsets, which is possible if signals s1 and s2 pass through this controller 20, which is then not limited solely to detecting signals s1 and s2.
It will be noticed that the controller 20 comprises at least one processor (or processing unit) and at least one memory cooperating together. The processor (or processing unit) may, for example, be a digital signal processor (or DSP). The memory stores data files and computer program(s) whose instructions are intended to be executed by the processor (or processing unit). This memory may, for example, be of the RAM type, but it could be of another type. This processor and this memory are arranged to perform detection and enabling/disabling operations together within their access point 2-n. The controller 20 may also comprise an input interface for receiving at least the first signals s1 and second signals s2 for use in calculations or processing, possibly after shaping and/or demodulating and/or amplifying them, in a manner known per se, by means of a digital signal processor. In addition, this controller 20 may also include an output interface, in particular for delivering enabling/disabling messages, and/or a mass memory. This controller 20 can, for example, be implemented in the form of a combination of electrical or electronic circuits or components (or hardware), possibly micro-programmed or micro-wired, software modules (or software), FPGA-type integrated circuits and specialized integrated circuits (or ASICs).
The use of a controller 20 significantly increases flexibility thanks to global, centralized management of all propagation times (and in particular time offsets dt1 and dt2) and real-time communication speeds, as well as real-time enabling/disabling, since the origin of signals and data is known at all times.
It should also be noticed that the invention is not limited to the above-described embodiments. Indeed, it will be apparent to those skilled in the art that various modifications can be made to the embodiments described above, in the light of the teaching just disclosed. In the detailed presentation of the invention given above, the terms used should not be interpreted as limiting the invention to the embodiments set out in the present description, but should be interpreted to include all equivalents the anticipation of which is within the reach of those skilled in the art by applying their general knowledge to the implementation of the teaching just disclosed to them.
| Number | Date | Country | Kind |
|---|---|---|---|
| FR2106322 | Jun 2021 | FR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/IB2022/055496 | 6/14/2022 | WO |
