Patent Application
20230289320
The present application is generally directed to communication system, and more particularly to a device for decoding the data communication under universal serial bus standard.
Universal Serial Bus (USB) is a standard of an interface, which has been developed for enhancing the expandability of a peripheral device (USB device/function device) connected to a USB host such as a personal computer. USB is a serial interface standard which allows communications between a host device and various USB-compliant devices to be performed via a common bus line.
USB 1.X defines two modes having different data transfer rates, i.e. low-speed mode (LS) of 1.5 Mbps and full-speed mode (FS) of 12 Mbps. The LS and FS mode may also be used in the standard termed USB 2.0, USB 3.0, etc.
Under USB standard, in principle, one USB host device can be connected with up to 127 devices via a common bus line which includes USB data lines and power supply lines. In order to decode the data transmission on the USB data lines, usually a field programmable gate array (FPGA) or a microcontroller/microprocessor may be used to complete USB clock synchronization and USB signal analysis.
There remains a need for a system with low cost for decoding the data communication under universal serial bus standard.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to be relied on to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
According to one aspect of the application, a device adapted to implement a state machine which defines a plurality of predetermined states and a plurality of predetermined events, for decoding USB data communicated over a universal serial bus (USB), the device comprising:
In one or more embodiment, a clock rate of the device clock is at least 6 times the data transferring rate over the USB.
In one or more embodiment, a clock rate of the device clock is no more than 12 times of the data transferring rate over the USB.
In one or more embodiment, the device further comprises an indicator output terminal configured to output an indication signal indicative that the bus state of the USB is an end of package or not.
In one or more embodiment, the control circuitry further comprises a counter unit (312) including first and second counters that are configurable to operate as a unified 32-bit counter or as two separate 16-bit counters.
In one or more embodiment, the control circuitry further comprises a control logic circuitry connected to the counter unit to provide control signals for the counters of the counter unit, wherein the control logic circuitry is also connected to the event generator to receive event signals therefrom, and wherein the control logic circuit is configured to use the control signals to reset the counter after an event is triggered by the event generator.
In one or more embodiment, the control circuitry further comprises a match register configured to load expected match value.
In one or more embodiment, the control circuitry further comprises a match logic module configured to generate a match logic in response to the count values from the counter unit begin equals to the match values from the match register, and wherein the one of the predetermined events is triggered only when the match logic is generated.
In one or more embodiment, the device further comprises an interrupt module connected to the event generator, wherein the interrupt module is configured to generate an interrupt signal in response to receiving a predetermined one of the event signals from the event generator.
According to a second aspect of the application, an apparatus for decoding USB data communicated over a universal serial bus (USB). The apparatus comprises a device. The device comprises:
In one or more embodiment, the apparatus further comprises a co-processor comprising input terminals and output terminals, wherein the input terminals of the co-processor are coupled to the output terminals of the device and configured to receive the output clock and the decoded stuffed-bit stripped synchronized data from the device, wherein the co-processor is configured to convert the decoded stuffed-bit stripped synchronized data and output clock into serial peripheral interface (SPI) signals. The Serial Peripheral Interface (SPI) is a synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems.
In one or more embodiment, the device comprises an indicator output terminal configured to output an indication signal indicative of whether the bus state of the USB is an end of package (EOP), and wherein the co-processor is configured to convert the indication signal to a corresponding signal compliant with the SPI specification.
In one or more embodiment, the apparatus further comprises a serial peripheral interface (SPI) interface coupled to the output terminals of the co-processor, wherein the apparatus is configured to output the SPI indication signal, SPI data signal and SPI clock signal via the SPI interface.
In one or more embodiment, a clock rate of the device clock is no more than 12 times of the data transfer rate over the USB.
According to a third aspect of the application, a non-transitory computer-readable medium storing a program to execute processing for decoding USB data, communicated over a universal serial bus (USB):
In one or more embodiment, providing control information to the event generator includes at least one of selecting a rising edge of the synchronized data as an ingredient of the event, and selecting a falling edge of the synchronized data as an ingredient of the event.
In one or more embodiment, providing control information includes generating count values at counters; loading match values to match registers; and comparing the count values from the counters with the values stored in the match registers to produce a match result.
In one or more embodiment, generating count values includes generating two counter values that represent a unified 32-bit count values or two separate 16-bit count values.
In one or more embodiment, a clock rate of the device clock is no more than 12 times of the data transferring rate over the USB.
In one or more embodiment, the processing further comprises generating an interrupt signal in response to a predetermined event signal from the event generator.
So that the manner in which the above recited features of the present application can be understood in detail, a more particular description of the application, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this application and are therefore not to be considered limiting of its scope, for the application may admit to other equally effective embodiments. The drawings are for facilitating an understanding of the application and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying drawings, in which like reference numerals have been used to designate like elements, and in which:
USB does not transmit data directly on the USB data lines. It converts the data into NRZI encoded data with Not-Return-to-Zero-Inverse (NRZI) encoding, and then the NRZI encoded data are transmitted on the USB data lines. Data capture by using a conventional low cost microcontroller may therefore be challenging. The NRZI data comprises J state and K state.
A string of raw data “1”s as shown throughout most of the “Packet-Data” interval in the upper waveform, at 101, may cause long periods with no transitions in the encoded data. In order to ensure adequate signal transitions, A “0” is inserted after every six consecutive “1”, in the raw data, as shown by the middle waveform, at 102. This process is known as “bit stuffing” and the inserted “0” is known as a “stuffed-bit”. The stuffed data packet is then converted to NRZI, with each “0” causing a data transition, and each “1” causing no transition, as shown by the lower waveform, at 103. One difficulty in decoding the data on the USB data lines is how to detect the stuffed-bit. In addition, in order to decode the USB data lines, it is also necessary to ensure clock synchronization.
The system 200 uses bit stuffing and NRZI encoding system (not shown) in physical layer of the USB host 202 to encode the data for USB transmission. The system 200 may be used for LS and FS mode which may be used in the standard of USB 1.x, 2.0, 3.0 etc.
The device 208 may be coupled to one of the USB host 202 and the USB device 204. In some embodiments, the device 208 may be on the host side and coupled to the USB host 202 through cables. In some embodiments, the device 208 may be on the function side and coupled to the USB device 204 through cables. In some other embodiments, the device 208 may be located separately from the host side and the function side and coupled to one of the USB host 202 and the USB device 204 through cables.
The device 208 may be a peripheral which is adapted to implement a state machine with one 32 bit counter. In some embodiments, the device 208 is adapted to implement a state machine with two 16 bit counters. Each of the 16 bit counters may be used for some parts of the state machine. The state machine defines a plurality of predetermined states and a plurality of predetermined events, for decoding USB data communicated over a universal serial bus (USB). The device 208 is configured to receive the data over the USB data lines 206 and then synchronize the data, provide decoded stuffed-bit stripped synchronized data by using the predetermined states and events.
The device 208 comprises pair of data input terminals 218, 228 for receiving the USB encoded data with bit stuffing which is encoded from the raw data. Then the device 208 synchronizes the data and processes the synchronized data based on the predetermined events and states. The device 208 also comprises a clock input terminal (not shown) for receiving a system clock from a clock source. Then the device 208 identifies the stuffed-bits and decode synchronized data to raw data “1” and raw data “0”. Some of the predetermined events comprise identifying a stuffed-bit in the synchronized data. Some of the predetermined events comprise stripping the identified stuffed-bit from synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data. A combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data, and a further of the predetermined events comprises outputting decoded stuffed-bit stripped synchronized data and toggling the output clock at the output terminals.
The USB data lines 206 include two data lines D+/D− that carry the encoded data. The synchronized data from each of the data lines D+ and D− have high level and low level. And there are rising edges from the low level to the high level and falling edges from the high level to the low level. The device 208 checks if the USB bus state is “end of package” (EOP) which means the synchronized data are not valid. If the USB bus state is not EOP, the synchronized data “1” means the state of the data on one of the data lines D+ and D− does not change, and the synchronized data “0” means the state of the data on the data lines D+ and D− changes. When the synchronized data from the D+ have one of the rising edge and the falling edge, the synchronized data from the D− have corresponding one of the falling edge and the rising edge. Then the device 208 may use one of the data lines D+ and D− to decode the synchronized data. The device 208 decodes the synchronized data “1” when the data on the data line D− and data line D+ does not have a rising edge or a falling edge. The device 208 decodes the synchronized data “0” when the data on the data lines D+ D− has one of the rising edge and the falling edge. The device 208 identifies a stuffed-bit when the synchronized data “0” is received after six synchronized data “1” received consecutively. The stuffed-bit will not be output by the device 208 and the output clock will not be toggled. The device 208 outputs the decoded stuffed-bit stripped synchronized data when the output clock is toggled.
The details of the device 208 will be described below in combination of
The pair of data input terminals are used for receiving the USB data, and the clock input terminal is used for receiving a system clock. The clock processor 302 is coupled to the pair of data input terminals and the clock input terminal, and is configured to output synchronized data for the event generator 304 and a device clock (SCT clock) based on the system clock for various components of the device 300. The device also outputs a prescaler clock for the prescaler 314. The system clock may be generated by a clock generator. In some embodiments, the device clock and the prescaler clock are equivalent to the system clock. However, in other embodiment, one or both of the device clock and the prescaler clock may be differ from the system clock with respect to clock rate. The clock rate is also referred to as the clock frequency. For the full-speed mode (FS), the data transferring rate over the USB is typically 12 Mbps. In some embodiments, the clock rate of the device clock is no more than 12 times of the data transferring rate over the USB. The clock rate of the device clock may be one of 72 MHz, 96 MHz, 120 MHz and 144 MHz. Then the clock rate of the system clock of device 300 may be 6 times, 8 times, 10 times or 12 times of the data transferring rate. By this way, the device 300 may have enough time to decode the data package on the USB.
The prescaler 314 is configured to produce one or more clock signals for the counter unit 312 using the prescaler clock from the clock processor 302. The control logic circuitry 320 is configured to produce control signals to control at least one counter of the counter unit 312. The control signals determine when the counter is incremented, cleared and loaded. The control logic circuitry 320 includes an input to receive event signals generated by the event generator 304. The control logic circuitry is configured to provide corresponding control signals to the counter unit 312 in response to different event signals, i.e., when certain events are triggered. The control logic circuit 322 is configured to use the control signals to reset the counters of the counter unit 312 after an event is triggered by the event generator 304.
The counter unit 312 is configured to produce one or more running count values. As mentioned above, the counter unit includes one or more counters. In an embodiment, the counter unit 312 includes first and second counters that are configurable to operate as a unified 32-bit counter or as two separate 16-bit counters. In this embodiment, each counter of the counter unit 312 is connected to prescaler 314 to receive the device clock. Each counter is also connected to the control logic circuitry 320 to receive the control signals from the control logic circuitry 320. Thus, each counter maintains a count value using the device clock from the prescaler 314 and using the control signals from the control logic circuitry 320.
The match register 316 is configured to load expected match value. In some embodiments, the expected match value may be thirteen when the clock rate of the system clock of device 300 is 12 times of the data transferring rate, which means the USB data may be received at the time of the thirteenth clock cycle comes.
The match logic module 318 is configured to generate a match logic in response to the count values from the counter unit 312 equals to the expected match values from the match register, and wherein the one of the predetermined events is triggered only when the match logic is generated. Thus, each data from the USB could be captured for every twelve counts when the clock rate of the system clock of device 300 is twelve times of the data transferring rate.
The event generator 304 is coupled to the clock processor 302 to receive the synchronized data and the device clock. The state logic circuitry 306 is coupled to an output of the event generator 304. The state logic circuitry 306 is configured to store a present state, being a one of the predetermined states. The output terminals 308 are coupled to the event generator 304 and comprise a decoded-data output terminal and a clock output terminal. The event generator 304 is configured to trigger respective ones of the predetermined events, in response to respective combinations of values of the synchronized data, the device clock, the control information and the present state. Referring to
In some embodiments, the output terminals 308 are configured to output an indication signal indicative whether the bus state of the USB is an end of package (EOP) or not.
In some embodiments, an interrupt module 310 is configured to generate an interrupt signal in response to receiving a predetermined one of the event signals from the event generator.
Thus, present application uses a device adapted to implement a state machine with predetermined states and events to decode the data communication on the USB bus. The device may be implemented with a low cost MCU which may reduce the cost and may be easily integrated into other embedded products such as a secure bus monitor.
Referring back to
The co-processor 212 comprises input terminals 220, 222, and 224 and at least one output 226 terminal. The input terminals 220, 222 of the co-processor 212 are coupled to the output terminals of the device 208 and configured to receive the output clock (at input terminal 220) and the decoded stuffed-bit stripped synchronized data (at input terminal 224) from the device 208. The co-processor 212 is configured to convert the decoded stuffed-bit stripped synchronized data and output clock into serial peripheral interface (SPI) signals. In some embodiments, In some embodiments, the device 208 also outputs an indication signal as shown by SCT_CS to the input 222 of the co-processor 212. The indication signal SCT_CS is used for indicating whether the bus state of the USB is an end of package (EOP) or not. Then the co-processor 212 is configured to convert the indication signal to a SPI indication signal as shown as SPI_CS. The co-processor 212 may transmit the SPI signals to the SPI interface 214 by internal bus. In embodiments which are implemented on or together with an ARM Cortex M architecture, the internal bus may include AHB bus and APB bridge. In some other embodiments, the co-processor 212 may convert the raw data signals in other ways to meet different requirement.
The serial peripheral interface (SPI) interface 214 is coupled to the output terminals 216 of the processor. The apparatus 216 may be configured to output the SPI indication signal (SPI_CS), SPI data signal (SPI_MOSI) and SPI clock signal (SPI_CLK) via the SPI interface 214.
In some embodiments, a USB transceiver 210 is coupled between the USB host 202 and the device 208 for improving the signal quality and signal integrity. The USB data lines D+ and D− carry analog data. The transceiver 210 is used to transfer the analog data to digital data. In some other embodiments, the device 208 may also receive the data from data lines directly without the transceiver 210 because the analog data from the data lines are similar to digital data. The USB transceiver 210 may be implemented using a transceiver which is well-known in the art.
A non-transitory computer-readable medium stores a program to execute processing for decoding USB data. The USB data is communicated over a universal serial bus (USB) and input to a pair of data input terminals, and a system clock is put to the clock input terminal. The processing comprises generating synchronized data and a device clock based on a system clock by a clock processor 302; providing the synchronized data to an event generator 304; providing control information to the event generator, wherein the control information is generated by a control circuitry 322; providing a present state stored by a state logic circuitry 306 to the event generator; providing a plurality of predetermined events to a plurality of registers of the event generator; triggering respective ones of the predetermined events is in response to respective combinations of values of the synchronized data, the device clock, the control information and the present state. A one of the predetermined events comprises identifying a stuffed-bit in the synchronized data, another of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, a combination of the predetermined events comprises decoding stuffed-bit stripped synchronized data, and a further of the predetermined events comprises outputting, at the output terminals, decoded stuffed-bit stripped synchronized data and toggling the output clock. In some embodiments, a clock rate of the device clock is no more than 12 times of the data transferring rate over the USB.
In some embodiments, the processing provides control information to the event generator includes at least one of selecting a rising edge of the synchronized data as an ingredient of the event, and selecting a falling edge of the synchronized data as an ingredient of the event.
In some embodiments, the processing provides control information includes generating count values at counters; loading match values to match registers; and comparing the count values from the counters with the values stored in the match registers to produce a match result.
In some embodiments, the processing generates count values includes generating two counter values that represent a unified 32-bit count values or two separate 16-bit count values.
In some embodiments, the processing further comprises generating an interrupt signal in response to a predetermined event signal from the event generator.
In some embodiments, the operation of device 208 decode the data with NRZI encoding may include the following steps.
S401 is a step for initializing output signals of the device 208. For example, the indication signal SCT_CS is set to zero. Both of the clock signal SCT_CLOCK and the raw data signal SCT_DATA are set to one.
S402 is a step for detecting or decoding the data received on the USB data lines D+ and D−. If a data packet has been supplied to the device, the operation goes to S403.
S403 is a step for handling the bus state. If the bus state of the data signal lines is on an “SE0” state which means both of the data signal line D+ and the data signal line D− are at low level and the bus state of the USB is an end of package (EOP), then goes to S404. If the bus state is not an EOP, the operation goes to S406.
S404 is a step for processing the end of packet (EOP). After processing the EOP, goes to S405.
S405 is a step for setting the indication signal output by device 208 to zero. The operation returns to S402.
S406 is a step for processing data on the USB data lines. And the operation goes to S407.
S407 is a step for checking whether USB D− has rising or falling edge. If the USB D− does not have rising or falling edge, the operation goes to S408. If the USB D− has rising or falling edge, the operation goes to S410. In some embodiments, the step S407 may also be used for judging whether USB D+ has rising or falling edge.
S408 is a step for telling the data on the USB data lines is not changed and the raw data is one. The operation goes to S409.
S409 is a step for setting the raw data signal SCT_DATA to one, toggling the clock signal SCT_CLOCK and setting the indication signal SCT_CS to one.
S410 is a step for checking whether a bit stuffing is inserted or not. If six ones have been received consecutively, the next data zero will be treated as a stuffed-bit and the operation goes to S411. Otherwise, the operation goes to S412.
S411 is a step for ignoring the stuffed-bit. And the operation returns to S402.
S412 is a step for telling the data zero received as the raw data zero. The operation goes to S413.
S413 is for setting the raw data signal SCT_DATA to zero, toggling the clock signal SCT_CLOCK and setting the indication signal SCT_CS to one. And the operation returns to S402.
The device 208 operates in this manner, making it possible to decoding the data with NRZI encoding on the USB and detecting the stuffed-bit and realizing clock synchronization.
The device 208 may be adapted to implement a low state machine (“L State Machine”) part and a high state machine (“H State Machine”) part. Both the low state machine and the high state machine are implemented with hardware.
The clock source of state machine may be at 144 MHz and the USB data communication may be under full speed mode with the data transferring rate over the USB of 12 Mbps. The low state machine part may include first counter (“L counter”) and the high state machine part may include second counter (“H counter”). The first counter may be known as using the first half bits of a 32-bit counter. The higher counter may be known as using the second half bits of the 32-bit counter.
Some of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data. As shown in
The state logic circuitry 306 in
The event generator 304 in
A combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data.
A further of the predetermined events comprises outputting, at the output terminals, the decoded stuffed-bit stripped synchronized data and toggling the output clock.
Some of the predetermined events comprising detecting the end of the package. As shown in
In this way, the device 208 is configurated to comprise two state machine parts (L State Machine part and High State Machine part) to process the USB signal with predetermined states and events. The Low state machine part is for processing USB data streams. The high state machine part is for detecting USB EOP. In other embodiments, the “H State Machine” part may be used for processing USB data streams. And the “L State Machine” part may be used for detecting USB EOP.
Although the operations of the method herein are shown and described in a particular order, the order of the operations of the method may be altered so that certain operations may be performed in an inverse order or so that certain operations may be performed, at least in part, concurrently with other operations.
Referring now to the use of the terms “a” and “an” and “the” and similar referents in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of protection sought is defined by the claims as set forth hereinafter together with any equivalents thereof entitled to. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illustrate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the term “based on” and other like phrases indicating a condition for bringing about a result, both in the claims and in the written description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the application as claimed.
Preferred embodiments are described herein, including the best mode known to the inventor for carrying out the claimed subject matter. Of course, variations of those preferred embodiments will become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventor expects skilled artisans to employ such variations as appropriate, and the inventor intends for the claimed subject matter to be practiced otherwise than as specifically described herein. Accordingly, this claimed subject matter includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed unless otherwise indicated herein or otherwise clearly contradicted by context.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210252656.7 | Mar 2022 | CN | national |
