Patent Application
20050029959
The present invention relates to a device for generating a voltage ramp in a plasma display panel.
Plasma display panels, called hereafter PDPs, are flat displays. They generally comprise two parallel insulating plates, each bearing one or more arrays of electrodes and defining between them a gas-filled space. The plates are joined together so as to define intersections between the electrodes of these arrays. Each intersection of electrodes defines an elementary cell to which corresponds a gas space partially bounded by barrier ribs and in which an electrical discharge takes place when the cell is activated. Conventionally, two arrays of crossed electrodes, each array being placed on a different plate, serve for addressing discharges in the cells, and two arrays of parallel coplanar electrodes serve to sustain these discharges. In general, one of the arrays of coplanar electrodes serves both for addressing and sustaining. The panel therefore comprises three arrays of electrodes. In the rest of the description, the array of electrodes serving only for addressing the cells of the PDP is denoted by A, the array of electrodes serving only to sustain the cells of the PDP is denoted by X and the array of electrodes serving both to address and sustain the cells of the PDP is denoted by Y. The arrays X and Y placed on the same plate and the electrodes of the array A are orthogonal to those of the array X and of the array Y. These arrays are covered with a dielectric layer, especially to provide a memory effect. This dielectric layer is itself covered with a protective and secondary-electron emission layer, generally based on magnesia.
Each electrode of the array X forms with an electrode of the array Y a pair of electrodes defining between them a succession of light discharge regions, generally distributed along a row of discharge regions of the panel. The electrode arrays X and Y therefore supply rows of discharge regions, whereas the electrode array A serving only for addressing supplies columns of discharge regions. The light discharge regions form a two-dimensional matrix on the panel.
The adjacent discharge regions, at least those that emit different colours, are generally bounded by barrier ribs. The walls of the light discharge regions are generally partially coated with phosphors sensitive to the ultraviolet radiation from the light discharges. Adjacent discharge regions are provided with phosphors emitting different primary colours, so that the combination of three adjacent regions forms an image element or pixel.
When the plasma panel is in operation, to display an image, a succession of display or sub-display operations is carried out using the matrix of discharge regions. Each sub-display operation generally comprises the following steps:
After a sub-display operation, the discharge regions may be in very different internal electrical voltage states, especially depending on whether these regions have or have not been activated during this sub-display operation; other factors contribute to this dispersion of the internal voltage states, such as the nature of the phosphors corresponding to these regions, the inevitable fluctuations in the dimensional characteristics of these discharge regions, and the fluctuations in the composition of the surface of the walls of these regions, which are due to the panel manufacturing processes.
In order for the internal voltage state of the discharge regions to be addressed to be made uniform, most of the address steps are preceded by a step of resetting these regions, the purpose of which is essentially to reset all the discharge regions to be addressed in the same internal voltage state, whether or not they have been activated during the preceding sub-display operation; this reset step conventionally comprises an electric charge priming operation followed by a charge adjustment operation, also called an “erase” operation in which these charges are erased and after which, ideally, the internal voltages within each discharge region are close to the ignition thresholds for the said regions.
For each pair of address or sustain electrodes of a discharge region, it is possible to associate an external voltage applied between these electrodes and an internal voltage in the gas space separating the materials that cover these electrodes. The internal voltage generally differs from the external voltage owing to the surface charges that occur on the surface of the insulating materials that cover the electrodes, and the interface between these dielectrics and the gas in the discharge region.
These surface charges result, on the one hand, from a capacitive effect due to the dielectric properties of the materials that define the discharge regions and, on the other hand, from an accumulation of charges called “memory” charges that are produced by the preceding discharges within the gas in these discharge regions.
These priming and erase operations are generally carried out by applying a voltage ramp to the electrodes of the array Y of the PDP, the potential on the electrodes of the arrays X or A of the PDP being kept constant. More precisely, the priming of electrical charges on the cells of the PDP is obtained by applying a rising voltage ramp to the electrodes of the array Y and the adjustment of the charges is obtained by applying a falling voltage ramp again to the electrodes of the array Y of the PDP.
At the present time, in plasma panels, the voltage ramps are generated by circuits using DC voltage sources and power transistors operating in linear mode. This operation of the transistors in linear mode therefore introduces energy losses that obey a law of the CV2F type where C represents the overall capacitance of the group of cells to be set, this capacitance being that of the electrode array Y relative to the two other arrays A and X, V is the maximum charging voltage to be reached, which is around 400 to 600 V, and F is the number of charges and discharges in the cells per second. The corresponding power reached at the present time is about 10 W. It is worthwhile reducing this energy loss, not only in order to improve the energy efficiency of the device, but also to reduce the temperature rise of the transistors that expend this energy and thus reduce the dimensions of these transistors and of the heat sinks serving to dissipate this energy.
To reduce these losses, it is known to create a resonance of the capacitance of the plasma panel with an inductor. Such a device is disclosed in International Patent Application WO 02/058041 filed in the name of LG Electronics Inc. In that device, the energy losses obey a law of the RPi2 type where RP is the residual resistance of the device, the said residual resistance being able to be reduced by choosing weakly resistive components, something which represents a cost. That device also has the following drawbacks:
The present invention proposes a device for generating voltage ramps in plasma panels that generates small energy losses and completely or partly alleviates the aforementioned drawbacks.
The present invention relates to a device for generating a voltage ramp in a plasma display panel comprising a plurality of cells, the said voltage ramp being applied to electrodes of the cells of the plasma display panel in order to prime and/or reset electrical charges on the walls of the said cells, the said device comprising a DC voltage source, an inductor, switches and diodes, characterized in that, to generate the said voltage ramp, the switches operate in chopping mode.
According to one particular embodiment, the device comprises four switches, each provided with a diode in parallel. The device then comprises:
Other features and advantages will become apparent on reading the description that follows, this being given with reference to the appended drawings in which:
According to the invention, the switches of the device operate in a chopping mode in order to generate the voltage ramps. The voltage ramps generated may be rising or falling, it being possible for this rise or fall to be linear or non-linear.
The switches M1 and M2 are connected in series between the positive and negative terminals of the DC voltage source G. In the present example, the negative terminal of the source G is connected to earth, without this being necessary. The switches are MOS power transistors. The drain of the transistor M1 is connected to the positive terminal of the voltage source G, its source is connected to the drain of the transistor M2, and the source of the transistor M2 is connected to the negative terminal of the voltage source G. Moreover, the diode D1 is connected in parallel with the transistor M1, its cathode being connected to the positive terminal of the voltage source G, and the diode D2 is connected in parallel with the transistor M2, its anode being connected to the negative terminal of the voltage source G.
The switches M3 and M4 are connected in series between the electrodes of the array Y of the plasma panel and the negative terminal of the voltage source G. The drain of the transistor forming the switch M3 is connected to the electrodes of the array Y and its source is connected to the drain of the transistor forming the switch M4. The source of the transistor M4 is connected to the negative terminal of the voltage source G. The diode D3 is connected in parallel with the transistor M3, its cathode being connected to the drain of the transistor M3, and the diode D4 is mounted in parallel with the transistor M4, its anode being connected to the negative terminal of the voltage source G. The inductor L is connected between the mid-point of the switches M1 and M2 and the mid-point of the switches M3 and M4.
A control circuit (not shown) is provided for turning the switches M1 to M4 off and on.
The operation of this device will now be described with reference to
The curve in the upper part of
These phases are denoted by 1 to 9. During each phase, the switches of the device are either in the off-state, or in the on-state, or in a chopping mode in which they alternate between an on-state and an off-state with a chopping frequency f.
The table in the lower part of
In the table, the switches in an on-state are denoted by “on”, the switches in an off-state are denoted by “off” and the switches operating in chopping mode are denoted by “chopping mode”.
During phase 1, the voltage signal delivered by the device is a rising voltage ramp superposed on the DC voltage VS. During this phase, the switch M1 is in an on-state, the switches M2 and M3 are in an off-state and the switch M4 operates in chopping mode. The inductor L charges up when the switch M4 is conducting (on-state) and discharges via the diode D3 into the capacitance CP when it is off. During this phase, the voltage delivered by the device reaches VP=400V. This voltage may be obtained, without an additional voltage generator, thanks to the presence of the inductor L. This positive voltage ramp is especially used during the priming phase of the cells of the plasma panel.
Another method for obtaining this rising voltage ramp consists in making the switch M1 operate in chopping mode in order to obtain better linearity at the start of the ramp. In this operating mode, the operation of the switch M1 is synchronized with that of the switch M4. The inductor L charges up when M1 and M4 are on and discharges via the diodes D2 and D3 into the capacitor CP when they are off. Each time the switches M1 and M4 are turned off/on, the voltage across the terminals of CP increases by dVP.
During phase 2, the voltage generated is a falling edge dropping from VP to VS. This edge is obtained by turning the switch M3 on and turning the switches M1, M2 and M4 off. The transistor M3 is maintained in the on-state in order for the inductor L to come into resonance with the capacitance CP. Energy is transferred from the capacitance CP to the voltage source G via the diode D1.
During phase 3, the voltage generated is a falling ramp dropping from VS to a lower voltage, for example 0 volts if the negative terminal of the source G is connected to earth. During this phase, the switches M2 and M3 operate in chopping mode and the switches M1 and M4 are in an off-state. The switches M2 and M3 are synchronously controlled and are simultaneously in the same state. When the switches are in the on position, the voltage across the terminals of the capacitance CP lowers and energy is transferred from the capacitance CP to the inductor L and, when they are in the off position, the energy stored in L is transferred to the voltage source G via the diodes D1 and D4.
During phase 4, the voltage generated is a rising edge in resonant mode, going from the voltage V to the voltage VS. During this phase, the switch M1 is in the on position and the others are in the off position. The inductor L forms a resonant circuit with the voltage source VS, the capacitance CP and the diode D3. The switch M1 is maintained in the on position for the time needed for the voltage across the terminals of the capacitance CP to reach the desired value, in this case here the value VS. This is, for example, obtained after complete discharge of the inductor L into the capacitance CP.
Phase 5 corresponds to a rest phase in which all the switches of the device are in the off position. There is no energy transferred during this phase. The voltage VS is maintained in the capacitance CP.
During phase 6, the voltage generated is a falling edge dropping from VS to 0 volts. During this phase, the switches M2 and M3 are in the on-state and the switches M1 and M4 in the off-state. Energy is transferred from the capacitance CS into the inductor L.
Phase 7 is identical to phase 5 and corresponds to a rest phase in which all the switches of the device are in the off position. During this phase, the energy stored in the inductor L is transferred to the voltage source G via the diodes D1 and D4. The voltage across the terminals of the capacitance CP is maintained at zero.
Phase 8 is a phase during which the voltage generated is a rising voltage ramp going from 0 to VS. During this phase, the switches M1 and M4 operate in chopping mode, the other switches being in an off-state. While M1 and M4 are conducting, the inductor L is charged with energy under the voltage VS and then, after M1 and M4 are turned off, the inductor transfers the said energy into the capacitance CP via the diodes D2 and D3.
Finally, phase 9 is a rest phase identical to that of phase 7. The voltage obtained at the end of phase 8 across the terminals of the capacitance CP is maintained across the terminals of the latter.
In practice, the chopping frequency of the switches is between 100 and 500 kHz. At each chopping cycle, the voltage across the terminals of the capacitance CP varies by an amount dV. The slope of the ramp is adjusted by varying the chopping frequency and the conduction time of the switches in chopping mode.
The device of the invention has many advantages, especially the following:
| Number | Date | Country | Kind |
|---|---|---|---|
| 03/09679 | Aug 2003 | FR | national |
