BRIEF DESCRIPTION OF THE DRAWINGS
The invention is specifically explained in more detail below with reference to the drawings.
FIG. 1 shows a schematic illustration of an exemplary embodiment of a current limiting circuit; and
FIG. 2 shows a more detailed refinement of the current limiting circuit illustrated in FIG. 1.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
As shown in FIG. 1, provision is made for a charge pump circuit 4 that can be connected to a connection 10 of an input voltage and that can be used to supply an input current. This charge pump circuit 4 is connected, via the output 11, to a circuit for which it is intended but is not illustrated. In this case, the capacitor 2 depicts the capacitive load of the circuit that can be connected to the output 11. Via an AND circuit 3 a clock signal is supplied from the connection 5 to the charge pump circuit 4. The clock signal supplied clocks the charge pump circuit and correspondingly converts the input voltage that is applied to the input 10 into an output voltage. However, this output voltage is immediately present at the output only when there is no load. When there is a capacitive load, the output voltage rises in accordance with an E-function on the basis of the capacitive load, that is to say on the size of the capacitor 2. The larger the capacitive load, the larger the load current IL, as is symbolically indicated at the capacitor 2 in FIG. 1. The magnitude of the load current IL allows the voltage across the capacitor 2, which is connected between ground and the load current node K2, to rise. A capacitor 1 is likewise connected to the load current node K2.
The current that flows into the capacitor 1 is proportional to the voltage rise at the load current node K2. The difference between the load current in the capacitor 2 and the load current IL′ in the capacitor 1 corresponds to the difference between the capacitor 2 and the capacitor 1. As shown in FIG. 1, provision is made of a comparison circuit 6 that compares the current IL′ for the capacitor 1, which current is supplied to the comparison circuit 6 via the connection K1, with a reference current from a reference current source 7.
The output signal from the comparison circuit 6 is digital. The coding is such that, when the load current IL′ is higher than the reference current, the logic circuit part 3 is used to prevent the clock signal that is supplied via the connection 5. In situations in which the current IL′ is lower than the reference current from the reference current source 7, the coded signal from the comparison circuit 6 is such that the clock signal, which is supplied via the connection 5, is supplied to the charge pump circuit 4 via the logic circuit device 3.
Some explanations regarding the circuit shown in FIG. 1 are given below. In principle, the output current from the charge pump circuit 4 is composed of the current IL′ and the load current IL. If the capacitor 1 is sufficiently small in comparison with the capacitor 2, the output current I from the charge pump circuit 4 corresponds to the load current IL in the capacitor 2. The output current I from the charge pump circuit 4 is proportional to the input current flowing via the input connection 10 that means a multiple of the input current. If the input current is now intended to be limited, only the output current I that is proportional thereto needs to be limited. This means that, when the capacitor 1 is sufficiently small in comparison with the capacitor 2, the current IL must be limited. As already indicated above, the current IL is proportional to the voltage rise at the load current node K2. This voltage rise in turn gives rise to a proportional current IL′ that is again compared with the reference current. This always means that the maximum input current can be selected with the choice of reference current from the reference current source 7.
FIG. 2 shows a further refinement of the circuit arrangement shown in FIG. 1; in this case, identical parts are provided with identical reference symbols. The current through the capacitor 1 is converted, at the transistor T1, into a voltage that is in turn supplied to the gate connection of a transistor T2. The transistor T2 is connected between a current source and a ground connection. The voltage drop that is applied to the gate connection is correspondingly dropped across the output connection of the transistor T2, which is connected to the comparison circuit 6, since the current passed through the transistor T2 is proportional to the voltage that is present at the gate connection. The comparison circuit 6 compares the voltage that is supplied from the output connection of the transistor T2 with a voltage (not illustrated) that is applied to the comparison input 7′. The comparison result is supplied to the logic circuit device 3, which may be in the form of an AND circuit, for example. In accordance with the signal from the comparison circuit 6, the AND circuit 3 supplies the clock signal, which is supplied to the connection 5, to the charge pump circuit 4 or prevents the clock signal, which in turn limits the input current that is supplied to the charge pump circuit 4 via the connection 10.
Patent Application
20080042727
