Patent Application
20210109885
The subject matter herein generally relates to HDD backplane management.
A hard disk drive (HDD) backplane used in server systems requires both Non-Volatile Memory Express (NVME) HDD and Serial Advanced Technology Attachment (SATA)/Serial Attached SCSI (SAS) HDD. Currently, for cost reasons, most server systems use some interfaces to support NVME HDDs and most interfaces support SATA/SAS HDDs.
In addition, for the above traditional backplane, a separate integrated circuit (I2C) interface is usually required to implement management of the HDD backplane, which makes wiring traces complex and inflexible.
Therefore, there is room for improvement within the art.
Many aspects of the disclosure can be better understood with reference to the figure. The components in the figures are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the disclosure.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
The mainboard 10 includes a baseboard management controller (BMC) 12, a first connecter port 13, and a second connecter port 14.
The BMC 12 is electrically connected to the first connector port 13 and the second connector port 14 through a connecting line, for example, I2C bus. The BMC 12 can read information of the backplane 20 through the first connector port 13 or the second connector port 14.
The first connector port 13 may be a Slimline connector port. The first connector port 13 can be electrically connected to the backplane 20 through a PCIE signal line for data transmission.
The second connector port 14 can be a MiniSAS connector port. The second connector port 14 can be electrically connected to the backplane 20 through a SATA/SAS signal line for data transmission.
The backplane 20 includes a first HDD interface 21, a second HDD interface 22, a Complex Programmable Logic Device (CPLD) 23, an integrated circuit (I2C) selector 24, and a sensor 25.
The first HDD interface 21 corresponds to a first type of HDD, such as an NVME HDD. When the first type of HDD is inserted in the first HDD interface 21, the first HDD interface 21 outputs a first identification signal.
The second HDD interface 22 corresponds to a second type of HDD, such as a SATA/SAS HDD. When the second type of HDD is inserted in the second HDD interface 22, the second HDD interface 22 outputs a second identification signal.
The CPLD 23 is electrically connected to the first HDD interface 21 and the second HDD interface 22 for respectively receiving the first identification signal and the second identification signal. The CPLD 23 is also electrically connected to the I2C selector 24. The CPLD 23 can determine, according to the received identification signal, for example the first identification signal or the second identification signal, whether a HDD is inserted in the backplane 20 and if so a type of the HDD inserted in the backplane 20. The CPLD 23 further outputs a first controlling signal or a second controlling signal to the I2C selector 24.
For example, when the CPLD 23 receives the first identification signal, the CPLD 23 determines that a first type of HDD is inserted in the first HDD interface 21. When the CPLD 23 receives the second identification signal, the CPLD 23 determines that a second type of HDD is inserted in the second HDD interface 22. If the CPLD 23 does not receive either first or second identification signals, the CPLD 23 determines that there is no HDD inserted in the backplane 20.
The I2C selector 24 is electrically connected to the CPLD 23, the first connector port 13, the second connector port 14, and the sensor 25 via an I2C bus. The I2C selector 24 selectively turns on the first connector port 13 or the second connector port 14 according to the first controlling signal or the second controlling signal output by the CPLD 23.
For example, when the first type of HDD is inserted in the first HDD interface 21, the CPLD 23 outputs the first controlling signal to the I2C selector 24. The I2C selector 24 receives the first controlling signal and turns on the first connector port 13. When the second type of hard disk is inserted in the second HDD interface 22, the CPLD 23 outputs the second controlling signal to the I2C selector 24. Then the I2C selector 24 receives the second controlling signal and turns on the second connector port 14.
The sensor 25 is electrically connected to the I2C selector 24. The sensor 25 includes, but is not limited to, a temperature sensor and a voltage sensor. The sensor 25 stores information of the backplane 200, such as a state of the backplane 200, types of HDDs inserted in the backplane 200, a temperature of the backplane 200, a voltage of the backplane 200, and so on.
In this embodiment, when the I2C selector 24 turns on the first connector port 13 or the second connector port 14, the BMC 12 can read the backplane information stored in the sensor 25 through the first connector port 13 or the second connector port 14, and the I2C selector 24, thereby effectively managing the backplane 20 through the BMC 12.
For example, when the first HDD interface 21 receives the first type of HDD, the first HDD interface 21 outputs the first identification signal to the CPLD 23. According to the received first identification signal, the CPLD 23 determines that the first type of HDD is inserted in the first HDD interface 21 and outputs the first controlling signal to the I2C selector 24. At the same time, the I2C selector 24 receives the first controlling signal from the CPLD 23 and turns on the first connector port 13. Then the BMC 12 reads, through the first connector port 13 and the I2C selector 24, the backplane information stored in the sensor 25, thereby effectively managing the backplane 20.
When the second HDD interface 22 receives the second type of HDD, the second HDD interface 22 outputs the second identification signal to the CPLD 23. According to the received second identification signal, the CPLD 23 determines that the second type of HDD is inserted in the second HDD interface 22 and outputs the second controlling signal to the I2C selector 24. At the same time, the I2C selector 24 receives the second controlling signal from the CPLD 23 and turns on the second connector port 14. Then the BMC 12 reads, through the second connector port 14 and the I2C selector 24, the backplane information stored in the sensor 25, thereby effectively managing the backplane 20.
In addition, when an HDD is not inserted in either the first HDD interface 21 or the second HDD interface 22, the I2C selector 24 does not turn on the first connector port 13 or the second connector port 14, then the mainboard 10 does not work.
In this embodiment, the mainboard 10 further includes a Platform Control Hub (PCH) 11. The PCH 11 is electrically connected to the first connector port 13 through a clock signal line. The PCH 11 is configured to output a clock (CLK) signal to the first connector port 13. The clock signal is configured to control the first connector port 13 to perform data transmission through a PCIE signal line.
In this embodiment, the CPLD 23 is further electrically connected to the first connector port 13. When the CPLD 23 receives the first identification signal, this indicates that the first type of HDD is inserted in the first HDD interface 21. Then the CPLD 23 further outputs the first controlling signal to the first connector port 13. That is, when the CPLD 23 receives the first identification signal, the CPLD 23 outputs the first controlling signal to the first connector port 13 and the I2C selector 24.
When the first connector port 13 receives the first controlling signal, the PCH 11 outputs the clock signal, through the clock signal line, to the first connector port 13. Then the first connector port 13 performs data transmission through the PCIE signal line. If the first connector port 13 does not receive the first controlling signal, the PCH 11 does not output the clock signal and the PCH 11 is in a sleep state.
It is believed that the embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the scope of the disclosure or sacrificing all of its advantages, the examples hereinbefore described merely being illustrative embodiments of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201910964161.5 | Oct 2019 | CN | national |
