Patent Application
20250004978
This application claims priority to Taiwanese Invention patent application Ser. No. 11/212,4083, filed on Jun. 28, 2023.
The disclosure relates to a device for monitoring an inter-integrated circuit (I2C) bus, and more particularly to a device for monitoring an I2C bus that is electrically connected between a processor and an optical module.
Optical modules (e.g., an optical transceiver) have been widely used in telecommunication systems. However, the optical module often malfunctions (e.g., a logic level of a signal on a serial data (SDA) line is unable to change from logical low to logical high) due to hot swapping.
Conventionally, for troubleshooting, software supporting the inter-integrated circuit (I2C) protocol is executed to access the optical module, and to reset the optical module when it is determined that the optical module is inaccessible. However, such an approach may adversely impact operation of the telecommunication system.
Therefore, an object of the disclosure is to provide a device for monitoring an inter-integrated circuit (I2C) bus that can alleviate at least one of the drawbacks of the prior art.
According to the disclosure, the I2C bus is electrically connected between a processor and an optical module, and includes a serial data (SDA) line. The device includes a signal-edge detector, an anomaly detector and a reset-interrupt generator.
The signal-edge detector is electrically connected to the SDA line of the I2C bus, and is configured to continuously detect an SDA signal from the SDA line of the I2C bus, to generate and output a timing-start signal when detecting that a logic level of the SDA signal changes from logical high to logical low, and to generate and output a timing-reset signal when detecting that the logic level of the SDA signal changes from logical low to logical high.
The anomaly detector is electrically connected to the signal-edge detector. The anomaly detector is configured to, upon receiving the timing-start signal from the signal-edge detector, start to time a timing duration, and determine whether the timing duration reaches a preset time duration. The anomaly detector is configured to generate and output an error signal when it is determined that the timing duration reaches the preset time duration, and upon receiving the timing-reset signal from the signal-edge detector, to reset the timing duration to zero.
The reset-interrupt generator is electrically connected to the anomaly detector, and is adapted to be electrically connected to the processor and the optical module. The reset-interrupt generator is configured to in response to receipt of the error signal from the anomaly detector, perform one of a step of outputting an interrupt signal to the processor to allow the processor to remove an abnormal state, and a step of outputting a pin-reset signal to the optical module to allow the optical module to reset a pin that is electrically connected to the SDA line of the I2C bus.
Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment(s) with reference to the accompanying drawings. It is noted that various features may not be drawn to scale.
Referring to
A brief introduction to a conventional I2C protocol is provided in the following. A logic level of an SDA signal on the SDA line and a logic level of an SCL signal on the SCL line should be both maintained at logical high when no data is transmitted via the I2C bus. During utilizing the SDA line for data transmission (including data reading and data writing), no matter which kind of I2C format is used, the data transmission begins with a predefined start condition (where each of the SDA signal and the SCL signal is at a specific logic level) followed by data that is to be transmitted, and ends with a predefined stop condition (where the logic level of the SDA signal returns to logical high). That is to say, a condition that the logic level the SDA signal is always kept at logical low without returning to logical high during data transmission by the I2C bus will be regarded as abnormal.
The processor 200 may be a central processing unit (CPU), a microprocessor, a micro control unit (MCU), a system on a chip (SoC), or any circuit configurable/programmable in a software manner and/or hardware manner to implement functionalities discussed in this disclosure.
The optical module 300 may be an optical transceiver, but is not limited thereto.
As shown in
The signal-edge detector 1 is electrically connected to the SDA line of the I2C bus. The signal-edge detector 1 is configured to continuously detect the SDA signal from the SDA line of the I2C bus, generate and output a timing-start signal when detecting that the logic level of the SDA signal changes from logical high to logical low, and generate and output a timing-reset signal when detecting that the logic level of the SDA signal changes from logical low to logical high.
The anomaly detector 2 is electrically connected to the signal-edge detector 1 and the reset-interrupt generator 3. Upon receiving the timing-start signal from the signal-edge detector 1, the anomaly detector 2 is configured to start to time a timing duration, and to determine whether the timing duration reaches a preset time duration. The anomaly detector 2 is further configured to generate and output an error signal to the reset-interrupt generator 3 when it is determined that the timing duration reaches the preset time duration. On the other hand, upon receiving the timing-reset signal from the signal-edge detector 1, the anomaly detector 2 is configured to reset the timing duration to zero.
Specifically, the anomaly detector 2 includes a counter 21 and a determining module 22.
The counter 21 is electrically connected to the signal-edge detector 1. Upon receiving the timing-start signal from the signal-edge detector 1, the counter 21 is configured to count a counted value starting from zero based on a reference clock signal (which is generated by the device 100, i.e., the CPLD, based on an external clock source), and generate and output a timeout signal every time overflow occurs in the counter 21 during counting. In addition, upon receiving the timing-reset signal from the signal-edge detector 1, the counter 21 is configured to reset the counted value to zero.
The determining module 22 is electrically connected to the signal-edge detector 1, the counter 21 and the reset-interrupt generator 3. The determining module 22 is configured to receive the timeout signal from the counter 21, to count a number of accumulative times of receiving the timeout signal from the counter 21, and to determine whether the timing duration reaches the preset time duration by determining whether the number of accumulative times of receiving the timeout signal from the counter 21 has reached a preset number. The determining module 22 is configured to generate and output the error signal to the reset-interrupt generator 3 when it is determined that the number of accumulative times of receiving the timeout signal from the counter 21 has reached the preset number. Upon receiving the timing-reset signal from the signal-edge detector 1, the determining module 22 is configured to reset the number of accumulative times of receiving the timeout signal to zero. It is worth to note that the anomaly detector 2 resets the timing duration to zero by resetting the number of accumulative times of receiving the timeout signal to zero and resetting the counted value to zero.
It is worth to note that the preset time duration is related to the preset number, a period of the reference clock signal and a maximum setting of the counter 21. In particular, the preset time duration is a product of the preset number, the period of the reference clock signal and the maximum setting of the counter 21.
In a scenario where the preset number is 9, the maximum setting of the counter 21 (which is a 8-bit counter) is 256 and the period of the reference clock signal is 1 ms, the preset time duration will be equal to 2304 ms, i.e., 1×256×9=2304.
In general, when the SDA line of the I2C bus is being used to transmit data (including data reading and data writing), the logic level of the SDA signal frequently changes between logical high and logical low during data transmission. Therefore, the counter 21 starts to count the counted value upon receiving the timing-start signal (the logic level changing from logical high to logical low), and usually before overflow occurs, and then resets the counted value to zero upon receiving the timing-reset signal (the logic level changing from logical low to logical high), without generating and outputting the timeout signal. In this embodiment, a condition that the logic level of the SDA signal has been kept at logical low for 2304 ms without returning to logical high during data transmission by the I2C bus is regarded as abnormal, and thus the error signal is generated and outputted to the reset-interrupt generator 3, accordingly.
The reset-interrupt generator 3 is adapted to be electrically connected to the processor 200 and the optical module 300. The reset-interrupt generator 3 is configured to in response to receipt of the error signal from the determining module 22 of the anomaly detector 2, perform one of a step of outputting an interrupt signal to the processor 200 to allow the processor 200 to remove an abnormal state, and a step of outputting a pin-reset signal to the optical module 300 to allow the optical module 300 to reset a pin that is electrically connected to the SDA line of the I2C bus. For example, in response to receipt of the interrupt signal from the reset-interrupt generator 3, the processor 200 would execute relevant software programs for removing the abnormal state. More specifically, in order to remove the abnormal state, the processor 200 would perform a procedure according to settings of an operating system run by the processor 200 to reset the optical module 300, to output a message for notifying a user to check the optical module 300, or to enable the device 100 (i.e., the CPLD) to reset the optical module 300. In response to receipt of the pin-reset signal from the reset-interrupt generator 3, the optical module 300 would be reset to revert the current settings thereof to default settings. In addition, a pull-up resistor would be electrically connected to the SDA line of the I2C bus to raise the logical level of the SDA signal to logical high.
To sum up, the device 100 according to the disclosure monitors the I2C bus connected between the processor 200 and the optical module 300 in real time, and determines whether an error occurs on the I2C bus by determining whether the SDA signal of the SDA line of the I2C bus has been at the low logical level for the preset time duration. When it is determined that an error occurs on the I2C bus, the device 100 outputs the interrupt signal to the processor 200 or outputs the pin-reset signal to the optical module 300 so as to remove the abnormal state in time. In this way, the I2C bus may be monitored without disturbing normal operations of the processor 200 and the optical module 300.
In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiment(s). It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects; such does not mean that every one of these features needs to be practiced with the presence of all the other features. In other words, in any described embodiment, when implementation of one or more features or specific details does not affect implementation of another one or more features or specific details, said one or more features may be singled out and practiced alone without said another one or more features or specific details. It should be further noted that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure.
While the disclosure has been described in connection with what is (are) considered the exemplary embodiment(s), it is understood that this disclosure is not limited to the disclosed embodiment(s) but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112124083 | Jun 2023 | TW | national |
