Number | Date | Country | Kind |
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9002665 | Aug 1990 | SEX |
This application is a continuation-in-part of U.S. patent application Ser. No. 07/745,411, filed on Aug. 15, 1991, now abandoned, which application is incorporated here by reference.
Number | Name | Date | Kind |
---|---|---|---|
3859638 | Hume, Jr. | Jan 1975 | |
4197582 | Johnston et al. | Apr 1980 | |
4288865 | Graham | Sep 1981 | |
4384350 | Lee et al. | May 1983 | |
4467275 | Maeda et al. | Aug 1984 | |
4528505 | Peterson | Jul 1985 | |
4841232 | Graham et al. | Jun 1989 | |
4860288 | Teske et al. | Aug 1989 | |
4872169 | Whetsel, Jr. | Oct 1989 | |
4875003 | Burke | Oct 1989 | |
4879717 | Sauerwald et al. | Nov 1989 | |
4910455 | Nadd | Mar 1990 | |
4963824 | Hsieh et al. | Oct 1990 | |
4999575 | Germer | Mar 1991 | |
5057774 | Verhelst et al. | Oct 1991 | |
5063304 | Iyengar | Nov 1991 | |
5122920 | Pease | Jun 1992 | |
5285151 | Akama et al. | Feb 1994 |
Number | Date | Country |
---|---|---|
358376 | Mar 1990 | EPX |
Entry |
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"Strategies for Testing VLSI Boards Using Boundary Scan", P. Hansen, Electronic Engineering, vol. 61, No. 755, pp. 103, 105-106, 109; 111, Nov. 1989. |
"Dividing Up a PC Board With Boundary Scan Extends Chip-Oriented, Design-For-Testability Systems to PC Boards", Bottom-Up Techniques Propel Board Testability, Ellis et al., Electronic Design, vol. 38, No. 10, pp. 57-60, 62, 64, May 24, 1990. |
"Testing Multiple Power Connections with Boundary Scan", Dirk van de Lagemaat, IEEE, pp. 127-130, 1989. |
"Elimination of Bus Contention During Chip-to-Chip Connectivity Test", IBM Technical Disclosure Bulletin, vol. 32, No. 6A, Nov., 1989. |
"Self Test Method for Secure LSSD Chip", Research Disclosure, p. 336, May, 1989. |
"Circuit Board Tester", Research Disclosure, p. 244, Apr., 1987. |
Number | Date | Country | |
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Parent | 745411 | Aug 1991 |