Patent Application
20140347064
The present disclosure relates to a fan testing device.
A fan testing device has a first connector to connect to a motherboard, and a second connector to connect to a fan.
Many aspects of the present disclosure can be better understood with reference to the following drawing. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure.
The FIGURE is a circuit diagram of an embodiment of a fan testing device of the present disclosure.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawing is not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like.
The FIGURE shows an embodiment of a fan test device 10 of the present disclosure.
The fan test device 10 can comprise a first connection module 20 to connect to a fan, a second connection module 30 to connect to a motherboard, a control chip U1, and an alarm module 40. In the embodiment, the fan test device 10 can notify a user whether the first connection module 20 and the second connection module 30 are coupled incorrectly to the motherboard and the fan, respectively.
The first connection module 20 can comprise a first connector J1, a first resistor R1, a second resistor R2, a third resistor R3, and a capacitor C1. The first connector J1 can be coupled to the fan. A power pin 1 of the first connector J1 is coupled to a first power input terminal P5V through the first resistor R1. A speed pin 2 of the first connector J1 is coupled to the first power input terminal P5V through the second resistor R2. The speed pin 2 of the first connector J1 is also grounded through the third resistor and the capacitor C1 in that order. A node between the third resistor R3 and the capacitor C1 is coupled to a speed pin 1 of the control chip U1. A ground pin 3 of the first connector J1 is grounded. A signal pin 4 of the first connector J1 is coupled to a control pin 2 of the control chip U1. The signal pin 4 of the first connector J1 is further coupled to a power source (not shown) that outputs a constant high-level signal, such as logic 1, to the signal pin 4 of the first connector J1.
The second connection module 30 can comprise a second connector J2, a fourth resistor R4, a fifth resistor R5, a diode D1, a fuse FS, and an electronic switch Q1. The second connector J2 can be coupled to the motherboard. A signal pin 1 of the second connector J2 is coupled to a signal pin 3 of the control chip U1. A power pin 2 of the second connector J2 is coupled to a second power input terminal P12V_A. The power pin 2 of the second connector J2 is also coupled to an anode of the diode D1 through the fuse FS. A cathode of the diode D1 is coupled to a third power input terminal P12V. An alarm pin 3 of the second connector J2 is coupled to a second terminal of the electronic switch Q1. A first terminal of the electronic switch Q1 is grounded through the fifth resistor R5. The first terminal of the electronic switch Q1 is also coupled to an alarm pin 4 of the control chip U1 through the fourth resistor R4. A third terminal of the electronic switch Q1 is grounded. A ground pin 4 of the second connector J2 is grounded.
The alarm module 40 can comprise a sixth resistor R6 and a light-emitting diode (LED) D2. A cathode of the LED D2 is coupled to an indicating pin 5 of the control chip U1 through the sixth resistor R6. An anode of the LED D2 is coupled to the first power input terminal PSV.
When the first connector J1 is coupled to the motherboard while the second connector J2 is coupled to the fan, the signal pin 4 of the first connector J1 is coupled to ground of the motherboard, causing the signal pin 4 of the first connector J1 to be grounded, and further causing the control pin 2 of the control chip U1 to be at a low level. The signal pin 1 of the second connector J2 is coupled to the fan, causing the signal pin 1 of the second connector J2 to be at a low level and further causing the signal pin 3 of the control chip U1 to be at a low level.
The alarm module 40 alerts when the alarm module 40 receives a first signal from the control chip U1. In the embodiment, the control chip U1 outputs a low-level signal, such as logic 0, through the indicating pin 5 when the control pin 2 and the signal pin 3 of the control chip U1 are both at a low level, causing the LED D2 to light up to indicate that the connection between the first connector J1 and the motherboard, and the connection between the second connector J2 and the fan, are incorrect.
When the first connector J1 is coupled to the fan while the second connector J2 is coupled to the motherboard, the motherboard outputs a high-level signal to the signal pin 1 of the second connector J2, causing the signal pin 3 of the control chip U1 to be at a high level. The control pin 2 of the control chip U1 receives the constant high-level signal from the signal pin 4 of the first connector J1. The control chip U1 outputs a high-level signal through the indicating pin 5 when the control pin 2 and the signal pin 3 of the control chip U1 are both at a high level, causing the LED D2 to turn off. The fan outputs a speed signal through the speed pin 2 of the first connector J1, and the control chip U1 receives the speed signal through the speed pin 1 of the control chip U1. When the control chip U1 determines that a speed of the fan is abnormal, the control chip U1 outputs a high-level signal to the first terminal of the electronic switch Q1 through the alarm pin 4 of the control chip U1, causing the electronic switch Q1 to turn on. When the electronic switch Q1 is turned on, the alarm pin 3 of the second connector J2 is grounded. When the alarm pin 3 of the second connector J2 is grounded, the motherboard receives a low-level signal from the alarm pin 3 of the second connector J2 and determines that the speed of the fan is abnormal. When the control chip U1 determines that the speed of the fan is normal, the control chip U1 outputs a low-level signal to the first terminal of the electronic switch Q1, causing the electronic switch Q1 to turn off. The motherboard receives a high level signal through the alarm pin 3 of the second connector J2 and determines that the speed of the fan is normal.
In the embodiment, the electronic switch Q1 is an NPN transistor, but can be any other suitable transistor.
The fan test device 10 operates normally when the first connector J1 is coupled to the fan, and the second connector J2 is coupled to the motherboard, and notifies a user when the first connector J1 and the second connector J2 are coupled to the motherboard and the fan, respectively.
While the disclosure has been described by way of examples, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013101986583 | May 2013 | CN | national |
