Patent Application
20210359185
The present disclosure relates generally to through glass vias. More particularly, it relates to laser formed through glass vias for electronic devices.
Micro light emitting diode (microLED) displays may have a higher brightness and a higher contrast ratio compared to liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays. There may be other benefits of microLED displays depending upon the specific application. To enable high resolution and large area displays, there is interest in fabricating microLED displays with active matrix backplanes based on Low Temperature PolySilicon (LTPS) or oxide thin-film transistors (TFTs). A display configuration may include top emitting microLED panels with driver boards located on the display backside. If these display panels are used in large area tiled display applications, electrical interconnections between the two substrate surfaces should be fabricated in a way that enables close tile-to-tile spacing (e.g., less than 100 micrometers spacing between tiles).
Metalized vias in a glass substrate may be used to electrically interconnect components on a first side of the glass substrate to components on a second side of the glass substrate. There are multiple methods for fabricating vias in glass substrates. These methods, however, are mainly focused on the fabrication of high quality vias, at high density, in thin glass (e.g., less than 0.3 millimeters), and on small substrate sizes (e.g., less than 300 millimeters). One method for fabricating vias utilizes a laser damage and multi-hour glass etch process. A via fabricated using the laser damage and multi-hour glass etch process has nearly vertical sidewalls. To enable utilization of existing large generation size display glass processing, the via should be fabricated in glass substrates having thicknesses greater than about 0.3 millimeters. Limiting the via aspect ratio to an approximate value of 5:1, the via diameter would be about 60 micrometers for a straight sidewall structure. This 60 micrometers diameter would take up significant space within a pixel layout. In addition, using via fabrication processes that have been optimized for interposer or other applications results in an over-designed via fabricated in a higher cost process. Lasers may be used to create through glass vias or micro-holes in glass. Direct laser ablation based micro-hole drilling, however, creates undesirable debris and also a rim around the micro-hole.
Some embodiments of the present disclosure relate to a device. The device includes a glass substrate, a plurality of electronic components, a metallization layer, and a plurality of vias. The plurality of electronic components are on a first surface of the glass substrate. The metallization layer is on a second surface of the glass substrate opposite to the first surface. The plurality of vias extend through the glass substrate. At least one via is in electrical communication with an electronic component and the metallization layer. At least one via includes a first diameter at the first surface and a second diameter greater than the first diameter at the second surface such that a ratio of the second diameter to the first diameter is greater than 1.5:1.
Yet other embodiments of the present disclosure relate to a method for fabricating vias. The method includes applying a first gel layer over a first surface of a glass substrate. The method includes laser ablating the glass substrate to form a via hole through the glass substrate such that debris from the laser ablating is trapped in the first gel layer. The method includes removing the first gel layer from the first surface.
Yet other embodiments of the present disclosure relate to material for collecting debris due to laser ablation. The material includes a first solution and a second solution. The first solution includes 5% to 10% PolyVinyl Alcohol (PVA) in water by weight. The second solution includes 1% to 10% Sodium Tetraborate in water by weight.
Yet other embodiments of the present disclosure relate to a device. The device includes a glass substrate, a plurality of electronic components, a metallization layer, and a plurality of vias. The plurality of electronic components are on a first surface of the glass substrate. The metallization layer is on a second surface of the glass substrate opposite to the first surface. The plurality of vias extend through the glass substrate. At least one via is in electrical communication with an electronic component and the metallization layer. At least one via is at least partially filled with an insulating, conductive, or semi-conductive material.
The methods and materials disclosed herein may be used to form devices including substantially debrisless and substantially rimless laser-formed through glass vias. Via holes may be fabricated quickly and cost effectively using laser ablation and a gel layer to collect debris and to prevent rim formation around the via holes. Accordingly, the via holes may be formed without the use of toxic chemicals typically used for vias formed using a laser damage and etching process. Via holes of different shapes and sizes may be formed in the same substrate. Via holes of a wide range of taper angles may also be formed. In addition, the via holes may be formed before or after the fabrication of other components (e.g., electronic components) on the substrate. The gel layer used to collect the debris and to minimize rim formation during the laser ablating may be reused.
Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understanding the nature and character of the claims. The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment(s), and together with the description serve to explain principles and operation of the various embodiments.
Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Ranges can be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, another embodiment includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
Directional terms as used herein—for example up, down, right, left, front, back, top, bottom, vertical, horizontal—are made only with reference to the figures as drawn and are not intended to imply absolute orientation.
Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order, nor that with any apparatus, specific orientations be required. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or that any apparatus claim does not actually recite an order or orientation to individual components, or it is not otherwise specifically stated in the claims or description that the steps are to be limited to a specific order, or that a specific order or orientation to components of an apparatus is not recited, it is in no way intended that an order or orientation be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps, operational flow, order of components, or orientation of components; plain meaning derived from grammatical organization or punctuation, and; the number or type of embodiments described in the specification.
As used herein, the singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a” component includes aspects having two or more such components, unless the context clearly indicates otherwise.
Compared to interposer or other applications, in display applications the substrates may be larger, the glass may be thicker, relatively few vias may be used, and some via requirements may be relaxed. For example, for glass substrates with edge dimensions greater than about 100, 200, 300, 400, 500, 700, 1000, or 2000 millimeters; the glass thickness may be less than about 2, 1, 0.7, 0.6, 0.5, 0.4, or 0.3 millimeters. These combinations of glass substrate edge dimensions and glass thicknesses may increase restrictions on the via diameter and increase the challenge of placement within a pixel layout. Although the substrate is described as glass, in certain exemplary embodiments the substrate may be a ceramic or glass-ceramic material. In other embodiments, the substrate may include multiple layers of substantially similar or different materials.
Accordingly, disclosed herein is a glass electronics substrate, which may be used for a display. As display resolution increases, there is less area within a pixel to accommodate emitters, TFTs, conductor lines, and other components. Because of this, the size of the components within a pixel should be minimized. In addition, for top emission tiled displays, an electrical interconnection may be used between the substrate top surface and back surface. Using top emitting microLED displays as an example, the microLEDs and TFT matrix (e.g., LTPS, oxide, aSi, or organic semiconductor) on top of the glass substrate should be electrically interconnected with the driver board located under the glass substrate. Electrical vias may provide this interconnection ability. These vias should have a minimum size and a highly registered placement to fit within the crowded layout of a high resolution display pixel. A typical pixel may have a less than about 1 millimeter or less than about 700, 500, 400, 300, or 200 micrometers pixel pitch in either the vertical or horizontal directions. Although a TFT active matrix is specifically mentioned, the need for a small diameter high-registration via also applies to passive matrix and direct-driver configurations. Display applications or other applications using the vias and via fabrication processes disclosed herein result in faster throughput and lower cost than previous fabrication processes. Although microLED displays are discussed as an example, other applications may include liquid crystal displays, OLED displays, and non-display devices.
Referring now to
Glass substrate 102 may, for example, have a thickness between the first surface 108 and the second surface 110 of about 0.3 millimeters or greater. Each of the vias 106 may include linear sidewalls 116 between the first surface 108 and the second surface 110. Each of the vias 106 may include a conformal conductive layer 114 (e.g., Cu) on sidewalls 116 of the via. The conformal conductive layer 114 may form a cone shape that is pinched off at first surface 108. The conformal conductive layer 114 may enable compatibility with high temperature device processing by reducing the effects of the differential thermal expansion of the conductive material 114 and the glass substrate 102. In other embodiments, each via 106 may be fully filled with a conductive material.
The conformal conductive layer 114 of each via 106 may be able to survive higher temperature excursions without the failures observed with vias fully filled with a conductive material. For example, fully filled vias may suffer issues of stress cracking in the glass around the via and pistoning of the conductive material out of the via. This is due to the thermal expansion mismatch between the conductive material and the surrounding glass. If the via is filled conformally and pinched off at one end, the via may be able to survive the thermal excursions, for example greater than about 300, 400, 500, or 600 degrees Celsius. The conformal conductive layer 114 of each via 106 may have a thickness less than about 50, 20, 10, 5, 2, or 1 micrometers on the sidewalls 116 of each via.
In certain exemplary embodiments, each of the vias 106 may be filled with a material 118 within the conformal conductive layer 114 on the sidewalls 116 of each via. Whether insulating, conductive, or semi-conductive, the material 118 may also have a thermal expansion coefficient greater than about 20, 15, 10, or 5 parts per million per degree Celsius. The material 118 filling each via 106 may minimize process contamination, provide mechanical support, or provide other effects. For example, a sol-gel material may be used for material 118. The sol-gel material may be compatible with LTPS, oxide, aSi, or organic TFT processing. The sol-gel material may also survive thermal excursions greater than about 300, 400, 500, or 600 degrees Celsius. In certain exemplary embodiments, the material 118 may not completely fill the via as shown in
The first diameter 202a or 202b may be on a device side (i.e., first surface 108 of glass substrate 102) and, for example, be less than about 100, 50, 40, 30, 20, or 10 micrometers. In contrast, the second diameter 204a or 204b on the second side 110 of the glass substrate 110 may, for example, have a diameter of greater than about 50, 100, 150, or 200 micrometers. In certain embodiments, the ratio of the second diameters 204a and 204b to the first diameters 202a and 202b, respectively, may, for example, be greater than about 1.5:1, 2:1, 5:1, 10:1, or 15:1. The ratio of the thickness of glass substrate 102 to the first diameter 202a or 202b may, for example, be greater than about 2:1, 5:1, 10:1, 20:1, or 50:1. The via shape shown in
The smaller first diameter 202a and 202b at the first surface 108 of the glass substrate 102 enables efficient integration within a crowded pixel layout of a high resolution display. The larger second diameter 204a and 204b at the second surface 110 of the glass substrate 102 enables efficient metallization and relaxation of backside patterning design rules. In general, the structure of vias 200a and 200b allows for the use of smaller via dimensions on the side of the glass substrate requiring precise pixel layout and integration while allowing for larger via dimensions on the side of the glass substrate that benefits more from relaxation of alignment tolerances. Some device designs for display or non-display applications may have the most efficient layouts with the small diameter of the vias on the same substrate surface. Other designs may benefit from having some vias with the smaller diameters on one substrate surface and other vias with the small diameter on the other substrate surface.
Via holes 200a and 200b may be placed, for example, less than about 100, 50, 20, or 10 micrometers away from electronic components other than components used for purely electrical connections. For example, the electronic components may include TFTs, capacitors, inductors, integrated circuits (ICs), or other components. The smaller first diameter 202a and 202b enables this close proximity to the other components.
In certain exemplary embodiments, both via holes 200a and 200b having different dimensions may be formed in a single glass substrate 102, such as in device 100 of
The curved sidewalls 116b may be beneficial during the metallization and via fill process to force bridging of the conductive material to occur at the smaller first diameter 302a and 302b surface. This bridging may naturally create a via pinched at the first surface 108 of the glass substrate 102. The dimensions of first diameters 302a and 302b and second diameters 304a and 304b may be similar to the dimensions of first diameters 202a and 202b and second diameters 204a and 204b, respectively, as previously described with reference to
In both gel layer application methods (i.e., spraying and spin coating), a two-step application of materials may be used. For example, in a first step, a layer of a PolyVinyl Alcohol (PVA) solution may be applied to a thickness greater than about 0.5 millimeters to cover the glass substrate. In a second step, a Sodium tetraborate solution may be misted over the PVA. In certain exemplary embodiments, applying gel layer 400 may include applying a layer of a first solution of about 5% to 10% PVA in water by weight and misting a second solution of about 1% to 10% Sodium Tetraborate in water by weight over the layer of the first solution. After the application of gel layer 400, the glass substrate 102 is ready to be laser ablated. Alternatively, if a certain gel layer 400 thickness is desired after application, water may be allowed to evaporate out of the solution to thin the gel layer prior to laser ablation. Forming the gel layer 400 on the glass substrate 102 ensures that there are no air gaps between the gel layer and the glass substrate. In addition, the formation of the gel layer 400 on the glass substrate 102 allows for variable surface conditions. While traditional protective layers need to be applied to a flat surface, gel layer 400 may be applied over all existing structures on the glass substrate 102 such as electronic components or physical features of the glass as will be described in more detail below with reference to
If a laser is pulsed and there is no gel layer on the glass substrate, the ablated material reforms on the surface of the glass substrate all around the via hole and even up to millimeters away. The debris may be hot enough such that the debris may attach to the glass substrate surface and become a part of the glass. This debris may be removed by polishing or etching. When a gel layer 400 is on the surface of the glass substrate 102 as depicted in
When the laser 404 is introduced to the glass substrate 102 without a gel layer and ablates the glass substrate, the laser also melts the surrounding material away from the middle of the via hole. Internally, this melting causes a localized compaction of the glass substrate and towards the openings of the via hole the material is pushed up and away from the glass substrate forming a rim that can be micrometers in scale. With the addition of the gel layer 400, the rim formation does not occur on the first surface 108 of the glass substrate 102 or occurs at a much reduced level. This helps maintain the surface quality of the glass substrate 102 so that the vias can be reached for a multitude of uses without having a barrier due to the rim.
The laser ablation may be performed with a single laser 404 (e.g., CO2 laser) to create the tapered structure without the need for significant etching. An etch process may still be used as a clean-up step to complete the via formation if desired. The elimination of the significant etching step drastically reduces the overall process time and cost associated with the via formation, especially for display applications that may have fewer vias per substrate compared to other applications. Elimination or substantial reduction of the via etch step while incurring a small increase in laser processing per via is a trade-off that increases the overall process throughput.
The via holes 402 may be formed in the glass substrate 102 before substantial electronic processing, at the end of the device fabrication process, or in the middle of the device fabrication process. Location of the via formation process depends upon the specific process step requirements that may occur before or after via formation. As part of the processing, the temporary protective gel layer 400 may be applied at any step before via hole formation and removed at any step after via hole formation. In addition, the via hole formation can create a blind via hole structure. In this case, the via hole is mostly created and then the final opening or connection on the smaller diameter side is formed at a later step. This final opening may be created by an etch process. If it is controlled by a photolithographically patterned etch process, the location of the smaller diameter via opening may be very precisely controlled to enable integration within a pixel. This small etched opening may also be created before the laser ablation process.
Laser 404 may, for example, include various mirrors and a lens (e.g., 1, 2, or 4 inch lens). Laser 404 may form via holes 402 having an upper diameter (i.e., at second surface 110) between about 150 and 250 micrometers and a lower diameter (i.e., at first surface 108) between about 10 and 150 micrometers. In certain exemplary embodiments, an xyz stage (not shown) may be used to move glass substrate 102 relative to laser 404. Laser 404, for example, may have a 5.5, 9.3, or 10.6 micrometers wavelength. Laser 404 may, for example, be a 30 watt laser to provide hundreds of 50 microsecond pulses in a 200 microsecond waveform to form each via hole 402. Laser 404 may also be an 80 watt laser to provide 27 microsecond pulses in a 280 microsecond waveform to form each via hole 402. In other embodiments, other laser powers and waveforms may be used to form each via hole 402 by providing a pulse train to ablate through holes in about 15 milliseconds or less. The laser beam is not hindered by the gel layer 400.
Applying each gel layer 500a and 500b may, for example, include applying a layer of a first solution of 5% to 10% PolyVinyl Alcohol (PVA) in water by weight and misting a second solution of 1% to 10% Sodium Tetraborate in water by weight over the layer of the first solution for each gel layer 500a and 500b. The first gel layer 500a and the second gel layer 500b may, for example, both be applied to a thickness of about 0.5 millimeters or greater. The gel layers 500a and 500b provide a temporary protective coating on first surface 108 and second surface 110 of the glass substrate 102 to protect the first surface 108 and the second surface 110, respectively, during a laser ablation process (
The composition of material 700 is inexpensive and toxic-free. Since the material 700 is a non-newtonian solid, the material may be peeled off the substrate after use. By being made of an ion and polymer that are both soluble in water, material 700 also allows for easy cleaning if there is any residue left on the substrate after the gel is removed by washing with water.
It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments of the present disclosure without departing from the spirit and scope of the disclosure. Thus it is intended that the present disclosure cover such modifications and variations provided they come within the scope of the appended claims and their equivalents.
This application claims the benefit of priority under 35 U.S.C. § 119 of U.S. Provisional Application Ser. No. 62/876,131 filed on Jul. 19, 2019 and U.S. Provisional Application Ser. No. 62/747,959 filed on Oct. 19, 2018, the content of each are relied upon and incorporated herein by reference in their entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2019/055343 | 10/9/2019 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62876131 | Jul 2019 | US | |
| 62747959 | Oct 2018 | US |
