Embodiments disclosed herein relate in general to devices using liquid metal (LM) drops and in particular to microelectronic or MEMS devices incorporating miniaturized LM drops.
The use of liquid metals in various electrical or electromechanical devices is known. Larger devices using liquid metals include relays (e.g. mercury relays) and switches. Small LM volumes (“drops”) are also known for their use in micro-electro-mechanical system (MEMS) devices, for example for RF and other switching and cooling devices. However, in order to use LM components, such devices have added structural features (e.g. layers) which are not needed in regular MEMS devices. In addition, the incorporation of LM drops in microelectronic devices requires added layers and technological process steps.
There is therefore a need for, and it would be advantageous to have devices for switching or tuning of an electrical circuit based on standard microelectronics and/or MEMS technologies which incorporate LM drops.
In various embodiments, there are provided devices for switching or tuning of an electrical circuit having a liquid metal drop enclosed and sealed inside a small cavity. The term “drop” is used to describe an entity having a volume made of LM, and is not meant to be limiting to a particular shape or size. In some embodiments, the drop may have a very small (miniaturized) volume, on the order of a few cubic micrometers. In other embodiments, the drop may have a volume of tens of cubic micrometers or more. The drop may be enclosed and sealed in a cavity of slightly larger volume (referred to herein as “sealed cavity” or “sealed volume”). In some embodiments where the drop has such a miniaturized volume, the cavity sealing it may be formed in a microelectronic or a MEMS device (including glass based MEMS), or in a microelectronics based interposer for 2.5D and/or 3D multiple IC integration. In such embodiments, the small total thickness of microelectronic layered structure prepared by planar technologies (generally less than 10 micrometer) may restrict the LM drop size.
In some embodiments, the sealed volume is defined at least partially by microelectronics (e.g. VLSI CMOS) device layers. In other words, its boundaries are defined by layers or features of a microelectronics process or technology (such as VLSI-CMOS). The term “CMOS” is used henceforth as an exemplary (but in no way limiting) term for the processes or technologies (e.g. RF-CMOS, Silicon, Glass, GaAs or GaN), to simplify the description. In other embodiments, the sealed cavity may be formed by covering and sealing a LM drop formed on a flat surface. In yet other embodiments, the sealed volume may be defined by MEMS layers (e.g. between bonded wafers or inside deep silicon trenches)
The LM drop may physically open or close a RF transmission line and therefore open or close an electrical circuit by a force applied to the LM drop, which force creates a change in the liquid metal shape and dimensions. The electrical circuit under open or close states may be a RF circuit but could also be a DC, AC or THz circuit. The switching may occur directly between open and close states or through any number of intermediate states.
Non-limiting embodiments are herein described, by way of example only, with reference to the accompanying drawings, wherein:
Device 100 includes a LM drop 102 located inside a sealed cavity 104. As shown (
The cavity is sealed by a CMOS sealing layer 116 (i.e., in this embodiment, cavity top plane 104d is covered by sealing layer 116). Thus, unlike known LM-containing sealed cavities which are either defined by glass tubes or by two wafers, a sealed cavity disclosed herein is defined from all sides either partially or fully by CMOS (microelectronics) layers. Methods and processes for forming a LM drop inside a sealed cavity in microelectronics layers are described in detail in co-pending PCT application PCT/IB2012/XXXXXX by the same inventors, which is incorporated herein by reference. In an embodiment and as described therein, the LM drop is an alloy of about (by weight) 68.5% gallium (Ga), 21.5% indium (In) and 10% tin (Sn). As described in PCT/IB2012/XXXXXX, the Ga—In—Sn alloy may have small amounts of added metals which affect the formation of the LM drop. In some embodiments, the amounts may total less than 1% by weight.
Device 100 further includes a first RF transmission (“signal”) line 118 which extends between a first end 120 and a first contact point 122 through a via 118a and a second RF transmission (“signal”) line 124 which extends between a second end 126 and a second contact point 128 through a via 124a. As shown in section A-A in
The substrate (e.g. Si) areas below the CMOS layered structure are isolated by N or P well (tap) guard rings to isolate the RF transmission lines 118 and 124. The guard rings may be single, double or triple ground rings, and may be formed using design rules familiar in the CMOS technology. In an embodiment, a guard ring 150 may be located under a contact area, therefore isolating for example areas 158 and 160 located respectively under RF transmission line 118 and RF transmission line 124. However, the guard ring location may be anywhere in the design in order to improve the isolation between different RF elements of the switch. Other guard rings 152, 154156 may also be located around the entire switch area (152, 154) and underneath it (156) in order to isolate it from the surrounding signals in the CMOS circuits.
The contact metals may be specifically chosen not to react with the LM. For example, tungsten (W) is both CMOS compatible and does not react with a Ga—In—Sn alloy or with mercury (Hg). Tungsten can therefore serve as a contact metal in a device such as device 100.
The dielectric layers in contact with the LM drop are part of the VLSI-CMOS dielectric layers. An exemplary CMOS compatible dielectric layer material which does not react with a Ga—In—Sn or Hg LM drop is SOG (Spin on Glass). Another exemplary CMOS compatible dielectric material which does not react with a Ga—In—Sn LM or with Hg is alumina. Alumina can also be deposited over all the internal surfaces of the cavity before the LM drop is formed. Alumina creates a high wetting angle with the LM drop (needed for lower operation voltage), has high breakdown voltage and high dielectric constant.
In some embodiments, first type “wetting” layers may be formed inside the sealed volume to increase the wetting angle between the LM drop and the layers it is in contact with. Such first type wetting layers may be needed for lower operation voltage. They include for example self assembled monolayers (SAM) of Alkoxy-silanes, Chloro-silanes or Flouro-silanes. In some embodiments, second type wetting layers may be formed inside the sealed volume to hold the drop in location in order to prevent its movement under acceleration, shock or vibration, by fixing drop surfaces not intended to be moved to the inner side of the cavity. Such layers include for example SAM of 11-hydroxy-1-undecanethiol, poly(dimethyl siloxane). The wetting layers may be patterned inside the sealed cavity
In use, in the “open” state,
Alternatively, an electrostatic force can be applied between the drop and an electrode spaced apart (for example a via). This will cause the drop to move as a result not of EWOD but of direct electrostatic force action.
Advantageously, in microelectronics devices using LM drops disclosed herein, the operation of the LM drop by EWOD may be effected from all directions (top, bottom and sides). This is enabled by the use of regular metallic layers from top and bottom and uses of vertical electrodes (e.g. vias) from the sides. This is in contrast with known art, in which a LM contact can be operated from only two directions. Note that option does not exist in MEMS, which normally does not include a layered CMOS structure.
Device 100 also includes a first conduction line 530 which extends between a first end 532 and a second end 534, a second conduction line 536 which extends between a first end 538 and a second end 540, and a third conduction line 572 which extends between a first end 570 and a second end 574. In an embodiment, the conduction lines are connected to a direct current (DC) source. In another embodiment, the conduction lines are connected to an alternating current (AC) source. LM drop 102 is in permanent electrical contact with second end 540 and is electrically isolated from conduction lines 530 and 572 by dielectric layer 510 and other dielectric layers.
In use, in the “open” state,
To emphasize, in contrast with the use of device 100, in which when the DC voltage is turned to OFF the LM drop returns to its original shape due to its surface tension, in device 500 the switch is disconnected by applying a voltage on a different (added) electrode (572) and pulls the drop in order to disconnect it from the two RF ports currently drawn on the same side.
The N switches may be identical or different. Switch 600 includes a single input/output RF port 606 and N input/output RF ports 608-1 to 608-N. Each switch may be in an “open” or “closed” RF transmission state. Switch 600 may be used for selecting between transmission lines, to control a capacitance level, to control an inductance level or to control an impedance termination level.
In use for selecting between branches (of any kind), switch 600 will have usually one switch 602 in a closed state and all the other switches 602 is open state. When used for controlling a capacitance level or induction level or both, switch 600 will usually have one or more switches 602 in closed state and all the other switches 602 in open state. In an embodiment in which switches 602 are implemented using devices 400, the RF signals in RF ports 606-1 to 606-N will depend on the capacitance value of these devices which is controlled by the DC voltage applied on these devices as described above. When used for controlling an impedance termination level, the switch will be either in open state or, when in closed state, will reflect to the circuit an impedance level between Mega-ohms and zero ohm (grounded).
While this disclosure describes a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of such embodiments may be made. The disclosure is to be understood as not limited by the specific embodiments described herein, but only by the scope of the appended claims.
This application is related to and hereby claims the priority benefit of commonly-owned and co-pending U.S. provisional patent applications No. 61/685,113 filed Mar. 12, 2012, No. 61/633,624 filed February 15, No. 61/633,625 filed Feb. 15, 2012 and No. 61/685,886, filed Mar. 27, 2012, all of which are incorporated herein by reference in their entirety.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/IB2012/053899 | 7/31/2012 | WO | 00 | 7/26/2013 |
Number | Date | Country | |
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61633624 | Feb 2012 | US | |
61633625 | Feb 2012 | US | |
61685113 | Mar 2012 | US | |
61685886 | Mar 2012 | US |