Devices with nanocrystals and methods of formation

Abstract

Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.

Description

TECHNICAL FIELD

This application relates generally to semiconductor devices and device fabrication and, more particularly, to forming nanocrystals and other nanostructures.

BACKGROUND

The semiconductor device industry has a market driven need to reduce the size and cost of integrated circuits (ICs), including persistent memory devices such as floating gate memory and flash memory. As the dimensions of the memory devices are reduced, the voltage used to program the gates is reduced for reliability reasons associated with the thinner gate dielectric thickness. The thinner gate dielectrics for the smaller IC dimensions may have problems with leakage current levels, and thus the length of time the individual gate can retain the programmed charge may not be sufficient.

The floating gate of flash memory devices can be replaced with small crystals. These small crystals have been referred to as nanocrystals. The nanocrystals are located over the channel region, and separated from the channel region by a gate dielectric. The nanocrystals should be distributed and be capable of holding a sufficient charge so that, if programmed to hold a charge, the nanocrystals will control the channel region below the nanocrystals as well as the region between the nanocrystals. Too few nanocrystals, over the entire channel or a portion of the channel, may not be able to control the channel. Too many nanocrystals, over the entire channel or a portion of the channel, may result in a leakage path in the gate dielectric such that some of the charge stored on the nanocrystals may be lost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a floating gate transistor.

FIG. 2 shows a top view of a transistor channel region for a floating gate transistor embodiment.

FIG. 3 illustrates an embodiment of a transistor having one or more levels of nanocrystal floating gates.

FIG. 4 illustrates an embodiment of ion implantation nucleation.

FIG. 5 is a block diagram of an embodiment of an electronic system.

FIG. 6 is a diagram of an embodiment of an electronic system having devices.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

The terms “wafer” and “substrate” used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC) structure or a micro electro-mechanical (MEM) structure. The term “substrate” is understood to include semiconductor wafers. The term “substrate” is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term “conductor” is understood to generally include n-type and p-type semiconductors and the term “insulator” or “dielectric” is defined to include any material that is less electrically conductive than the materials referred to as conductors or as semiconductors. The term “high work function” is understood to generally include all materials having a higher work function than that of heavily doped polycrystalline silicon. The term “high dielectric constant” is understood to generally include all materials having a higher dielectric constant than the 3.9 value of silicon dioxide. The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

Disclosed herein, among other things, is a method for providing a controllable distribution of the nucleation sites across the surface of the substrate for use in growing nanoscale structures. Thus, the density and spatial distribution of nanostructures, such as nanocrystals, can be controlled. In nonvolatile memory embodiments where the nanocrystals function as a floating gate, the distribution and size of the nanocrystals is sufficiently uniform to hold a charge sufficient to control the channel region.

An aspect relates to a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures are grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures include at least one of nanocrystals, nanowires and nanotubes. According to various nanocrystal embodiments, the nanocrystals are positioned within a gate stack and function as a floating gate for a nonvolatile device.

An aspect relates to a method of growing nanocrystals on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes including implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Material is deposited to grow nanocrystals using the controllable distribution of nucleation sites to seed the growth of the nanocrystals.

The present subject matter provides a method for creating nucleation sites with a controllable density and distribution for use in growing nanoscale structures.

The processes illustrated in this disclosure can be used to provide devices with nanoscale structures with a controllable density and distribution. Examples of nanoscale structures include nanocrystals, nanowires, and nanotubes. To simplify the disclosure, a non-volatile memory embodiment with a floating gate formed by nanocrystals is discussed below. Those of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to control the density and distribution of nanostructures, such as nanocrystals, nanowires and nanotubes.

A gate dielectric in a transistor has both a physical gate dielectric thickness and what may be referred to as an equivalent oxide thickness, using the silicon dioxide (SiO₂) gate dielectric as the standard of comparison. The equivalent oxide thickness is a measure of the electrical properties of the gate dielectric, such as capacitance per unit area. Equivalent oxide thickness refers to the thickness of a theoretical SiO₂ layer that would have the same electrical properties as the dielectric layer, and is often useful when dealing with gate dielectrics having dielectric constants that are higher than the 3.9 value of silicon dioxide. High dielectric constant materials are useful in transistors of reduced dimensions. The physical thickness of the high dielectric may be much larger than the electrical equivalent value, and thus higher transistor speed may be obtained without the increased leakage rate and decreased reliability that would be found in an equivalent silicon dioxide gate dielectric. For example, a dielectric material with a dielectric constant of 10 would have a physical thickness of 2.5 nanometers to provide the same speed performance as a silicon dioxide thickness of only 1.0 nanometer, and would have better leakage characteristics due to the greater physical thickness. A high dielectric constant gate dielectric may be useful in the present subject matter, including the reduced leakage current values from the individual nanocrystals of the floating gate to the substrate, resulting in increased data retention values. High work function material may be useful in the present subject matter by adjusting the tunneling barrier to adjust the programming barriers and speed.

FIG. 1 illustrates an embodiment of a floating gate transistor 100 having a substrate 102, a source diffusion region 104 having an opposite doping type from the substrate, and a drain diffusion region 106, having the same doping type as the source region 104. The area of the substrate 102 between the source 104 and the drain 106 is known as the channel. The channel allows conduction between the source and drain if the gate 112 has an appropriate charge. The amount of charge on the gate 112 needed to allow conduction depends on factors including the thickness and dielectric constant of the gate insulator 110, the doping level of the substrate 102 and the channel 108, and leakage between the gate 112 and the substrate. The gate 112 in the present embodiment is what is known as a floating gate that has no direct electrical connection to any signal, electrode or substrate, and is formed of many small closely spaced nanoparticles in non contacting proximity to one another. These small closely spaced nanoparticles may be known as nanocrystals and act as a single electrode if the spaces between the nanocrystals are small enough to control the region of the channel 108 surrounding the nanocrystal. A floating gate formed from nanocrystals has also been referred to as a floating plate. The transistor 100 also includes an inter-gate dielectric layer 114 and a control electrode 120, which may be formed of any gate electrode material. The control electrode is connected to signal over conductor 122.

Nanocrystals such as those of floating electrode 112 may be grown in a number of ways using well known methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), and spin coating. Various nanocrystal embodiments include metals and various nanocrystal embodiments include insulators. For example, the nanocrystals may be made of any gate electrode material, including high work function materials. Various nanocrystal embodiments include platinum (Pt), various nanocrystal embodiments include rhodium (Rh), various nanocrystal embodiments include ruthenium (Ru), various nanocrystal embodiments include palladium (Pd), various nanocrystal embodiments include cobalt (Co), various nanocrystal embodiments include silicon (Si), various nanocrystal embodiments include titanium (Ti), various nanocrystal embodiments include zirconium (Zr), various nanocrystal embodiments include hafnium (Hf), various nanocrystal embodiments include tantalum (Ta), various nanocrystal embodiments include tungsten (W), various nanocrystal embodiments include tantalum nitride (TaN), various nanocrystal embodiments include titanium nitride (TiN), various nanocrystal embodiments include tungsten nitride (WN), various nanocrystal embodiments include titanium oxide (TiO_X), various nanocrystal embodiments include cobalt oxide (CoO_X), various nanocrystal embodiments include ruthenium oxide (RuO_X), various nanocrystal embodiments include hafnium oxide (HfO_X), various nanocrystal embodiments include aluminum oxide (Al₂O₃), various nanocrystal embodiments include tungsten oxide (WO_X), various nanocrystal embodiments include titanium carbide (TiC), various nanocrystal embodiments include tantalum carbide (TaC), various nanocrystal embodiments include tungsten carbide (WC), and various nanocrystal embodiments include various combinations of these materials.

If the nanocrystals of floating gate 112 are substantially in direct electrical contact with one another, then the floating gate will function as a single gate electrode. If there is a leakage path somewhere in the gate insulator 110, then the charge stored in the gate electrode 112 will disappear over time, and the data retention of the transistor 100 will be unacceptable. Even if the entire floating gate 112 does not discharge, but a substantial portion of the gate electrode 112 has a leakage path, then the channel region will block or limit current flow in the region of the channel 108 corresponding to the leakage path, and the transistor 100 will either be non-conductive, or conductive at a level too low for proper operation.

With respect to nonvolatile memory embodiments with floating gates formed from nanocrystals, it is desired to have the floating gate nanocrystals close enough together to electrically control the space between the nanocrystals, but not to have the nanocrystals be too large or to be in direct electrical contact with each other. For example, one sub-50 nm nonvolatile memory embodiment has approximately 100 nanocrystals in a 40 by 40 nanometer channel region, with the nanocrystals being around 2 nanometers in size and about 2 nanometers in separation from one another. Other embodiments are anticipated to accommodate other device dimensions, and other structures with nanocrystal distributions are contemplated.

One method to provide control of the size and spacing of the nanocrystals provides nucleation sites to initiate the ALD or CVD chemical reactions to begin to form nanocrystals. The nucleation sites may be formed by damage locations in the top surface of the gate dielectric, or by ion implantation of atoms into or onto the top surface of the dielectric. Normal energy ion implantation energies such as fifteen thousand electron volts (15 KeV) using boron ions may result in inadequate dielectric damage at the surface and undesirable amounts of damage deeper in the gate dielectric, resulting in leakage paths or short circuits due to the relatively high speed of the ion. Low energy ion implantation resulting in ions or atoms that stick out of the surface of the gate dielectric may most efficiently form the nucleation sites.

FIG. 2 shows a top view of a transistor channel region for a floating gate transistor embodiment. The illustrated transistor 200 has a source diffusion region 204, a drain diffusion region 206, and a channel region 208. A gate dielectric is not shown for simplicity. A number of nanocrystals 212 are distributed substantially evenly over the entire area of the channel 208. In the illustration, none of the nanocrystals are touching one another. According to a sub-50 nm nonvolatile memory embodiment, the channel region is about 40 nanometers on a side and contains about 100 nanocrystals having a size of about 2 nanometers and a spacing of about 2 nanometers. Not all of the nanocrystals will be exactly 2 nanometers and have a 2 nanometer spacing, nor will every nanocrystal be electrically isolated as shown in the figure. However, the present subject matter is capable of providing nanocrystals with substantially even distribution in size and in spacing. If the spacing becomes too large, then regions of the channel 208 will not be turned on as programmed, resulting in either lower source 204 to drain 206 conduction, or an open circuit. Leakage paths can potentially develop if the nanocrystals 212 are too large or in direct electrical contact. Such leakage paths across the gate dielectric will reduce the charge stored by the corresponding nanocrystals, and potentially result in regions of the channel 208 that are not as conductive as desired, and potentially result in reduced data retention periods.

FIG. 3 illustrates an embodiment of a transistor having one or more levels of nanocrystal floating gates. In this illustrative embodiment the nanocrystals are shown as individual elements with a first layer of nanocrystals 312 and a second layer of nanocrystals 316. The present subject matter has embodiments having only a single layer of nanocrystals 312, or two, three or even more individual layers of nanocrystals. Each of the individual layers of nanocrystals may have a controlled size crystal and a substantially uniform distribution of electrically isolated nanocrystals. This illustrative embodiment has a transistor 300 formed on a substrate 302, which may be a silicon substrate of either P type or N type, an epitaxial layer grown on a silicon substrate or on an insulative substrate such as sapphire. The substrate may also be all other semiconductive material such as amorphous silicon, polycrystalline silicon, germanium, gallium arsenide, or any other compound semiconductor and still be within the inventive subject matter. The substrate has a source region 304 and a drain region 306 with a channel region 308 between the source and drain. There is a gate dielectric 310, which may be silicon oxide, silicon nitride, silicon oxynitride, or any other dielectric or insulative material, including high dielectric constant materials such as alumina, titanium dioxide, hafnium dioxide, tantalum dioxide, barium titanate, and the like. The gate dielectric 310 separates the floating gate electrode 312 from the channel region and the source and drain regions. The gate electrode 312 in this embodiment is formed of individual nanocrystals 312 of material capable of storing a charge. For example, the nanocrystals can be formed from any gate electrode material, such as polysilicon, refractory metals such as tungsten, high work function materials such as silicon carbide, or other conductive material or semiconductor material capable of forming nanocrystals with the desired properties to function as the floating gate of a floating gate nonvolatile memory device. The nanocrystals also can be formed from insulators, such as RuO_X, CoO_X, TiO₂ and the like. The first floating gate 312 has spaces 313 between each of the nanocrystals so that the nanocrystals are electrically isolated from each other. The first layer of nanocrystals has a first inter-gate dielectric layer 314, which may be formed of any dielectric material as above, upon which a second layer of nanocrystals 316 is formed as above with reference to the first layer of nanocrystals 312. The second layer of nanocrystals 316 has spaces 317 separating the nanocrystals. The second layer of nanocrystals has a second inter-gate dielectric layer 318 formed as above, which separates the second nanocrystal layer from the control gate 320, which is connected to an input signal 322 from either an adjacent transistor or from an external source. The formation of the dielectric layers can use a variety of processes, such as chemical vapor deposition, atomic layer deposition, evaporation, and the like, as may be appropriate for the dielectric type and size. Any dielectric deposition technique may be used which results in very conformal coverage of nanocrystals and which provides a good quality dielectric with degradation of the nanocrystals. Degradation of nanocrystals may occur because of the temperature or corrosiveness of the deposition temperature. There may be additional layers of nanocrystal floating gates formed in the same manner. Such transistors as those discussed in FIGS. 1 to 3 may be used in logic devices as local memory, as non-volatile memory arrays such as flash memory, or in almost any electronic device. Some embodiments will treat the nanocrystals, such as illustrated at 312 or 316, before depositing their corresponding subsequent intergate dielectric, such as illustrated at 314 and 318. For example, the nanocrystals can be oxidized.

For floating gate embodiments, the size of the nanocrystals can range from about 0.5 nanometers to about 5 nanometers, and the average spacing between nanocrystals can range from about 0.5 nanometers to about 5 nanometers. It is expected that approximately 80% or more of the nanocrystals will fall within these ranges. According to various sub-50 nm nonvolatile memory embodiments, an average size of the nanocrystals is 2 nanometers with a spacing between nanocrystals of about 2 nanometers. According to various embodiments, the electrically isolated nanocrystals have a maximum diameter of 4.0 nanometers and a density of greater than one nanocrystal per 15 square nanometers.

FIG. 4 illustrates an embodiment of ion implantation nucleation. The transistor is shown in an intermediate step of the manufacturing process, when a device having a semiconductive substrate 402 with source 404 and drain 406 formed on a surface of the substrate. The drawing is meant to illustrate the implantation of nucleation sites, and is not drawn to scale. There is a channel region 408 and a gate insulator layer 410. The nucleation sites may be formed over the entire wafer as shown, or only over the channel region 408 by simple photo-masking or other well known masking procedures, to limit the ion implantation to the channel region of the gate dielectric 410. The nucleation sites may be damage locations in the top surface of the gate dielectric 410 caused by the passage of relatively heavy ions such as argon, or they may be atoms of the ion implanted material sticking up from the gate dielectric surface as shown. The depth range of the implanted ion should be small to cause the ions to stop at the top surfaces, or at least near the top surface to avoid excessive gate dielectric damage. For example, according to various embodiments, the implanted ions do not travel past the top 1 nanometer of the gate dielectric layer 410 or do not travel past the top ⅕ of the gate dielectric layer 410.

The ions 412 may be formed by any method of ion formation and acceleration, including plasma systems such as plasma doping systems (PLAD). The ion energy should be low enough to prevent any of the ions 412 from moving fast enough in the direction indicated by the arrows toward the gate dielectric 410 to penetrate the gate dielectric layer. Various types of ions may be used, such as typical dopant species such as boron, phosphorous or arsenic. The ions may be of the material that will form the nanocrystals, or the ions may be of inert gases such as argon, neon, helium and xenon, or the ions may be semiconductor materials such as silicon, carbon, germanium or other ions. The dose of the ion has an affect on the uniformity of the distribution of eventual nanocrystals grown and on the size of the nanocrystals.

Typical ion energies depend upon the mass of the ion, and should be set to partially embed the ions 412 into the surface of the gate dielectric 410 either partially, as shown with ion 414, entirely embedded forming a persistent defect in the surface of the gate dielectric, as shown with ion 416, or slightly so as to remain entirely on the surface of the gate dielectric, as shown with ion 418. Typical ion energies found with PLAD are a few dozen electron volts (eV). Typical ion densities expressed in the number of ions per unit surface area are in the 10¹² ions/cm² levels. The ions should preferably be deposited in a discontinuous layer on the surface of the gate dielectric 410. According to various floating gate embodiments for sub-50 nm memories, the range of energies for implanting boron ion(s) into a silicon dioxide gate dielectric extend from approximately 0.01 KeV to approximately 2.0 KeV with a dose of ranging from approximately 1E11 ions/cm² to approximately 1E14 ions/cm². The energy and dose ranges depend on the ions and the gate dielectric. Thus, appropriate energies and doses can be selected to implant a variety of ions on the surface or shallowly below the surface of a variety of gate dielectrics.

Structures such as shown in FIG. 1, 2, 3 or 4 may be used in any integrated circuit or transistor devices, such as flash memory devices as well as other memory, logic or information handling devices and systems. Embodiments of these information handling devices include wireless systems, telecommunication systems, computers and integrated circuits.

FIG. 5 is a block diagram of an embodiment of an electronic system. The illustrated electronic system 500 has one or more devices having portions of the circuits with non-volatile memory devices, with nanocrystals as disclosed herein. Electronic system 500 includes a controller 502, a bus 504, and an electronic device 506, where bus 504 provides electrical conductivity between controller 502 and electronic device 506. In various embodiments, controller 502 and/or electronic device 506 include an embodiment for a portion of the device design used for nanocrystal floating gate transistors as previously discussed herein. Electronic system 500 may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers.

FIG. 6 depicts a diagram of an embodiment of a system 600 having a controller 602 and a memory 606. Controller 602 and/or memory 606 include a portion of the circuit for selectively heating the device to a desired temperature. System 600 also includes an electronic apparatus 608, and a bus 604, where bus 604 may provide electrical conductivity and data transmission between controller 602 and electronic apparatus 608, and between controller 602 and memory 606. Bus 604 may include an address, a data bus, and a control bus, each independently configured. Bus 604 also uses common conductive lines for providing address, data, and/or control, the use of which may be regulated by controller 602. In an embodiment, electronic apparatus 608 includes additional memory devices configured similarly to memory 606. An embodiment includes an additional peripheral device or devices 610 coupled to bus 604. In an embodiment controller 602 is a processor. Any of controller 602, memory 606, bus 604, electronic apparatus 608, and peripheral device or devices 610 may include a nonvolatile memory in accordance with the disclosed embodiments. System 600 may include, but is not limited to, information handling devices, telecommunication systems, and computers. Peripheral devices 610 may include displays, additional memory, or other control devices operating in with controller 602 and/or memory 606.

The present subject matter provides a method for creating nucleation sites with a controllable density and distribution for use in growing nanoscale structures. The nucleation sites are created using low energy ion implantation techniques to create the nucleation sites at or near the top surface of material in which the ions are implanted. Thus, the processes illustrated in this disclosure are able to seed the growth of nanoscale structures, such as nanocrystals, nanowires and nanotubes, such that the resulting nanoscale structures have a controllable density and distribution. Nanocrystals can be used for a variety of purposes, such as storing charge, enhancing tunneling, and channeling current to increase current density. The floating gate embodiment provided above is an example of a device where the nanocrystals are used to store charge. Such charge storing nanocrystals can also be used to selectively store charge in a body of a transistor in a nonvolatile memory design, such as illustrated in, for example, U.S. Patent Application Publication 2004/0041208, entitled “One Transistor SOI Non-Volatile Random Access Memory Cell”. Some embodiments may use nanocrystals to enhance tunneling, such as may be beneficial between a control gate and a floating gate. Enhanced charge tunneling is illustrated in, for example, U.S. Patent Application Publication 2003/0042534, entitled “Scalable Flash/NV Structure and Device with Extended Endurance”. Additionally, nanocrystals can be used to provide a path for a locally high current density, such as may be useful for fast ionic or phase change memory devices. Thus, a locally high current density can be provided for a relatively large electrode.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of embodiments of the present invention, including but not limited to. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description. The scope of the present invention includes any other applications in which embodiments of the above structures and fabrication methods are used. The scope of the embodiments of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. An electronic device comprising: a substrate having a pair of diffused regions with a diffusion type opposite that of the substrate;a plurality of dielectric layers disposed over the substrate, the plurality of dielectric layers comprising ion nucleation sites embedded in a surface of the plurality of dielectric layers;a plurality of layers of electrically isolated nanocrystals disposed upon the plurality of dielectric layers, each electrically isolated nanocrystal disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals, each layer of the plurality of layers of electrically isolated nanocrystals vertically spaced from the other layers of electrically isolated nanocrystals; anda control gate disposed above the plurality of dielectric layers.

2. The electronic device of claim 1 wherein at least one of the plurality of dielectric layers does not comprise any nanocrystals.

3. The electronic device of claim 2 wherein the at least one of the plurality of dielectric layers without the nanocrystals is disposed between the substrate and the plurality of dielectric layers with the electrically isolated nanocrystals.

4. The electronic device of claim 3 wherein the at least one of the plurality of dielectric layers without the nanocrystals comprises one of silicon oxide, silicon nitride, silicon oxynitride, alumina, titanium dioxide, hafnium dioxide, tantalum dioxide, or barium titanate.

5. The electronic device of claim 1 wherein the electrically isolated nanocrystals comprise one of metal nanocrystals, insulating nanocrystals, or combinations of metal nanocrystals and insulating nanocrystals.

6. The electronic device of claim 1 wherein the substrate comprises one of amorphous silicon, polycrystalline silicon, germanium, or a compound semiconductor.

7. The electronic device of claim 1 wherein the plurality of electrically isolated nanocrystals are disposed over the substrate between the pair of diffused regions.

8. The electronic device of claim 1 wherein adjacent layers of the plurality of layers of electrically isolated nanocrystals are separated by a dielectric layer.

9. The electronic device of claim 1 wherein the electronic device is a non-volatile memory device.

10. The method of claim 1 wherein the nanocrystals comprise platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), titanium oxide (TiOX), cobalt oxide (CoOX), ruthenium oxide (RuOX), hafnium oxide (HfOX), aluminum oxide (Al2O3), tungsten oxide (WOX), titanium carbide (TiC), tantalum carbide (TaC), or tungsten carbide (WC).

11. The method of claim 1 wherein the nanocrystals comprise combinations of two or more of platinum (Pt), rhodium (Rh), ruthenium (Ru), palladium (Pd), cobalt (Co), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), tungsten (W), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium oxide (TiOX), cobalt oxide (CoOX), ruthenium oxide (RuOX), hafnium oxide (HfOX), aluminum oxide (Al2O3), tungsten oxide (WOX), titanium carbide (TiC), tantalum carbide (TaC), or tungsten carbide (WC).

12. A system comprising: a controller; andan electronic device coupled to the controller, the electronic device comprising a plurality of floating gate transistors, each floating gate transistor comprising: a source and a drain formed in a substrate and separated laterally from each other by a region;a plurality of gate dielectrics disposed above the substrate;a plurality of layers of isolated nucleation sites, each layer disposed in different gate dielectrics;a plurality of layers of electrically isolated nanocrystals, each layer disposed on a top surface of the different gate dielectrics with a substantially even statistical distribution above and across the region, each electrically isolated nanocrystal disposed from a respective ion implanted material of the ion nucleation sites, the ion implanted material being of a material different from the electrically isolated nanocrystals;an inter-gate dielectric disposed over the plurality of gate dielectrics; andforming a control gate electrode disposed over the inter-gate dielectric.

13. The system of claim 12 wherein the plurality of gate dielectrics comprise a first thickness and the inter-gate dielectric comprises a second thickness that is different than the first thickness.

14. The system of claim 12 wherein at least 80% of the electrically isolated nanocrystals have diameters within a range of approximately 0.5 nanometers to approximately 5 nanometers, and are separated from each other by a separation distance within a range from approximately 0.5 nanometers to approximately 5 nanometers.

15. The system of claim 12 wherein the nucleation sites in the gate dielectrics are substantially all on a top surface of the gate dielectrics.

16. The system of claim 12 wherein each electrically isolated nanocrystal is attached to its respective dielectric layer by its respective ion nucleation site formed by a defect including at least one of boron, nitrogen, neon, argon, krypton, platinum, ruthenium, rhodium, palladium, titanium, zirconium, hafnium, silicon, germanium, cobalt, or tantalum.

17. The system of claim 12 wherein the ion implanted material is located above the top ⅕ of each of the gate dielectric layers.

18. The system of claim 12 wherein the ion implanted material comprises inert gases or semiconductor materials.

19. The system of claim 18 wherein the inert gases comprise argon, neon, helium or xenon and the semiconductor materials comprise silicon, carbon, or germanium.

20. The system of claim 12 wherein each layer of electrically isolated nanocrystals comprises a floating gate.

21. A memory cell comprising: a channel region;a first dielectric material adjacent to the channel region;a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures;a second dielectric material adjacent to the plurality of nanoscale structures; anda control gate adjacent to the second dielectric material.

22. The memory cell of claim 21, wherein the nanoscale structures comprise at least one of nanocrystals, nanowires and nanotubes.

23. The memory cell of claim 21, wherein the nanoscale structures comprises nanocrystals, and wherein the nanocrystals function as a floating gate of the memory cell.

24. The memory cell of claim 21, wherein the nanoscale structures comprise ruthenium nanocrystals.

25. The memory cell of claim 21, wherein the nucleation sites comprise atoms of the ion implanted material sticking out from the surface of the first dielectric material.

26. The memory cell of claim 21, wherein the nucleation sites comprise ions sticking out from the surface of the first dielectric material.

27. The memory cell of claim 21, wherein the channel region comprises polycrystalline silicon.

28. The memory cell of claim 21, wherein the channel region comprises silicon.

29. The memory cell of claim 21, wherein the channel region is between a source region and a drain region.

30. The memory cell of claim 21, wherein the plurality of nanoscale structures comprise a plurality of electrically isolated nanoscale structures.

31. The memory cell of claim 21, wherein the plurality of nanoscale structures are disposed upon the first dielectric material.

32. The memory cell of claim 21, wherein at least one of the plurality of nucleation sites at least partially embedded in a surface of the first dielectric material is only partially embedded into the surface of the first dielectric material.

33. The memory cell of claim 21, wherein at least one of the plurality of nucleation sites at least partially embedded in the surface of the first dielectric material is entirely embedded into the surface of the first dielectric material.

34. The memory cell of claim 21, wherein the ion implanted material of the plurality of nucleation sites is in the top 1 nanometer of the first dielectric material.

35. The memory cell of claim 21, wherein the ion implanted material of the plurality of nucleation sites is in the top ⅕th of the first dielectric material.

36. The memory cell of claim 21, wherein sizes of the plurality of nanoscale structures range from about 0.5 nanometers to about 5 nanometers.

37. The memory cell of claim 21, wherein average spacings between adjacent nanoscale structures of the plurality of nanoscale structures range from about 0.5 nanometers to about 5 nanometers.

38. The memory cell of claim 21, wherein a density of the plurality of nanoscale structures is greater than one nanoscale structure per 15 square nanometers.

39. A transistor comprising: a channel region;first dielectric material adjacent to the channel region;a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures;second dielectric material adjacent to the plurality of nanoscale structures; anda control gate adjacent to the second dielectric.

40. A memory device comprising a plurality of memory cells, wherein each of the memory cells comprises: a channel region;first dielectric material adjacent to the channel region;a plurality of nanoscale structures, each of the plurality of nanoscale structures seeded from ion implanted material of a respective nucleation site of a plurality of nucleation sites at least partially embedded in a surface of the first dielectric material opposite the channel region, the ion implanted material being of a material different from the plurality of nanoscale structures;second dielectric material adjacent to the plurality of nanoscale structures; anda control gate adjacent to the second dielectric.