Patent Application
20250238588
The present disclosure relates to processing units. More particularly, the present disclosure relates to configuring a processing unit to utilize a die in multiple rotational states with reduced trace routes for various channels.
ASIC, or Application-Specific Integrated Circuits, represent a type of integrated circuit tailored for a specific application rather than serving as a general-purpose device. The process of ASIC design involves several stages, including specification, design, verification, and manufacturing. Designers utilize hardware description languages (HDLs) such as Verilog or VHDL to articulate the functionality of the circuit. The key feature of ASICs is their customization for a particular purpose, allowing for optimization in performance, power efficiency, and physical size. This customization contributes to the superior performance of ASICs compared to general-purpose processors, as they are engineered to excel in their designated functions.
While ASICs offer enhanced performance, their development often incurs higher upfront costs for design and manufacturing. This cost is justified in applications where specific performance, power efficiency, or other tailored requirements are crucial. Despite the advantages, ASIC development typically takes longer compared to utilizing off-the-shelf components. Once developed, however, ASICs prove advantageous in terms of their specialized performance and efficiency. Examples of ASIC applications span diverse fields, including telecommunications, automotive systems, consumer electronics, and notably in cryptocurrency, where ASICs are commonly employed for mining purposes, optimized for specific hashing algorithms.
For certain processing units, ASIC chip family planning often comprises a first version that is fully functional (and includes full serialization/deserialization (SerDes) functionality. However, at the second phase, for the cost sensitive products, designs can be a configured as a “lite” version to keep costs down. These configurations can use the same die but reduce the SerDes channel numbers to half or less than half with smaller packages. This can lead to inefficient usage of the available dies.
Systems and methods for configuring a processing unit to utilize a die in multiple rotational states with reduced trace routes for various channels in accordance with embodiments of the disclosure are described herein.
In some embodiments, a processing unit includes a die, wherein the die is bifurcated, and a substrate, configured to couple with the die at a first orientation, wherein the substrate is further configured to couple with the die at a second orientation.
In some embodiments, the second orientation is one-hundred and eighty degrees relative to the first orientation.
In some embodiments, the bifurcation is configured to render the die into a first slice and a second slice.
In some embodiments, the first slice and second slice have similar communication channels.
In some embodiments, the communication channels include a plurality of serialization/deserialization (SerDes) channels.
In some embodiments, the plurality of SerDes channels are divided equally between the first slice and the second slice.
In some embodiments, the substrate is configured with a plurality of corresponding SerDes channels.
In some embodiments, the substrate extends outward from the die on all four sides when coupled.
In some embodiments, the plurality of corresponding SerDes channels on the substrate are disposed on three of the four sides.
In some embodiments, the corresponding SerDes channels are communicatively coupled to the plurality of SerDes channels on the substrate through a matching plurality of traces.
In some embodiments, the corresponding plurality of SerDes channels on the substrate are arranged to facilitate shorter trace lengths of the matching plurality of traces.
In some embodiments, a method includes bifurcating a die into a first slice and a second slice, configuring a substrate to couple with the die at both a first orientation associated with a first slice, and a second orientation associated with the second slice, and coupling the die to the substrate.
In some embodiments, each slice of the die is configured with a plurality of serialization/deserialization (SerDes) channels.
In some embodiments, the substrate is further configured with a corresponding plurality of SerDes channels.
In some embodiments, the substrate extends outward from the die on all four sides when coupled.
In some embodiments, the plurality of corresponding SerDes channels on the substrate are disposed on three of the four sides.
In some embodiments, the corresponding SerDes channels are communicatively coupled to the plurality of SerDes channels on the substrate through a matching plurality of traces.
In some embodiments, the corresponding plurality of SerDes channels on the substrate are arranged to facilitate shorter trace lengths of the matching plurality of traces.
In some embodiments, a processing unit includes a die, wherein the die is bifurcated into a first slice and a second slice, and configured with a plurality of similar serialization/deserialization (SerDes) channels on each slice, and a substrate, wherein the substrate is configured to communicatively couple with the plurality of SerDes channels via a corresponding plurality of SerDes channels and a matching plurality of traces, and wherein, the substrate is further configured to couple with the die in at least two orientations. Each orientation providing similar communicative coupling between the plurality of SerDes channels on each slice and the corresponding SerDes channels and matching plurality of traces on the substrate.
Other objects, advantages, novel features, and further scope of applicability of the present disclosure will be set forth in part in the detailed description to follow, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the disclosure. Although the description above contains many specificities, these should not be construed as limiting the scope of the disclosure but as merely providing illustrations of some of the presently preferred embodiments of the disclosure. As such, various other embodiments are possible within its scope. Accordingly, the scope of the disclosure should be determined not by the embodiments illustrated, but by the appended claims and their equivalents.
The above, and other, aspects, features, and advantages of several embodiments of the present disclosure will be more apparent from the following description as presented in conjunction with the following several figures of the drawings.
Corresponding reference characters indicate corresponding components throughout the several figures of the drawings. Elements in the several figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures might be emphasized relative to other elements for facilitating understanding of the various presently disclosed embodiments. In addition, common, but well-understood, elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present disclosure.
In response to the issues described above, devices and methods are discussed herein that can enter deep standby lower-power state utilizing a physical level connection while retaining connections with neighboring devices, thus conserving a greater amount of electricity. A processor package is a sophisticated assembly comprising various components that collectively house and facilitate the operation of the central processing unit (CPU). At the heart of the package lies the die, a tiny silicon chip containing the processor's core elements, such as the arithmetic and logic units and cache memory. This die is mounted on a substrate, often made of materials like fiberglass-reinforced epoxy, providing structural support and hosting a network of trace routes. These trace routes serve as electrical pathways, enabling communication between the die and other parts of the package, as well as the external components on the motherboard.
The substrate, besides offering mechanical support, features a package cavity, a recessed area where the die is securely positioned. This cavity not only protects the delicate die but also accommodates thermal solutions, like heat spreaders or heat sinks, crucial for managing the heat generated during processor operation. The package is externally connected to the motherboard through package pins, arranged in a grid pattern along the edges, which transmit signals, power, and ground connections.
Additionally, the processor package incorporates a lid or cap, often referred to as the Integrated Heat Spreader (IHS). This metal cover sits atop the die and aids in dissipating heat away from the processor. To enhance thermal conductivity, a Thermal Interface Material (TIM) is applied between the die and the IHS. The efficient transfer of heat is pivotal in maintaining optimal operating temperatures and ensuring the processor's reliability.
The overall package is designed to be mounted on the motherboard using either a Ball Grid Array (BGA) or Land Grid Array (LGA) configuration. In the BGA setup, the processor is directly soldered to the motherboard, while in the LGA arrangement, an array of lands on the motherboard makes contact with corresponding pins on the processor package. The intricate interplay of these components, including the die, substrate, trace routes, thermal solutions, and external connections, is fundamental in creating a high-performance and reliable processor package for modern computing systems.
ASIC, or Application-Specific Integrated Circuits, represent a type of processor tailored for a specific application rather than serving as a general-purpose device. The process of ASIC design involves several stages, including specification, design, verification, and manufacturing. Designers utilize hardware description languages (HDLs) such as Verilog or VHDL to articulate the functionality of the circuit. The key feature of ASICs is their customization for a particular purpose, allowing for optimization in performance, power efficiency, and physical size. This customization contributes to the superior performance of ASICs compared to general-purpose processors, as they are engineered to excel in their designated functions.
While ASICs offer enhanced performance, their development often incurs higher upfront costs for design and manufacturing. This cost is justified in applications where specific performance, power efficiency, or other tailored requirements are crucial. Despite the advantages, ASIC development typically takes longer compared to utilizing off-the-shelf components. Once developed, however, ASICs prove advantageous in terms of their specialized performance and efficiency. Examples of ASIC applications span diverse fields, including telecommunications, automotive systems, consumer electronics, and notably in cryptocurrency, where ASICs are commonly employed for mining purposes, optimized for specific hashing algorithms.
For certain processing units, ASIC chip design planning often comprises a first version that is fully functional (and includes full serialization/deserialization (SerDes) functionality. However, at the second phase, for the cost sensitive products, designs can be a configured as a “lite” version to keep costs down. These configurations can use the same die but reduce the SerDes channel numbers to half or less than half with smaller packages. This can lead to inefficient usage of the available dies. Therefore, embodiments described herein can more efficiently compress the SerDes and other communication channels by configuring the die in a bifurcated manner and couple it with a substrate that is configured with a compressed SerDes channel design, allow for reduced trace lengths which can increase performance and potentially reduce manufacturing costs.
Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, or the like) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “function,” “module,” “apparatus,” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer-readable storage media storing computer-readable and/or executable program code. Many of the functional units described in this specification have been labeled as functions, in order to emphasize their implementation independence more particularly. For example, a function may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A function may also be implemented in programmable hardware devices such as via field programmable gate arrays, programmable array logic, programmable logic devices, or the like.
Functions may also be implemented at least partially in software for execution by various types of processors. An identified function of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions that may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified function need not be physically located together but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the function and achieve the stated purpose for the function.
Indeed, a function of executable code may include a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, across several storage devices, or the like. Where a function or portions of a function are implemented in software, the software portions may be stored on one or more computer-readable and/or executable storage media. Any combination of one or more computer-readable storage media may be utilized. A computer-readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing, but would not include propagating signals. In the context of this document, a computer readable and/or executable storage medium may be any tangible and/or non-transitory medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, processor, or device.
Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object-oriented programming language such as Python, Java, Smalltalk, C++, C#, Objective C, or the like, conventional procedural programming languages, such as the “C” programming language, scripting programming languages, and/or other similar programming languages. The program code may execute partly or entirely on one or more of a user's computer and/or on a remote computer or server over a data network or the like.
A component, as used herein, comprises a tangible, physical, non-transitory device. For example, a component may be implemented as a hardware logic circuit comprising custom VLSI circuits, gate arrays, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. A component may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the functions and/or modules described herein, in certain embodiments, may alternatively be embodied by or implemented as a component.
A circuit, as used herein, comprises a set of one or more electrical and/or electronic components providing one or more pathways for electrical current. In certain embodiments, a circuit may include a return pathway for electrical current, so that the circuit is a closed loop. In another embodiment, however, a set of components that does not include a return pathway for electrical current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return pathway for electrical current) or not. In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a set of integrated circuits, a set of non-integrated electrical and/or electrical components with or without integrated circuit devices, or the like. In one embodiment, a circuit may include custom VLSI circuits, gate arrays, logic circuits, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device such as field programmable gate array, programmable array logic, programmable logic device, or the like (e.g., as firmware, a netlist, or the like). A circuit may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the functions and/or modules described herein, in certain embodiments, may be embodied by or implemented as a circuit.
Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to”, unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise.
Further, as used herein, reference to reading, writing, storing, buffering, and/or transferring data can include the entirety of the data, a portion of the data, a set of the data, and/or a subset of the data. Likewise, reference to reading, writing, storing, buffering, and/or transferring non-host data can include the entirety of the non-host data, a portion of the non-host data, a set of the non-host data, and/or a subset of the non-host data.
Lastly, the terms “or” and “and/or” as used herein are to be interpreted as inclusive or meaning any one or any combination. Therefore, “A, B or C” or “A, B and/or C” mean “any of the following: A; B; C; A and B; A and C; B and C; A, B and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or acts are in some way inherently mutually exclusive.
Aspects of the present disclosure are described below with reference to schematic flowchart diagrams and/or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the disclosure. It will be understood that each block of the schematic flowchart diagrams and/or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams and/or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor or other programmable data processing apparatus, create means for implementing the functions and/or acts specified in the schematic flowchart diagrams and/or schematic block diagrams block or blocks.
It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated figures. Although various arrow types and line types may be employed in the flowchart and/or block diagrams, they are understood not to limit the scope of the corresponding embodiments. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment.
In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements of proceeding figures. Like numbers may refer to like elements in the figures, including alternate embodiments of like elements.
Referring to
In the context of processor communication, the utilization of these communication channels often involves the integration of one or more serializers and deserializers, collectively known as SerDes components. These are fundamental in facilitating the transmission of data over serial channels. When a processor generates parallel data that needs to be transmitted, the serializer converts this data into a serial stream. The communication channels, represented by physical structures like lead frames and pins, serve as pathways for the serialized data. These channels extend beyond the processor package to the substrate, or Printed Circuit Board (PCB), incorporating traces and conductive pathways for efficient data transmission.
Although a specific embodiment for a conceptual partial cutaway illustration of a processor 100 suitable for carrying out the various steps, processes, methods, and operations described herein is discussed with respect to
Referring to
In a number of embodiments, semiconductor packaging can comprise the die 210, containing the integrated circuits, being securely mounted onto a substrate 230, which provides physical support and facilitates electrical connections. To address potential gaps and differences in thermal expansion between the die and the substrate, an underfill 220 is often applied. In certain embodiments, the die 210 can be attached to the substrate 230 using adhesives, and then an underfill 220, typically a liquid or gel-like material, is dispensed around the die's perimeter. This underfill 220 flows into the gaps through capillary action, creating a strong mechanical bond. After placement, the underfill is cured or hardened, forming a solid and stable connection between the die 210 and the substrate 230. Beyond improving mechanical integrity, the underfill 220 enhances thermal performance by serving as a thermal interface material, facilitating efficient heat transfer. Additionally, the underfill 220 provides protection for the die 210 and wire bonds against environmental factors like moisture and contaminants. The curing process can be achieved through methods such as heat or ultraviolet light, ensuring the reliability, durability, and optimal thermal characteristics of the final packaged semiconductor device.
Although a specific embodiment for a conceptual partial cutaway illustration of a processing package suitable for carrying out the various steps, processes, methods, and operations described herein is discussed with respect to
Referring to
In various embodiments, the processing package 300 is further defined by the application of a thermal grease 360 onto the processor/die 310. Additionally, a cap 350 can be fitted on top of the processing unit. The thermal grease 360 can be configured to allow for the thermal exchange or passing of heat generated by the die 310 to the cap 350 to better dissipate the generated heat. Thus, herein the processing package 300 can be understood as a processing unit with a cap applied.
Although a specific embodiment for a conceptual side-view illustration of a processing package suitable for carrying out the various steps, processes, methods, and operations described herein is discussed with respect to
Referring to
When a die is manufactured with multiple slices or cores, it is common for not all of them to function perfectly due to potential defects or variations in the fabrication process. In such cases, a technique known as “binning” is employed during the testing and validation phase. During manufacturing, processors are tested to identify any faulty or suboptimal cores. Once identified, the processor is categorized into different bins or groups based on the quality and performance of its cores. Processors with all functional cores intact are placed in the highest-performing bin and often sold as premium or high-end models. Processors with one or more non-functional cores are placed in lower-performance bins.
These dies with defective cores can still be used effectively by disabling the faulty cores of slices through a process called “disabling” or “harvesting.” This involves configuring the dic to only utilize the functional areas, effectively turning off the non-functional ones. The disabled areas are then bypassed during operation, and the processor operates with the remaining functional cores or slices. This approach allows semiconductor manufacturers to salvage imperfect chips and offer them at a lower price point, providing cost-effective solutions for consumers who may not need the full complement of slices or cores for their intended applications. Additionally, it helps minimize waste in the manufacturing process, contributing to overall production efficiency.
In the embodiment depicted in
Although a specific embodiment for a conceptual illustration of a bifurcated die with two slices suitable for carrying out the various steps, processes, methods, and operations described herein is discussed with respect to
Referring to
In this way, it can be known that the functional area to be utilized within the die will always be on one portion of the processing unit 500. As a result, the substrate can be reconfigured to take advantage of this configuration. In the embodiment depicted in
Although a specific embodiment for a conceptual illustration of a rotatable die coupled with a substrate in a south slice rotation suitable for carrying out the various steps, processes, methods, and operations described herein is discussed with respect to
Referring to
As can be seen in the embodiment depicted in
Although a specific embodiment for a conceptual illustration of a rotatable die coupled with a substrate in a north slice rotation suitable for carrying out the various steps, processes, methods, and operations described herein is discussed with respect to
Referring to
In a number of embodiments, the process 700 can arrange the serialization/deserialization (SerDes) channels on a substrate (block 720). These SerDes channels on the substrate can correspond to the SerDes channels available on the die. As discussed above, various embodiments, may arrange the SerDes channels in a compressed or otherwise compact fashion, such as arranging them on one, two, or three sides of the substrate. In this way, the trace lengths needed to complete the SerDes channels can be reduced.
In more embodiments, the process 700 can couple the die with the substrate in a first orientation (block 730). As those skilled in the art will recognize, the coupling can be done during a manufacturing process where the die is seated or otherwise disposed on the substrate to complete a plurality of communication channels. The first orientation can be any suitable orientation to complete the communication channels between the die and the substrate. In some embodiments, a first orientation can be associated with a first slice of the die, while a second orientation can be associated with a second slice of the die.
In further embodiments, the process 700 can remove and rotate the die 180 degrees (block 740). In certain cases, a die may not be suitable for coupling at a first orientation. Thus, a new orientation may be needed, necessitating the die's removal from the substrate. In certain embodiments, the die may be bifurcated in a way that rotating the die one-hundred and eighty degrees can allow for the use of a different slice of the die. Specifically, in some embodiments, the first slice can be associated with a first orientation, and the second slice is associated with the second orientation, such that the first and second orientation are one-hundred eighty degrees relative to each other. In still more embodiments, the process 700 can recouple the substrate to the die (block 750). This recoupling can be done during the manufacturing process as well.
Although a specific embodiment for a process 700 for coupling a bifurcated die in a substrate in multiple orientations suitable for carrying out the various steps, processes, methods, and operations described herein is discussed with respect to
Referring to
In a number of embodiments, the process 800 can produce a die with a plurality of slices (block 820). The die can be configured with multiple slices or cores, wherein some may not be functional. To allow the continued use of these dies, the use of functional slices/cores may be utilized within other lower-cost products.
In some embodiments, the process 800 can determine that at least one slice is non-functional (block 830). This determination can be from running one or more tests after manufacturing the die. In certain embodiments, the functionality can be determined upon coupling the die with a substrate.
In further embodiments, the process 800 can position the die in a functional orientation (block 840). As discussed above, the substrate can be configured to allow functionality to one or more slice of the die. In order to facilitate this, the die can be positioned in an orientation that allows coupling such that the functional slice can be utilized and in communication with the substrate.
In more embodiments, the process 800 can couple the die to the substrate (block 850). The coupling can be done during the manufacturing process. Upon coupling the die in a certain position upon the reconfigured substrate, a plurality of SerDes and/or other communication channels can be completed such that the components within the die can be communicatively coupled with external components.
Although a specific embodiment for a process 800 for configuring a substrate for use with a bifurcated die suitable for carrying out the various steps, processes, methods, and operations described herein is discussed with respect to
Although the present disclosure has been described in certain specific aspects, many additional modifications and variations would be apparent to those skilled in the art. In particular, any of the various processes described above can be performed in alternative sequences and/or in parallel (on the same or on different computing devices) in order to achieve similar results in a manner that is more appropriate to the requirements of a specific application. It is therefore to be understood that the present disclosure can be practiced other than specifically described without departing from the scope and spirit of the present disclosure. Thus, embodiments of the present disclosure should be considered in all respects as illustrative and not restrictive. It will be evident to the person skilled in the art to freely combine several or all of the embodiments discussed here as deemed suitable for a specific application of the disclosure. Throughout this disclosure, terms like “advantageous”, “exemplary” or “example” indicate elements or dimensions which are particularly suitable (but not essential) to the disclosure or an embodiment thereof and may be modified wherever deemed suitable by the skilled person, except where expressly required. Accordingly, the scope of the disclosure should be determined not by the embodiments illustrated, but by the appended claims and their equivalents.
Any reference to an element being made in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described preferred embodiment and additional embodiments as regarded by those of ordinary skill in the art are hereby expressly incorporated by reference and are intended to be encompassed by the present claims.
Moreover, no requirement exists for a system or method to address each, and every problem sought to be resolved by the present disclosure, for solutions to such problems to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. Various changes and modifications in form, material, workpiece, and fabrication material detail can be made, without departing from the spirit and scope of the present disclosure, as set forth in the appended claims, as might be apparent to those of ordinary skill in the art, are also encompassed by the present disclosure.
