Differential amplifier

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a differential amplifier, and in particular to a differential amplifier having a resistance load type differential pair in an integrated circuit.

The differential amplifier is utilized in a large number of electric circuits regardless of technical fields, and many of these electric circuits are utilized in an integrated form such as an IC or LSI.

As for circuit parts such as transistors, only discrete parts which had fulfilled the specification have been shipped. Therefore, circuit designs for the discrete parts have been made possible without much consideration of manufacturing process conditions because of little individual differences between the parts. Only consideration focused on circumferential variations such as temperature in use had to be made. However, as demands for speedup and space saving increase in the market, the integration of the circuits has been urged.

Integrated circuit designs, considering a manufacturing yield, require circuit designs allowing individual differences between lots depending on manufacturing process conditions.

Furthermore, minute machining for IC's (or LSI's) has been energetically advanced in recent years for the purpose of the speedup and cost reduction. Along with this, source voltages of electric circuits tend to decrease. This is because a malfunction caused by an occurrence of a leak current or the like due to an insulator destruction with a high voltage is prevented since the thickness of an oxide film of a gate or the like is thinned by the minute machining, taking a CMOS transistor as an example.

Therefore, a direct current design at a low voltage considering variations of circumferential and manufacturing process conditions has become more and more difficult. Particularly, it is required for a differential amplifier in many cases, especially in such a case as performing a feed forward control, that the gain variation is small against the variations of the circumferential and manufacturing process conditions.

2. Description of the Related Art

For a bias current of a differential amplifier, a current source (constant current source) {circle around (

1

)} as shown in

FIG. 8

for suppressing a current amount variation caused by variations of circumferential conditions, a current source {circle around (

2

)} as shown in

FIG. 9

for suppressing an internal resistance variation in an amplifier having a resistance load type differential pair and suppressing a limiter amplitude variation, or. a current source {circle around (

3

)} as shown in

FIG. 10

for suppressing a small signal gain variation in an amplifier having a resistance load type differential pair has been so far used individually according to the object of use. Hereinafter, the respective operations will be described taking a CMOS transistor as an example.

Firstly, the current source (constant current source) {circle around (

1

)} shown in

FIG. 8

will be described. It is often the case that an integrated circuit IC

1

internally has a reference constant voltage source S

1

utilizing PN semiconductor junctions with an output voltage V

BGR

to the extent of 1.2V which is called a band gap reference (BGR), having an extremely little variation dependency on the variations of the circumferential and manufacturing process conditions.

This reference voltage V

BGR

is dropped by a voltage divider rl to an allowable input range of an operational amplifier OA

1

to make a reference potential V

ref

thereof. The operational amplifier OA

1

controls a transistor M

11

so that a potential R

c

×I

c

by a current I

c

which flows through a resistor r

2

(resistance R

c

) which is externally connected to the integrated circuit IC

1

is equal to the reference potential V

ref

. Thus, the current source {circle around (

1

)} of

FIG. 8

outputs a current determined by the following equation:

I

c

=V

ref

/R

c

Eq. (1)

It is to be noted that the reference voltage V

ref

has a little dependency on condition variations since it is generated from the voltage V

BGR

which has little dependency on the condition variations by a voltage division ratio of the resistor r

1

, which is constant even if the resistance varies. Also, the reference resistor r

2

has a very little temperature dependency of less than±several 100 ppm/° C. because of an externally connected component.

Since Eq. (1) includes no element depending on the source, no dependency on a source voltage arises as long as the operational amplifier OA

1

or the like has a range of source voltage where a normal operation is enabled. Therefore, a constant current I

c

determined by Eq. (1) which has a very little dependency on the condition variations can be obtained. The current I

c

is reproduced as a current I

d

by a current mirror CM

1

which is composed of transistors M

12

, M

14

, M

13

, and M

15

so as to be provided as a bias current I

s

to a differential pair of an amplifier (not shown) of a resistance load type.

On the other hand, it is generally known that a small signal gain G of an amplifier having a resistance load type differential pair is expressed by the following equation:

G=R×{square root over ( )}β×{square root over ( )}I

s

Eq. (2)

[R: load resistance, β: gain coefficient of MOS-FET, I

s

: bias current value]

[β=μ·C

ox

·W/L (μ: electron mobility, C

ox

: gate oxide film capacity, W: gate width, L: gate length)]

Namely, supposing that an input potential difference of the differential pair is v

in

, an output signal amplitude of v

in

×G is generated between a load resistor (not shown) and the differential pair.

Also, a limiter amplitude V

lm

(V

in

×G≦V

lm

) which is a maximum output amplitude generated between the load resistor and the differential pair is expressed by the following equation:

V

lm

=R×I

s

Eq. (3)

In view of an integrated circuit having a resistance element in the manufacturing process, the load resistance R and the gain coefficient β vary as the circumferential and manufacturing process conditions vary as given by the following equations:

R=R

typ

(1±Δ

r

) Eq. (4)

β=β

typ

(1±Δ

B

) Eq. (5)

where R

typ

and β

typ

indicate design values in a circumferential condition which is most frequently used and in a manufacturing process condition (typical condition) which is best achieved, and Δ

r

and Δ

B

indicate variation amounts when the values are off the circumferential and manufacturing conditions.

It is to be noted that upon a circuit design, Δ

r

and Δ

B

are preliminary given to each manufacturing process used from conditions such as a working temperature range and a manufacturing yield according to the design specification. In addition, although Δ

r

and Δ

B

have a correlation with the temperature variation in some manufacturing processes, it may be generally considered that they vary independently of the condition variations.

Accordingly, the small signal gain G and the limiter amplitude V

lm

of the amplifier having the resistance load type differential pair given by Eqs. (2) and (3) are given by the following equations in consideration of the condition variations.

G=R

typ

×{square root over ( )}β

typ

×{square root over ( )}I

s

×(1±Δ

r

)×(1±Δ

B

)

0.5

Eq. (6)

V

lm

=R

typ

×I

s

×(1±Δ

r

) Eq. (7)

Therefore, when the current I

d

generated by the constant current source {circumflex over (1)} in

FIG. 8

is provided as the bias current I

s

(=constant) to the differential pair, Eqs. (6) and (7) can be respectively rewritten as the following equations:

G=G

typ

×(1±Δ

r

)×(1Δ

B

)

0.5

Eq. (8)

[G

typ

=R

typ

×{square root over ( )}β

typ

×{square root over ( )}I

s

=constant]

V

lm

=V

typ

×(1±Δ

r

) Eq. (9)

[V

typ

=R

typ

×I

s

=constant]

Namely, it is found that both of the small signal gain G and the limiter amplitude V

lm

vary with the condition variations.

This kind of current source is mostly used as a bias for a resistance load type differential pair utilizing an external resistor in a manufacturing process for such as a part of a bipolar and a gallium-arsenic series which has no resistance element excluding considerations of resistance variation or for a pair having an active load type differential pair which utilizes an internal resistor of a transistor and which is not suitable for an analog amplification due to an extremely high gain in many cases.

The current source {circle around (2)} shown in

FIG. 9

for suppressing or compensating an internal resistance variation in an amplifier (not shown) having a resistance load type differential pair will now be described.

This resistance variation suppressing type current source {circle around (2)} can be provided by replacing the external reference resistor r

2

in

FIG. 1

with an internal resistor in an integrated circuit IC

2

for the suppressing resistor of the constant current source.

Therefore, in this resistance variation suppressing type current source {circle around (2)}, an operational amplifier OA

2

controls a transistor M

21

so that a voltage drop=R

ic

×I

r

by a current I

r

flowing through a reference resistor r

3

of a resistance R

ic

within the integrated circuit IC

2

is equal to the reference potential V

ref

. Thus, the current source {circle around (2)} of

FIG. 9

outputs a current determined by the following equation:

I

r

=V

ref

/R

ic

Eq. (10)

It is to be noted that the reference potential V

ref

has a little dependency on condition variations. Since Eq. (10) includes no element depending on the source, no dependency on a source voltage arises as long as the operational amplifier OA

2

or the like has a range of source voltage where a normal operation is enabled. However, R

ic

presents a variation similar to Eq. (4) against the condition variations as expressed by the following equation:

R

ic

=r

typ

(1Δ

r

) Eq. (11)

When the current I

r

in the above-mentioned Eq. (10) by the resistance variation suppressing type current source {circle around (2)} is provided as the bias current I

s

to the differential pair, the following equation is given:

I

r

=I

s

/(1±Δ

r

) Eq. (12)

[I

s

=(kV

ref

/r

typ

=constant),

k: constant determined by current mirror ratio and the like]

Accordingly, by using Eqs. (2) and (3), the small signal gain G and the limiter amplitude V

lm

of the differential amplifier are respectively expressed by the following equations:

G=R×{square root over ( )}β×{square root over ( )}I

r

=G

typ

×(1±Δ

r

)

0.5

×(1±Δ

B

)

0.5

Eq. (13)

[G

typ

=R

typ

×{square root over ( )}β

typ

×{square root over ( )}I

s

=constant]

V

lm

=R×I

r

=V

typ

(=constant) Eq. (14)

[V

typ

=R

typ

×I

s

=constant]

Namely, it is understood that while the small signal gain G varies with the condition variation, the limiter amplitude V

lm

is kept constant. This kind of current source is often used as a bias for the last staged differential pair (slicer circuit) of an analog amplifier since it keeps the output signal amplitude constant.

The current source {circle around (3)} shown in

FIG. 10

for suppressing a small signal gain variation in an amplifier having a resistance load type differential pair will now be described. In Eq. (2), suppressing the variation of the small signal gain G can require the current value I

s

of the bias current source to vary in proportion to 1/R

2

and 1/β to cancel the variations of R and β. In

FIG. 10

, it is supposed that a suppressing transistor M

32

has a gate whose width is “N” times as wide as that of a suppressing transistor M

31

, while otherwise both are the same. At this time, currents I

31

and I

32

which respectively flow through the transistors M

31

and M

32

are approximately expressed as the following equations:

I

31

=(β/2)×(Vgs

31

−Vt)

2

Eq. (15)

I

32

=(Nβ/2)×(Vgs

32

−Vt)

2

Eq. (16)

[Vgs

31

, Vgs

32

: voltages between the gate and source of M

31

and M

32

,

Vt: threshold value of CMOS transistor]

Potentials at points A and B in

FIG. 10

are dropped to an appropriate voltage through a source follower

11

composed of transistors M

3

-M

10

including a current mirror CM

32

and controlled to be mutually equal by an operational amplifier OA

3

and transistors M

31

-M

34

. Since a potential difference between Vgs

31

and Vgs

32

is applied across the ends of a suppressing resistor r

4

(resistance r), the following equation can be obtained.

Vgs

31

−Vgs

32

=r×I

32

×{square root over ( )}(2I

31

/β)−{square root over ( )}{2I

32

/(Nβ)} Eq. (17)

Also, since the points A and B have the same potential, the currents I

31

and I

32

which respectively flow through R

31

and R

32

of the same resistance have the same value. Accordingly, a current I

33

flowing through a current source transistor M

33

is expressed with a calculation constant k

1

, a variation component of the resistance r of the resistor r

4

, and a variation component of the gain coefficient β using Eq. (17) as given by the following equation: (It is to be noted that another solution of Eq. (17), which is I

33

=0, lets a start-up circuit

10

composed of transistors M

35

and M

36

flow a start-up current I

ST

through the transistors M

35

and M

36

by a current mirror CM

31

, thereby prohibiting the state where no current flows through the suppressing transistors M

31

and M

32

.)

I

33

=I

31

+I

32

(=2I

32

)=((4/(r

2

β))(1−1/{square root over ( )}N)

2

=k

1

/{R

typ

2

(1±Δ

r

)

2

×β

typ

(1±Δ

B

)} Eq. (18)

Accordingly, the current expressed by Eq. (18) varying in proportion to 1/R

2

and 1/β is used as a bias current I

g

for a differential amplifier (not shown) by a current mirror (a current mirror CM

33

having a ratio k

2

and composed of the operational amplifier OA

3

and transistors M

31

-M

34

, M

37

, and M

38

) given by the following equation:

I

g

=k

2

×I

33

=I

s

/{(1±Δ

r

)

2

×(1±Δ

B

)} Eq. (19)

[I

s

=4(1−1/{square root over ( )}N)

2

/{r

typ

2

×β

typ

}=constant]

Thus, the small signal gain G and the limiter amplitude V

lm

are respectively expressed by the following equations from Eqs. (2) and (3):

G=R×{square root over ( )}β×{square root over ( )}I

g

=G

typ

(=constant) Eq. (20)

[G

typ

=R

typ

×{square root over ( )}β

typ

×{square root over ( )}I

s

=constant]

V

lm

=R×I

g

=V

typ

/{(1±Δ

r

)×(1±Δ

B

)} Eq. (21)

[V

typ

=R

typ

×I

s

=constant]

Namely, while the limiter amplitude V

lm

varies with condition variations, the small signal gain G is kept constant. Moreover, since Eqs. (19)-(21) include no element depending on the source, no dependency on a source voltage arises as long as the operational amplifier OA

3

or the like has a range of source voltage where a normal operation is enabled.

It is to be noted that since the arrangement example of

FIG. 10

performs a suppression of variation for an N-type differential pair, a suppression of variation for a P-type differential pair can be performed in the same arrangement by replacing the N-type transistor with the P-type, the source with the earth, the earth with the source, and the like.

A resistance load type differential pair using this kind of current source as a bias circuit can provide a linear output amplitude in response to an input amplitude even under the conditions varying. Therefore, it is frequently used in a circuit, where an analog linear amplification of a small signal is regarded as important, such as a circuit for performing a separation of S/N (Signal/Noise), i.e. a comparison of a constant identification potential with a signal amplitude of V

in-pp

×G after the amplification.

It is important for such an analog integrated circuit design to fulfill the following requirements:

Requirement 1:

Low voltage operation (minute machining of manufacturing process)

Requirement 2:

High speed operation (enhancement of signal band)

Concerning the “Requirement 1”, as the minute machining of IC's or LSI's has made a further progress in recent years for the purpose of the cost reduction, the source voltage of an integrated circuit has been reduced than before to the extent of e.g. 3V. Although being preferable from a viewpoint of low power consumption, this has resulted in much burden to the direct current design not requiring much consideration therefor.

As an example, this has become remarkable especially in case of an analog linear amplification. In the analog linear amplification, it is important for the purpose of suppressing the signal deterioration caused by wave distortions and the like to use all of the transistors composing the differential pair in the saturating operation, that is to use them over a range of voltage between the drain and the source where the variation of the current therebetween the drain and the source is extremely small with respect to the variation of the voltage Vds therebetween in case of CMOS transistors.

The direct current designs for the resistance load type differential pair are applied to the differential pair itself and the input/output levels of the differential pair.

This will be described hereinafter referring to FIG.

11

. Firstly, the following equation is given for the differential pair itself.

V

dd

(source voltage)≧R×I

s

+V

ds-min

(differential pair)+V

ds-min

(bias source) Eq. (22)

[V

ds-min

: minimum required voltage between drain and source for saturating operation]

Moreover, a relation of the following equation is required for an input signal level of differential pairs

41

and

43

.

V

in-min

(minimum signal input voltage)≧V

t

(differential pair)+V

ds-min

(bias source) Eq. (23)

[V

t

: threshold potential of transistor]

In the above Eq. (23), the purpose of considering V

t

of the differential pair is to suppress the wave distortions by realizing an instantaneous output response to an input since little current flows through the transistor at the voltage of V

t

or below.

Also, concerning the minimum signal input voltage V

in-min

, an amplifier often employs multi-staged differential pairs

41

and

43

as shown in

FIG. 11

which are mutually connected with a buffer such as a source follower

45

or an emitter follower. Accordingly, an input level between each differential pair (differential pair

43

) after the first stage is expressed by the following equation:

V

in-min

=V

dd

−R×I

s

−V

gs

(output voltage drop of source follower) Eq. (24)

Accordingly, the following equation is given by substituting Eq. (23) for Eq. (24).

V

dd

−R×I

s

×V

gs

(source follower)≧V

t

(differential pair)+V

ds-min

(bias source) V

dd

≧R×I

s

+V

gs

(source follower)+V

t

(differential pair)+V

ds-min

(bias source) Eq. (25)

Accordingly, since the “Requirement 1” means that the upper limit V

dd

becomes low in Eqs. (22) and (25) expressing the conditions for the direct current design, the limiter amplitude R×I

s

(see Eq. (3)) is restricted in Eq. (25), thereby making the direct current design difficult.

Also, the enhancement of the signal band in the “Requirement 2” requires improvements of the output signal band determined by the load resistance R and a parasitic capacitance C of the transistors composing the differential pairs

41

and

43

, and of the through-rate determined by the next stage input load such as a gate capacitance with respect to a driving ability (bias current amount) of the differential pairs

41

and

43

.

This means, in the circuit design, the increase of the bias current and the decrease in size of the transistors composing the differential pair, that is the increase of a current density between the drain and the source leads to the increase of the minimum potential V

ds-min

between the drain and the source required for the saturating operation, so that the limiter amplitude R×I

s

shown in Eq. (3) is also restricted in Eq. (25), thereby making the direct current design difficult.

Examples of general numerical values in Eq. (25) for a CMOS manufacturing process are shown in the following Table 1.

TABLE 1

Numerical value examples for CMOS manufacturing process

ITEM

SYMBOL

VOLTAGE (V)

REMARKS

SOURCE

V

dd

3.0-5.0

3 V IN GENERAL

VOLTAGE

THRESHOLD

V

t

0.5-1.0

PROCESS MINIMUM

VOLTAGE

MEASUREMENT

SATURATED

V

ds-min

DESIGNED TO BE

DEPENDENT ON

DRAIN

1.0 OR BELOW

CURRENT DENSITY

SOURCE

POTENTIAL

According to Table 1, supposing V

dd

=3V, V

gs

−V

t

=0.8V and V

ds-min

=0.4V in Eq. (25), the limiter amplitude R×I

s

requires to be 1V or less including the variation.

Accordingly, the limiter amplitudes will now be considered in case the current sources {circle around (1)}-{circle around (3)} shown in

FIGS. 8-10

are used for a bias current I

s

of the differential pairs

41

shown in FIG.

11

. Particularly for the analog linear amplification, it is important to enlarge the limiter amplitude in respect of securing the input dynamic range.

In the prior art shown in

FIGS. 8-10

, except for the contents to be suppressed as the objects of the current source in use, the values thereof vary greatly with the variations of the circumferential and manufacturing process conditions (variations of Δ

r

and Δ

B

).

The variation tendencies can be calculated by Eqs. (8), (9), (13), (14), (20), and (21) as shown in the following Table 2. Also,

FIG. 12

shows a small signal gain variation characteristic as the resistance R is varied,

FIG. 13

shows a small signal gain variation characteristic as the gain coefficient β is varied,

FIG. 14

shows a limiter amplitude variation characteristic as the resistance R is varied, and

FIG. 15

shows a limiter amplitude variation characteristic as the gain coefficient β is varied.

TABLE 2

Δ

r

and Δ

B

dependencies of small signal gain and limiter

amplitude by current source types

CURRENT

SOURCE

SMALL SIGNAL GAIN

LIMITER AMPLITUDE

TYPE

VARIATION: G/G

typ

VARIATION: V/V

typ

CURRENT

(1 ± Δ

r

) × (1 ± Δ

b

)

0.5

1 ± Δ

r

VARIATION

SUPPRESSING

TYPE

{circle around (1)}

RESISTANCE

(1 ± Δ

r

)

0.5

× (1 ± Δ

B

)

0.5

1

VARIATION

SUPPRESSING

TYPE

{circle around (2)}

GAIN VARIATION

1

1/[(1 ± Δ

r

) × (1 ± Δ

B

)]

SUPPRESSING

TYPE

{circle around (3)}

From the above, in the direct current design considering the variations of the circumferential and manufacturing process conditions, the maximum limiter amplitude at the time of condition variations is supposed to be R×I

s

in Eq. (25) as described above so that the limiter amplitude under the typical condition is made small by the amount of variation. Accordingly, it is found that the largest limiter amplitude can be secured when the resistance variation suppressing type current source {circle around (2)} without limiter amplitude variations is used as the bias for the differential pair.

However, as described above, since the analog linear amplification has often an object of the separation of S/N or a faithful reproduction of the input, it is also important to suppress the small signal gain variation.

However, as shown in Table 2 and

FIGS. 10-13

, in case the current sources are independently used, it is not possible to suppress both of the small signal gain variation and the limiter amplitude variation, or to satisfy G/G

typ

=1 and V/V

typ

=1 at the same time against the variations of the circumferential and manufacturing process conditions. Therefore, it is to be urged to select an extreme improvement of one of the variations while worsening the variation of the other.

It has been possible in the prior art to secure the limiter amplitude even if the gain variation suppressing type current source {circle around (3)} is solely used since the source voltage in use has been relatively high to the extent of 5V allowing a margin for the direct current design.

In a general circuit design, allowable values for design parameters are determined according to specification or the like. Also, in an amplifier design, an allowable gain variation Δ

pg

and an allowable limiter amplitude variation Δ

pl

can be calculated according to the design specification or the like, the allowable values depending on the place and object of the circuit.

If the current sources for different objects to be suppressed are independently used as in prior art, even though one of the variations of the gain and the limiter amplitude caused by the condition variations may have a margin with respect to the corresponding allowable variation, the other may not, which leads to the failure of the design proper.

As described above, in the design of the differential pair for the analog linear amplifier where the current sources for different objects to be suppressed, i.e. the limiter amplitude or the small signal gain, are independently used as in the prior art, there is a problem that it has become difficult to deal with the reduction of the source voltage following the minute machining of integrated circuits, the speedup of circuit operations, and the variations of circumferential and manufacturing process conditions in recent years, while enabling both of the design for suppressing the gain variation and the direct current design for securing the input dynamic range (limiter amplitude).

SUMMARY OF THE INVENTION

It is accordingly an object of the present invention to provide an amplifier having a differential pair of an integrated resistance load type with a bias current source suppressing a gain variation and a limiter amplitude (or direct current level) variation caused by variations of circumferential conditions such as a temperature and source voltage, manufacturing process conditions, and the like.

In the differential amplifier according to the present invention, a bias current I

g

for suppressing the gain variation of a resistance load type differential pair against the variations of the circumferential and manufacturing process conditions and a bias current I

r

for suppressing an output limiter amplitude variation against the variations of conditions as described above are mixed at a constant ratio in consideration of an allowable gain variation Δ

pg

and an allowable limiter amplitude variation Δ

pl

calculated from a design specification or the like under a circumferential condition which is most frequently used and a manufacturing process condition which is best achieved (typical condition) to obtain a current I

m

which is reproduced using a current mirror or the like. The reproduced current is used as a bias current I

s

of the resistance load type differential amplifier.

This enables, without extremely improving one of the variations while worsening the other as in the prior art, an appropriate distribution of variations to be performed corresponding to each allowable value and both of the gain design and the direct current design for the resistance load type differential pair to be compatible.

Namely, supposing that the ratio of the bias current I

r

for suppressing the limiter amplitude variation to the bias current I

g

for suppressing the small signal gain variation against the variations of the circumferential and manufacturing process conditions is α: 1−α where 0<α<1 under the typical condition, the mixed current I

m

can be expressed by the following equation by using Eqs. (12) and (19):

I

m

=αI

r

+(1−α)I

g

=I

s

[α/(1±Δ

r

)+(1−α)/{(1±Δ

r

)

2

×(1±Δ

B

)}] Eq. (26)

It is to be noted that “α=1” corresponds to a case where the limiter amplitude variation suppressing current is solely used while “α=0” corresponds to a case where the small signal gain variation suppressing current is solely used.

The current of this Eq. (26) is provided as a bias current source of the resistance load type differential pair. Since the small signal gain G and the limiter amplitude V

lm

under the varying conditions are given by Eqs. (6) and (7), when the current I

m

of Eq. (26) is applied to them, the small signal gain variation and the limiter amplitude variation are respectively given by the following Eqs. (27) and (28):

G/G

typ

=1±Δ

G

=[α×(1±Δ

r

)×(1±Δ

B

)+(1−α)]

0.5

Eq. (27)

[G

typ

=R

typ

×{square root over ( )}β

typ

×{square root over ( )}I

s

=constant, Δ

G

: small signal gain variation]

V/V

typ

=1±Δ

Vl

=[α+(1−α)/{(1±Δr)×(1±ΔB)}] Eq. (28)

[V

typ

=R

typ

×I

s

, Δ

Vl

: limiter amplitude variation]

In the above-mentioned Eqs. (27) and (28), if the value of α is determined so that the small signal gain variation Δ

G

and the limiter amplitude variation Δ

Vl

may respectively satisfy the allowable gain variation Δ

pg

and the allowable limiter amplitude variation Δ

pl

, both of the gain design and the direct current design of the resistance load type differential pair are made compatible.

It is to be noted that the above-mentioned resistance load type differential pair may have cascode transistors between load resistors and transistors composing the differential pair.

Also, the present invention may comprise a second resistance load type differential pair for inputting the output of the above-mentioned differential pair preferably through a source follower or an emitter follower and may use, as a bias current source of the second differential pair, a resistance variation suppressing type current source for generating a constant current which varies to suppress the limiter amplitude variation.

Also, the current output terminals of the other differential pair may be mutually connected with a resistor.

The present invention may further comprise a peak and a bottom detector which respectively detect a peak and a bottom value of an input signal, and a voltage divider which divides the output voltages of both detectors to generate a threshold signal, wherein the input signal and the threshold signal are given to the differential pair at the first stage.

Moreover, the transistors composing the current mirror may have cascode transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a circuit diagram illustrating an embodiment (1) of a differential amplifier according to the present invention;

FIG. 2

is a graph illustrating a small signal gain variation characteristic versus resistance × gain coefficient variation of a differential amplifier according to the present invention;

FIG. 3

is a graph illustrating a limiter amplitude variation characteristic versus resistance × gain coefficient variation in a differential amplifier according to the present invention;

FIG. 4

is a circuit diagram illustrating an embodiment (2) of a differential amplifier according to the present invention;

FIG. 5

is a circuit diagram illustrating an embodiment (3) of a differential amplifier according to the present invention;

FIG. 6

is a circuit diagram illustrating an embodiment (4) of a differential amplifier according to the present invention;

FIG. 7

is a circuit diagram illustrating an embodiment (5) of a differential amplifier according to the present invention;

FIG. 8

is a circuit diagram illustrating a prior art constant current source having an external reference resistor;

FIG. 9

is a circuit diagram illustrating a prior art current source of a resistance variation suppressing type;

FIG. 10

is a circuit diagram illustrating a prior art current source of a gain variation suppressing type;

FIG. 11

is a diagram illustrating a circuit example of a prior art differential amplifier of a resistance load type;

FIG. 12

is a graph illustrating a prior art small signal gain variation characteristic under varying resistance;

FIG. 13

is a graph illustrating a prior art small signal gain variation characteristic under varying gain coefficient;

FIG. 14

is a graph illustrating a prior art limiter amplitude variation characteristic under varying resistance; and

FIG. 15

is a graph illustrating a prior art limiter amplitude variation characteristic under varying gain coefficient.

Throughout the figures, the same reference numerals indicate identical or corresponding portions.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1

shows an embodiment (1) of a differential amplifier according to the present invention. In this embodiment, a resistance variation suppressing current source CS

1

and a gain variation suppressing current source CS

2

are connected in parallel and a current mirror CM

5

is used as a bias current source

52

for providing a bias current I

53

to a differential pair

51

which is composed of transistors M

51

and M

52

by reproducing a mixed current I

m

of both current sources CS

1

and CS

2

expressed by the above-mentioned Eq. (26). This current mirror CM

5

has cascode transistors M

54

and M

56

respectively added to transistors M

53

and M

55

.

This embodiment adopts, as described above, a value of α which is selected so that the small signal gain variation Δ

G

and the limiter amplitude variation Δ

Vl

in Eqs. (27) and (28) may respectively satisfy the allowable gain variation Δ

pg

and the allowable limiter amplitude variation Δ

pl

and a design value I

s

for a bias current I

53

of an amplifier having a resistance load type differential pair under a typical condition. Currents I

51

and I

52

from the reference current sources CS

1

and CS

2

respectively shown in

FIGS. 9 and 10

are mixed to be provided to the current mirror CM

5

so that the bias current I

52

suppressing the gain variation may amount to “(1×α)×I

s

” and the bias current I

51

suppressing the limiter amplitude variation may amount to “α×I

s

” under the typical condition (I

g

=I

r

=I

s

).

Specifically in this embodiment, when Δ

r

and Δ

B

are considered to be independent in the above-mentioned Eqs. (13), (14), (20), (21), (27), and (28), a small signal gain variation is shown in

FIG. 2 and a

limiter amplitude variation is shown in

FIG. 3

for a resistance variation × gain coefficient variation Δ

rB

which can be regarded as:

1±Δ

rB

=(1±Δ

r

)×(1±Δ

B

) Eq. (29)

Supposing that the resistance variation × gain coefficient variation Δ

rB

is +40% and both of the allowable gain variation Δ

pg

and the allowable limiter amplitude variation Δ

pl

are ±20% as shown by dotted lines in

FIGS. 2 and 3

, when the current sources for different objects to be suppressed (the limiter amplitude or the small signal gain) are solely used as marked with symbols Δ and ∘ in

FIGS. 2 and 3

, neither satisfies both of the allowable values at the same time. However, in this embodiment, although both of the allowable variations Δ

pg

and Δ

pl

cannot be satisfied at the same time when α=0.25 as marked with a symbol &Circlesolid; and α=0.5 as marked with a symbol ▴, it is found that both of the allowable values are satisfied at the same time by setting α=0.75 as marked with a symbol ▪, thereby enabling both of the gain design and the direct current design to be compatible.

By the above-mentioned arrangement, both of the gain design and the direct current design for the resistance load type differential pair which deals with the variations of conditions are made possible even under a low source voltage.

It is to be noted that the cascode transistors M

54

and M

56

are used in the current mirror CM

5

of this embodiment for improving the accuracy of the current mirror CM

5

by suppressing the variations of the drain potentials of the current source transistors M

53

and M

55

which are in charge of transferring the current in the current mirror CM

5

.

Especially in a CMOS transistor, since the resistance between the source and the drain is as low as several MΩ's depending on the manufacturing process, a current which flows between the source and the drain is easy to vary as the drain potential varies. However, they are not necessary if the resistance between the source and the drain can be made sufficiently high in the manufacturing process.

FIG. 4

shows an embodiment (2) of a differential amplifier according to the present invention. In this embodiment, transistors M

61

-M

66

and load resistors R

61

, R

62

respectively correspond to the transistors M

51

-M

56

and the load resistors R

51

, R

52

in the embodiment (1) of FIG.

1

. However, in this embodiment, transistors M

67

and M

68

having a gate or base grounded are inserted between the load resistors R

61

, R

62

of a differential pair

61

and the differential pair transistors M

61

, M

62

so that parasitic capacitances of the differential pair transistors M

61

and M

62

are not directly observed from the load resistors R

61

and R

62

, thereby suppressing the band deterioration.

FIG. 5

shows an embodiment (3) of a differential amplifier according to the present invention. In this embodiment, transistors M

71

-M

78

and load resistors R

71

, R

72

respectively correspond to the transistors M

61

-M

68

and load resistors R

61

, R

62

in the embodiment (2) of FIG.

4

. However, in this embodiment, supposing that the differential amplifier is used as a slicer, a differential pair

73

using only a bias current I

74

by a bias current source

74

for suppressing the resistance variation is connected to the output terminal of the differential pair

71

(

61

in the embodiment (2)) through a voltage dropping source (or emitter) follower

75

which is composed of transistors M

715

, M

716

and current sources CS

3

, CS

4

in order to keep an output amplitude (limiter amplitude) constant as in the case of FIG.

11

.

The bias current source

74

reproduces the constant current I

74

at a current mirror CM

72

composed of transistors M

711

-M

714

to provide as a bias current I

r

for the differential pair

73

. A direct current design for an input of the differential pair

73

is given by the above-mentioned Eq. (25). In case the differential pairs are used in the form of multi-stage, such a form is required from the viewpoint of a gain stability and a direct current level setting.

FIG. 6

shows an embodiment (4) of a differential amplifier according to the present invention. In this embodiment, transistors M

81

-M

89

, M

810

-M

814

, M

817

, M

818

, and load resistors R

81

-R

84

respectively correspond to the transistors M

71

-M

79

, M

710

-M

714

, M

715

, M

716

, and the load resistors R

71

-R

74

in the embodiment (3) of FIG.

5

. However, in this embodiment, a source resistor R

85

is connected between the source terminals of the transistors M

89

and M

810

of a differential pair

83

, and a bias current I

86

(=I

85

) is flown though transistors M

815

and M

816

in parallel with a bias current I

85

flowing through the transistors M

813

and M

814

composing a current mirror CM

82

.

This arrangement realizes the current mirror CM

82

providing a half or so of a current source (I

s

/2) of a conventional differential pair in order that a current value of the transistors M

815

and M

813

composing a bias current source connected across the ends of the source resistor R

85

maintains the output direct current level.

Namely, when using a differential amplifier as a slicer as in the above-mentioned embodiment (3), there is a case where stabilizing the output limiter amplitude is the only object so that while a sufficient gain is obtained solely by a first stage differential pair

81

, no gain is desirable to be obtained by a second stage differential pair

83

. In this case, since the second stage differential pair

83

obtains a gain of

6

dB due to a differential input, the second stage differential pair

83

is required to perform a low gain amplification such as −6 dB by a one-sided input.

A small signal gain G

s

of the differential pair

83

with the source resistor used in such an arrangement is expressed by the following equation where the source resistance is R

s

:

G

s

=g

m

×R

l

/(1+g

m

×R

s

) Eq. (30)

[g

m

={square root over ( )}β×{square root over ( )}I

s

, R

l

: load resistance, R

s

: source resistance]

From Eq. (30), it is understood that the small signal gain G

s

of the differential pair

83

is determined approximately by a ratio R

l

/R

s

of the load resistor R

83

or R

84

to the source resistor R

85

when g

m

or R

s

is sufficiently large whereby a low gain can easily be obtained.

FIG. 7

shows an embodiment (5) of a differential amplifier according to the present invention. In this embodiment, transistors M

91

-M

99

, M

910

-M

918

, and load resistors R

91

-R

95

respectively correspond to the transistors transistor M

81

-M

89

, M

810

-M

818

, and the load resistors R

81

-R

85

in the embodiment (4) of FIG.

6

. However, in this embodiment, a peak detector

96

and a bottom detector

97

for an input signal V

in

, as well as voltage dividers R

96

and R

97

composing a voltage divider portion detect a threshold e.g. a middle value between a peak and bottom value of the input signal in the form of feed forward, and provide the threshold to one input of the first stage differential pair in the above embodiments while providing the same to the other input, for the signal amplification.

Namely, in case of performing a certain type of an identification such as separation of S/N in relation to a signal amplified in the form of feed forward, the gain variation is desirable to be as little as possible within the range of the linear amplification. In this embodiment, by a differential amplification of the input signal based on the threshold detected by the voltage dividers R

96

and R

97

, the gain is decreased for the signal with a high input level and the gain is increased to the contrary for the signal with a low input level, thereby enabling the direct current design under a low voltage while suppressing the gain variation.

It is to be noted that in the above-mentioned embodiments, although CMOS transistors have been used in all the descriptions, the same arrangements are also made possible by bipolar transistors. In addition, although amplifiers have been described as N type, arrangements with P type are also made possible, so that in the embodiments (3) and (4), the combination of N type for the first stage differential pair and P type for the second stage differential pair or vice versa is made possible.

As described above, a differential amplifier according to the present invention is arranged such that a constant current which varies to suppress a small signal gain variation of a resistance load type differential pair caused by variations of circumferential conditions and manufacturing process conditions and a constant current which varies to suppress a limiter amplitude variation of the resistance load type differential pair caused by the variations of the same conditions are mixed at a fixed ratio under a condition which is most frequently used among the circumferential conditions and a condition which is best achieved among the manufacturing process conditions, which is used as a bias current of the differential pair. Therefore, an appropriate distribution of variations becomes possible between the gain variation and the limiter amplitude variation to enable a design of an amplification circuit having a resistance load type differential pair which deals with the variation of conditions even under a low source voltage following a minute machining of integrated circuits in recent years.

Number	Name	Date
3643183	Geffe	Feb 1972
4553107	Ogawa	Nov 1985
4887048	Krenik et al.	Dec 1989
4893092	Okamoto	Jun 1993
5220289	Kunitaka	Jun 1993

Differential amplifier

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

Priority Claims (1)

US Referenced Citations (5)

Foreign Referenced Citations (1)