Bazes, Mel, et al., "A Novel CMOS Digital Clock and Data Decoder," IEEE Journal of Solid-State Circuits, Dec. 1992, vol. 27, No. 12, pp. 1934-1940. |
Bazes, Mel, "A Novel Precision MOS Synchronous Delay Line," IEEE Journal of Solid-State Ciruits, Dec. 1985, vol. SC-20, No. 6, pp. 1265-1271. |
Cordell, Robert R., et al., "A 50 MHz Phase-and Frequency-Locked Loop," IEEE Journal of Solid-state Circuits, Dec. 1979, vol. SC-14, No. 6, pp. 1003-1009. |
Gardner, Floyd M., "Charge-Pump Phase-Lock Loops," IEEE Transactions on Communications, Nov. 1980, vol. COM-28, No. 11, pp. 1849-1858. |
Jeong, Deog-Kyoon, et al., "Design of PLL-Based Clock Generation Circuits," IEEE Journal of Solid-State Circuits, Apr. 1987, vol. SC-22, No. 2, pp. 255-261. |
Johnson, Mark G., et al., "A Variable Delay Line PLL fo CPU-Coprocessor Synchronization," IEEE Journal of Solid-State Circuits, Oct. 1988, vol. 23, No. 5, pp. 1218-1223. |
Sun, Sam Yinshang, "An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance," IEEE Journal of Solid-State Circuits, Apr. 1989, vol. 24, No. 2, pp. 325-330. |
Young, Ian A., et al., "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE Journal of Solid-State Circuits, Nov. 1992, vol. 27, No. 11, pp. 1599-1607. |