Embodiments of the present invention now will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. The present invention can, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout this application.
It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
The first and second load circuits 10 and 20 can be implemented with a resistor. For example, the first load circuit 10 includes a resistor R31, and the second load circuit 20 includes a resistor R32, in this embodiment. The first and second load circuits 10 and 20 can be implemented with other circuit elements, such as transistors, etc, which can function as a load.
The differential switching circuit 30 can include N-type metal-oxide semiconductor (NMOS) transistors NT31 and NT32. The NMOS transistor NT31 receives a first differential input signal VIn+, and the NMOS transistor NT32 receives a second differential input signal VIn−. The differential switching circuit 30 can be implemented with more than two NMOS transistors that receive the first differential input signal VIn+, and more than two NMOS transistors that receive the second differential input signal VIn−.
The NMOS transistors NT31 and NT32 employ a thick gate oxide that can endure a voltage level of the high power supply voltage VDDH.
The equalizer 40 includes a bandwidth control unit 50 and an equalizer control unit 60.
The bandwidth control unit 50 includes a variable capacitor Ceq and a variable resistor Req that are coupled in parallel to each other between source electrodes of the NMOS transistors NT31 and NT32. The bandwidth control unit 50 controls a bandwidth of first and second differential output signals VOut+ and VOut− in response to a bandwidth control signal from a controller (not illustrated). The variable capacitor Ceq can include a plurality of capacitors that are coupled in parallel, and provide a capacitance in response to a control signal. The variable resistor Req can include a plurality of resistors that are coupled in series, and provide a resistance in response to a control signal.
The equalizer control unit 60 can include an NMOS transistor NT33 that is coupled between the source electrodes of the NMOS transistors NT31 and NT32. The NMOS transistor NT33 is turned on/off in response to an equalizer control signal applied to a gate of the NMOS transistor NT33 from the controller (not illustrated). Two terminals of the NMOS transistor NT33 are short-circuited or opened when the NMOS transistor NT33 is turned on or turned off, and thus the bandwidth control unit 50 affects or does not affect on the differential switching circuit 30. The NMOS transistor NT33 can employ a thin gate oxide.
The current source 70 can include NMOS transistors NT34 and NT35, which can be low-voltage NMOS transistors. The transistors NT34 and NT35 have gates that are coupled to a bias voltage Vc, and operate in a saturation region. A magnitude of the constant current provided by the transistors NT34 and NT35 can be determined by the bias voltage Vc. The current source 70 can be implemented with any other circuit element that functions as a current source. For example, the current source 70 can be replaced by a load circuit including a resistor. Bodies of the NMOS transistors in
The differential circuit of
Referring to
Referring to
The first and second pre-stage load circuits 310 and 320 can be implemented with resistors R51 and R52, respectively.
While the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the invention. For example, the first and second pre-stage load circuits 310 and 320 can be implemented with other circuit elements, such as transistors, etc, that function as a load.
The pre-stage differential switching circuit 330 can include NMOS transistors NT51 and NT52. The NMOS transistor NT51 receives a first differential input signal VIn+, and the NMOS transistor NT52 receives a second differential input signal VIn−. The differential switching circuit 330 can be implemented with more than two NMOS transistors that receive the first differential input signal VIn+, and more than two NMOS transistors that receive the second differential input signal VIn−.
The NMOS transistors NT51 and NT52 employ a thin gate oxide that can endure a voltage level of the low power supply voltage VDDL.
The pre-stage current source 340 can include NMOS transistors NT53 and NT54, wherein the source of each of NMOS transistors NT53 and NT54 is coupled together at a common source node N1. The transistors NT53 and NT54 can employ a thin gate oxide. The transistors NT53 and NT54 have gates that are coupled to a bias voltage Vc, and operate in a saturation region. A magnitude of the constant current provided by the transistors NT53 and NT54 can be determined by the bias voltage Vc. The pre-stage current source 340 can be implemented with any other circuit element that functions as a current source. For example, the pre-stage current source 340 can be replaced by a load circuit including a resistor.
The pre-driver 300 receives first and second differential input signals Vin1+ and Vin1− that swing between a first voltage level and a second voltage level via gates of the transistors NT51 and NT52, performs a differential switching on the first and second differential input signals Vin1+ and Vin1−, and provides first and second differential output signals VOut1+ and VOut1− that swing between a third voltage level and a fourth voltage level to drains of the transistors NT51 and NT52. That is, the pre-driver of
The first blocking capacitor CB1 and the second blocking capacitor CB2 eliminate the DC components of the first and second differential output signals VOut1+ and VOut1−, respectively. Voltage levels of the DC-eliminated first and second differential output signals VOut1+ and VOu1− are not enough for driving transistors of the main driver 400, since the transistors employ a thick gate oxide. Accordingly, the voltage reference circuit 500 between the pre-driver 300 and the main driver 400 shifts the voltage levels of the DC-eliminated first and second differential output signals VOut1+ and VOut1− to levels sufficient for driving transistors that employ the thick gate oxide of the main driver 400.
Referring to
The first and second load circuits 410 and 420 can be implemented with a resistor. For example, the first load circuit 410 includes a resistor R61, and the second load circuit 420 includes a resistor R62.
The differential switching circuit 430 includes NMOS transistors NT61 and NT62 that employ a thick gate oxide.
The equalizer 440 includes a bandwidth control unit 450 and an equalizer control unit 460. The bandwidth control unit 450 includes a variable capacitor Ceq and a variable resistor Req, and receives a bandwidth control signal. The equalizer control unit 450 receives an equalizer control signal.
The current source 470 includes NMOS transistors NT64 and NT65 that employ a thin gate oxide.
Operation of the main driver 400 of
The main driver 400 receives first and second DC-eliminated and level-shifted output signals VIn2+ and VIn2− via gates of the transistors NT61 and NT62, performs a differential switching on the first and second output signals VIn2+ and VIn2− that are DC-eliminated and level-shifted, and provides third and fourth output signals VOut2+ and VOut2− that have a high voltage level.
The equalizer 440 of the main driver 400 is capable of solving signal distortions due to an additional circuit load caused by the DC elimination and the level shifting, and due to a parasitic capacitance caused by the transistors employing the thick gate oxide of main driver 400. That is, a bandwidth of the third and fourth output signals VOut2+ and VOut2− can be controlled according to an application and a circuit characteristic by controlling the variable capacitor Ceq and the variable resistor Req based on the bandwidth control signal.
Referring to
As mentioned above, the differential circuit and the output buffer circuit including the differential circuit according to this disclosure can be employed in a multi-power system operating at a high power supply voltage and a low power supply voltage. The pre-driver includes a differential circuit that employs low-voltage NMOS transistors, and the main driver includes a differential circuit that employs high-voltage NMOS transistors. Accordingly, the output buffer circuit is capable of providing simultaneously both operational speed and the high-voltage output signal.
While the example embodiments in accordance with aspects of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the invention. It is intended by the following claims to claim that which is literally described and all equivalents thereto, including all modifications and variations that fall within the scope of each claim.
Number | Date | Country | Kind |
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10-2006-0068839 | Jul 2006 | KR | national |