The present invention relates to differential circuits. Such circuits are used in a wide range of electronic devices including, for example, active matrix display devices.
The conventional circuit symbol and graphical definition of a differential voltage comparator are given in FIGS. 1(a) and 1(b) respectively. The output voltage VOUT is related to the two input voltages at nodes P and N (i.e. VP and VN) by:
where VDD and VSS are the voltages of the supply rails, VOS is the input offset-voltage caused by non-ideal transistor characteristics, and VSensitivity is the minimum difference between input voltages before a full output swing (VDD−VSS) can occur.
A conventional differential voltage comparator consists of two stages of amplifiers, as is well known in the art. It consists of a differential amplifier circuit as shown in FIGS. 2 and 3 to perform an amplification of the voltage difference between its two inputs VP and VN. For optimum operation, a pair of input transistors T3 and T4 identical in characteristics are required to connect to a pair of identical current-mirror transistors T1 and T2. In FIG. 2 the inputs are NMOS and in FIG. 3 the inputs are PMOS.
In theory, transistors with the same channel width and length (W and L) dimensions should behave identically. This is normally the case for single crystal technology. However, when the device feature size approaches the sub-micron level, spatial variation of transistor characteristics, although small in absolute terms, becomes a problem. This is because the variation becomes large in relation to the operating voltages. However, when the variation can be described by a linear function of position, this problem can be solved by choosing an appropriate topology for the transistors such that the effect of variation is averaged out. In the case of Thin Film Transistor (TFT) technology, the spatial variation of transistor characteristics is large (in absolute and relative terms) and is randomly distributed. The topological approach cannot be used. An object of the present invention is to solve this problem.
The effect of a random spatial variation of transistor characteristics on a conventional comparator circuit comprising a differential-pair is an unpredictable VOS. One proposed solution is to implement additional switches and a capacitor network for detecting and canceling any input offset-voltage VOS caused by the non-ideal transistor characteristics of the comparator circuit. This is effective, but it increases the component count.
Another solution is not to use a differential-pair. A charge-balance differential-voltage comparator requires only the matching of capacitances. Capacitances are easier to match than transistors.
A solution to solve the current-mirror pair problem is to use a single-transistor current-mirror as shown in FIG. 4a. This circuit requires two non-overlapping clock pulses Φ1 and Φ2 to operate. The input current IIN sets the gate bias voltage VGS1 for transistor T1 when the switches S1 and S2 are turned on. This bias condition is stored across C1 and mirrors the IIN as output current IOUT on T1 when S3 is turned on. FIG. 4b explains the operation graphically. The current level at point A when Φ1 is high is similar to the current level at point B when Φ2 is high (i.e. IOUT≈IIN), thus achieving the current-mirror function. In the illustrated circuit the load is a passive device.
According to the present invention a single transistor current-mirror is interfaced with a suitable load in combination with a suitable set of switches to accomplish a comparator function. The comparator function is, thus, not influenced by the spatial distribution of transistor characteristics.
Embodiments of the present invention will now be described by way of further example only and with reference to the accompanying drawings, in which:—
FIGS. 1(a) and 1(b) show the conventional circuit symbol and graphical definition of a differential voltage comparator, respectively;
FIG. 2 shows the input stage of a conventional comparator circuit using a differential pair with NMOS inputs;
FIG. 3 shows the input stage of a conventional comparator circuit using a differential pair with PMOS inputs;
FIGS. 4(a) and 4(b) respectively show a single transistor current-mirror and a graphical description of the operation of that circuit;
FIGS. 5(a) and 5(b) respectively a circuit according to an embodiment of the present invention and a graphical representation of the operation of that circuit;
FIG. 6 symbolically illustrates the internal mechanism of a differential comparator according to an embodiment of the present invention;
FIG. 7 shows the driving waveform of the circuit of FIG. 6;
FIG. 8 illustrates a circuit according to an embodiment of the present invention;
FIG. 9 illustrates a circuit according to another embodiment of the present invention;
FIG. 10 illustrates a circuit according to a further embodiment of the present invention;
FIG. 11 illustrates the interface of the circuit of one of the embodiments with a following stage in an electronic device;
FIG. 12 illustrates another example of the interface of the circuit of one of the embodiments with a following stage in an electronic device;
FIG. 13(a) illustrates another embodiment of a circuit according to the present invention and FIG. 13(b) shows the driving waveforms for that circuit;
FIG. 14 illustrates a modified form of the circuit of FIG. 8;
FIG. 15 shows simulation results for the circuit of FIG. 9;
FIG. 16 is a symbolic representation of a differential comparator according to the present invention including an output stage;
FIG. 17 is a variation of FIG. 16;
FIG. 18 is a detailed diagram of a circuit in accordance with the present invention;
FIG. 19 is a circuit diagram illustrating the input stage of an active matrix sensor cell;
FIG. 20 is a circuit diagram illustrating a current sensor having a discriminator circuit and an output stage;
FIG. 21 is a block diagram useful in explaining the driving method of a multiplexed current sensor for use in a finger print sensor; and
FIG. 22 is a timing diagram of a multiplexed current sensor for use in a finger print sensor.
Embodiments of the present invention will now be described in relation to a differential-current comparator circuit. A method of converting this circuit to a differential-voltage comparator will be described subsequently.
A circuit according to an embodiment of the present invention is illustrated in FIG. 5a. A single-transistor current mirror comprises a transistor T1 with a capacitor C1 connected between the source and gate thereof and a switch S3 connected between the gate and the drain thereof. The switch S3 is operated by a control signal. The single-transistor current-mirror circuit is connected to two current sources that sink IREF and ISEN through switches S10 and S11 driven by two non-overlapping clock signals Φ1 and Φ2, respectively. The control signal to the single-transistor current-mirror circuit is connected to Φ1. The output of this circuit is at node C, and the voltage at this node is referred to as VC.
The operation of this circuit is as follows.
Step 1:
- Φ1 goes high while Φ2 remains low. Switches S3 and S10 are now closed. This allows IREF to flow through the diode-connected transistor T1 and causes a voltage (equal to VGS1, the gate-source voltage of transistor T1) to appear across the capacitor C1. The value of C1 and the on-resistances of switch S3 dominate the charge-up time. At the end of this cycle, VC settles at a voltage VC1.
Intermediate Step:
- Both Φ1 and Φ2 are low. All switches are opened. Both current sources are disconnected from the single-transistor current-mirror circuit. The output voltage VC is floating, or is determined by discharging through the output load (not shown) connected to node C.
Step 2:
- Φ2 goes high while Φ1 remains low. Switch S11 is closed. The circuit is now configured as a source-follower amplifier with a current-source load. The output voltage is determined by the current source ISEN. As shown in FIG. 5b, at steady-state, if ISEN=ISEN2, which is greater than IREF, VC will be less than VC1. However, if ISEN=ISEN1, which is less than IREF, VC will be greater than VC1.
FIG. 6 shows a symbol for this differential-current comparator circuit with voltage output. The required driving waveform is given in FIG. 7.
FIG. 8 illustrates a specific example embodiment for the basic schematic as shown in FIG. 5a. The switches S3, S10 and S11 in FIG. 5a are replaced with n-channel transistors T3, T10 and T11, respectively. P-channel transistors, in principle, can also be used, but n-channel transistors are preferred because they have a lower on-resistance and hence smaller transistor sizes will be needed. As a result, the voltage feed-through effect of Φ1 and Φ2 into nodes C and M is reduced.
The implementation of the current sources depends on the actual applications. One or both of them can be implemented as independent transistors, such as T12 and T13 in Embodiment 2 as shown in FIG. 9, biased to operate in the saturation region. In Embodiment 2, voltages VP and VN controls T12 and T13 to produce IREF and ISEN, respectively. Although the circuit looks like a differential-voltage comparator, care must be taken if it is used as one because the trans-conductance of transistors T12 and T13 may not have the same characteristic (although they are the same size). The circuit as shown in FIG. 10 illustrates how the circuit can be used as a differential-voltage comparator. Transistors T12 and T13 are merged into a single transistor T14, with its gate terminal connected to VP or VN via transistor switches T10 and T11, controlled by Φ1 and Φ2, respectively.
The circuits illustrated in FIGS. 5a and 8 to 10 pre-amplify the difference between the input signals and pass the difference signal to the next stage. In order to further increase the output voltage swing and to make sure a minimum output load is attached to node C, a traditional MOS input amplifier (such as a single-ended source-follower amplifier) can be used. This is shown in FIG. 11. Alternatively, node C may be attached to another single-transistor current-mirror circuit for further amplification, as shown in FIG. 12. Essentially, the node C is connected to the gate of a transistor T35 which is connected between VSS and the output of the second single transistor current mirror. In addition, with reference to FIG. 10 and as shown in FIG. 13a, the basic circuit can be expanded by introducing additional transistor switches. In FIG. 13a, transistor T12 is connected between VBIAS and the gate of transistor T14. Additional non-overlapping clock pulses such as that shown in FIG. 13b will also be required. In FIG. 13a; Φ1 is applied to the gate of T12, Φ2 is applied to the gate of T10 and Φ3 is applied to the gate of T11.
The circuits described above in relation to FIGS. 5 to 13 can be modified to improve performance. When Φ1 goes down, the nodal voltage at nodes C and M are pulled down by the voltage feed-through effect at T3 and T10. Node C suffers the voltage feed-through effect from both T3 and T10 and hence a greater disturbance results. This disturbance could lead to an unexpected output spike at the second comparator stage. To avoid this problem, additional transistors T6 and T7 may be introduced to isolate node C from transistor T1. The circuit of FIG. 8 modified in this way is illustrated in FIG. 14. Additional transistors T6 and T7 are connected in parallel with each other and have their gates each effectively connected with a respective one of the two current source switches (T10 and T11), so as to receive the respective drive signal (Φ1 and Φ2) applied to the current source switches.
Simulation results for the circuit as shown in FIG. 9 with this modification added are shown in FIG. 15, with the circuit using polysilicon TFTs. VC falls during the falling edge of Φ1, but rises by the same amount during the rising edge of Φ2, therefore the initial operating point of VC during Φ2 is unaffected.
FIGS. 16 and 17 illustrate schematically how the input stage can be interfaced to a subsequent stage. FIG. 18 is a detailed circuit diagram of the input and self-bias comparator, in accordance with a preferred example of the present invention. The first stage of the circuit is exactly the circuit of FIG. 14. The output node C is connected to the input of a self bias comparator, the body of which comprises transistors T2, T4, T5, T12, T13, T14 and T17 together with capacitors C2 and C3. The output stage of the self bias comparator comprises transistors T8 and T9. Node C is connected to the source of both of transistors T4 and T12. The drains thereof are respectively coupled through capacitors C2 and C3 to the respective gates of T2 and T17. The drains of T4 and T12 are also respectively connected to the source of T5 and T13. The drain of both T5 and T13 are both connected to VSS. Control signal Φ1 is applied to the gates of T4 and T13. Control signal Φ2 is applied to the gates of T5 and T12. The gates of T2 and T17 are connected to each other and to the source of a transistor T14, whose drain is connected to the source of T17 and whose gate receives signal Φ1. The source of T2 is connected to VDD and it's drain is connected to the source of T17. The drain of T17 is connected to VSS. The interconnection of the drain of T2 and the source of T17 provides the output to the gates of both T8 and T9. The source of T8 is connected to VDD. The drain of T9 is connected to VSS and the interconnection between the drain of T8 and the source of T9 provides the final circuit output.
This invention can be used in detecting the peak and valley in a fingerprint sensor. An example of a fingerprint sensor circuit is shown in FIG. 19. The current source for ISEN is the output signal from a sensor pixel of an active matrix sensor array. Thus, comparing FIG. 19 with FIG. 14 it will be seen that the reference current source is provided by transistor T20, whose gate receives a voltage V1, and that the sensing current source is provided by transistor T21, whose gate receives a voltage V2. Respectively between T20 and T10 and between T21 and T11 are active matrix selection switches T15 and T18, and, T16 and T19. When the sensing cell is selected the voltage VDD is applied to the gates of all of transistors T15, T18, T16 and T19.
FIG. 20 shows an embodiment of a current sensor circuit having a self-bias charge-balance comparator as the output stage. The input stage is the circuit of FIG. 19 and the same self bias comparator as shown in FIG. 18 forms the output stage. The driving scheme is shown in FIG. 21. A non-overlap waveform generator outputs Φ1 and Φ2 which are applied as inputs to a first and second current sensor as well as to a multiplexor and latch circuit. The two current sensors receive an input current Iin and have their respective outputs connected to the multiplexor and latch circuit. The output of the multiplexor and latch circuit is fed through an output buffer stage so as to provide the final circuit output. The timing diagram for the circuit explained in FIGS. 20 and 21 is shown in FIG. 22.
The aforegoing description has been given by way of example only and it will be appreciated by a person skilled in the art that modifications can be made without departing from the scope of the present invention. For example, in FIG. 20 if the P type transistors are replaced by N type transistors and visa versa then VDD becomes Vss and Vss becomes VDD.
Patent Application
20060119399
