Differential comparator cirucit

Abstract

A differential comparator circuit for an Analog-to-Digital Converter (ADC) or other application includes a plurality of differential comparators and a plurality of offset voltage generators. Each comparator includes first and second differentially connected transistor pairs having equal and opposite voltage offsets. First and second offset control transistors are connected in series with the transistor pairs respectively. The offset voltage generators generate offset voltages corresponding to reference voltages which are compared with a differential input voltage by the comparators. Each offset voltage is applied to the offset control transistors of at least one comparator to set the overall voltage offset of the comparator to a value corresponding to the respective reference voltage. The number of offset voltage generators required in an ADC application can be reduced by a factor of approximately two by applying the offset voltage from each offset voltage generator to two comparators with opposite logical sense such that positive and negative offset voltages are produced by each offset voltage generator.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to the art of electronic circuitry, and more specifically to a thresholdless differential comparator circuit for an Analog-to-Digital Converter (ADC) or other application.

2. Description of the Related Art

A conventional Analog-to-Digital Converter (ADC) generally comprises a bank of single-ended voltage comparators as illustrated in FIG. 1. The reference numeral 10 designates a 4-bit (16 discrete value) comparator circuit comprising a voltage divider 12 including a plurality of resistors 12.sub.0 to 12.sub.16 that are connected in series between a positive voltage supply V.sub.DD and ground. The voltages at the upper ends of the resistors 12.sub.0 to 12.sub.16 increase progressively from the bottom to the top of the voltage divider 12.

The circuit further comprises a plurality of single-ended voltage comparators 14.sub.0 to 14.sub.15 having inverting inputs connected to the upper ends of the resistors 12.sub.0 to 12.sub.15 respectively. An analog input voltage V.sub.in is applied to the non-inverting inputs of the comparators 14.sub.0 to 14.sub.15, which produce output voltages V.sub.o1 to V.sub.o15 at their single-ended outputs.

An N-bit ADC requires 2.sup.N resistors and 2.sup.N -1 comparators. Thus, the circuit 10 comprises, for a 4-bit converter, 16 resistors and 15 comparators. In operation, each comparator 14.sub.0 to 14.sub.15 produces a logically high output if the input voltage V.sub.in is higher than the voltage at its inverting input, and vice-versa.

The values of the resistors 12.sub.0 to 12.sub.16 are selected such that the voltages at the upper ends thereof constitute a series of equally stepped reference voltages corresponding to the increments into which the analog input signal V.sub.in is to be digitized. Thus, all of the comparators 14.sub.0 to 14.sub.15 whose reference voltages are higher than the input voltage V.sub.in will produce low outputs, whereas all of the comparators whose reference voltages are lower than the input voltage V.sub.in will produce high outputs.

Although not explicitly illustrated, the circuit 10 further comprises a multiplexer or encoder that is responsive to the transition point from low to high output voltage from the comparators 14.sub.0 to 14.sub.15, and encodes the transition point to produce a digital value.

A major drawback of the conventional comparator 10 is that each of the comparators 14.sub.0 to 14.sub.15 operates at a different common mode voltage, which in the case of the circuit 10 of FIG. 1 is defined to be a voltage that is halfway between the voltages at the inverting and non-inverting inputs of the comparators 14.sub.0 to 14.sub.15.

Assuming, for example, that the input voltage V.sub.in can have a 2 V range from 1 V to 3 V, the reference voltage applied to inverting input of the lowest comparator 14.sub.0 will be approximately 1 V whereas the reference voltage applied to the highest comparator 14.sub.15 will be 3 V. If the input voltage V.sub.in has an average value of 2 V, the common mode voltage of the comparator 14.sub.0 is 2 V-1 V=1 V, whereas the common mode voltage of the comparator 14.sub.15 is 3 V-1 V=2 V.

In general, depending on the value of the input signal V.sub.in, the common mode voltage of the comparators 14.sub.0 to 14.sub.15 can range from 0 V to 3 V, the entire range of the input signal V.sub.in. Thus, the comparators 14.sub.0 to 14.sub.15 must be designed with sufficient dynamic range to accommodate this magnitude of input signal variation.

Each of the reference voltages can be considered as a "threshold" voltage for the particular comparator to which it is connected and is different for each comparator in the bank. Since a practical comparator is implemented as a differential amplifier (emitter-coupled in a bipolar transistor circuit or source-coupled in a field-effect transistor circuit), the input common-mode voltage can have a strong effect on the input-output transfer and delay characteristics.

These common-mode induced differences can cause an effective decrease in the overall resolution of the comparator bank. In addition, high frequency white noise due to crosstalk can become superimposed onto the input line resulting in further limits on the achievable resolution.

SUMMARY OF THE INVENTION

A differential comparator circuit for an Analog-to-Digital Converter (ADC) or other application in accordance with the present invention includes a plurality of differential comparators and a plurality of offset voltage generators.

Each comparator includes first and second differentially connected transistor pairs having equal and opposite voltage offsets. First and second offset control transistors are connected in series with the transistor pairs respectively.

The offset voltage generators generate offset voltages corresponding to reference voltages which are compared with a differential input voltage by the comparators. Each offset voltage is applied to the offset control transistors of at least one comparator to set the overall voltage offset of the comparator to a value corresponding to the respective reference voltage.

The number of offset voltage generators required in an ADC application can be reduced by a factor or approximately two by applying the offset voltage from each offset voltage generator to two comparators with opposite logical sense such that positive and negative offset voltages are produced by each offset voltage generator.

The present comparator circuit eliminates the input terminal that is dedicated to creating a threshold voltage which is present in conventional comparators, and enables all comparators within a comparator bank to be driven differentially and operated at the same common mode voltage. This eliminates variations in transfer and delay characteristics between the individual comparators, and enables the resolution of the comparator circuit to be substantially increased over the prior art.

In addition, the dynamic range required by each comparator is reduced by a factor of two, resulting in increased linearity. Another advantage of the present invention is that high speed crosstalk noise is rejected since the differential inputs of each comparator carry the same noise.

These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electrical schematic diagram illustrating a prior art comparator circuit for an Analog-to-Digital Converter (ADC);

FIG. 2 is an electrical schematic diagram illustrating a thresholdless differential comparator embodying the present invention;

FIG. 3 is an electrical schematic diagram illustrating an offset voltage generator for generating and applying an offset voltage to the comparator of FIG. 2;

FIG. 4 is an electrical schematic diagram illustrating a 4-bit thresholdless differential comparator circuit for an ADC comprising pluralities of the comparators of FIG. 2 and the offset voltage generators of FIG. 3;

FIGS. 5 and 6 are electrical schematic diagrams illustrating the operation of the comparator of FIG. 2;

FIG. 7 is a graph which further illustrates the operation of the comparator in conjunction with FIGS. 5 and 6;

FIG. 8 is a simplified equivalent circuit diagram of the comparator;

FIG. 9 is a simplified equivalent circuit diagram of the offset voltage generator;

FIG. 10 is a graph illustrating a computer simulation of the operation of the prior art comparator circuit of FIG. 1; and

FIG. 11 is a graph illustrating a computer simulation of the operation of the present comparator circuit of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

A comparator circuit according to the present invention comprises at least one thresholdless differential comparator 16 as illustrated in FIG. 2. The comparator 16 comprises a first differentially connected pair of transistors T1 and T2, and a second differentially connected pair of transistors T3 and T4. Although the comparator 16 is illustrated as being implemented using field-effect transistors, the invention is not so limited, and may be implemented using bipolar transistors or any other suitable type of electronic devices although not explicitly illustrated.

The sources of the transistors T1 and T2 are connected to the drain of an offset control transistor T5, whereas the sources of the transistors T3 and T4 are connected to the drain of an offset control transistor T6. The sources of the transistors T5 and T6 are connected through a constant current drain S1 to ground.

The drains of the transistors T1 and T2 are connected through load resistors R1 and R2 respectively to a power supply voltage V.sub.DD. The drains of the transistors T3 and T4 are connected to the voltage V.sub.DD through the resistors R1 and R2 in parallel with the transistors T1 and T2.

A differential input voltage V.sub.in +-V.sub.in - is applied to the gates of the transistors T1,T2, and also to the gates of the transistors T3,T4. A differential output voltage V.sub.out +-V.sub.out - appears across the lower ends of the resistors R2 and R1 respectively. A differential offset voltage V.sub.c +-V.sub.c - is applied to the gates of the transistors T5,T6.

In accordance with the present invention, the first pair of transistors T1 and T2 has a voltage offset that is equal and opposite to that of the pair of transistors T3 and T4. This can be accomplished by, for example, by appropriately scaling the gate widths of the transistors. The voltage offsets are also symmetrical about a zero point, such that when the input voltage V.sub.in +-V.sub.in - and the offset voltage V.sub.c +-V.sub.c - are zero, the output voltage V.sub.out +-V.sub.out - is zero.

For the purpose of describing the principles of the invention, it will be assumed that the gate widths of the transistors T1 and T4 are equal, and are larger than the gate widths of the transistors T2 and T3 which are also equal. FIG. 5 illustrates an extreme case in which V.sub.c - is sufficiently small that the transistor T6 is turned off and no current flows through it and the transistors T3 and T4, but V.sub.c + is sufficiently large that current flows through the transistors T5, T1 and T2. FIG. 6 illustrates the opposite case in which the transistors T6, T3 and T4 are turned on and the transistors T5, T1 and T2 are turned off.

In FIG. 5, the circuit 16 effectively consists of only the transistors T1, T2 and T5 and the associated elements as illustrated. It will be further assumed that the input voltage V.sub.in +-V.sub.in - is zero. Since the gate width of the transistor T1 is larger than that of the transistor T2, more current flows through the transistor T1 than through the transistor T2, and the voltage drop across the resistor R1 is larger than the voltage drop across the resistor R2.

Thus, voltage at V.sub.out - will be lower that the voltage at V.sub.out +, and the differential offset voltage V.sub.out +-V.sub.out - will be positive thereby constituting the maximum voltage offset of the transistor pair T1,T2. A negative input voltage V.sub.in +-V.sub.in - (input voltage offset) would have to be applied to the transistor pair T1, T2 to produce a zero output voltage.

FIG. 6 illustrates the voltage offset of the transistor pair T3,T4. It will again be assumed that the input voltage V.sub.in +-V.sub.in - is zero. Since the gate width of the transistor T4 is larger than that of the transistor T3, more current flows through the transistor T4 than through the transistor T3, and the voltage drop across the resistor R2 is larger than the voltage drop across the resistor R1.

Thus, voltage at V.sub.out + will be lower that the voltage at V.sub.out -, and the differential offset voltage V.sub.out +-V.sub.out - will be negative thereby constituting the maximum voltage offset of the transistor pair T3,T4. A positive input voltage V.sub.in +-V.sub.in - (input voltage offset) would have to be applied to the transistor pair T3,T4 to produce a zero output voltage.

The voltage offset of the comparator 16, designated as V.sub.off, is approximately equal to the algebraic sum of the voltage offsets of the transistor pairs T1,T2 and T3,T4, and is variable from a maximum positive value as described with reference to FIG. 5 to a maximum negative value as described with reference to FIG. 6 by selecting the value of the differential offset voltage V.sub.c +-V.sub.c -.

When V.sub.c +-V.sub.c - has a maximum positive value, the comparator 16 has a maximum positive voltage offset V.sub.off. When V.sub.c +-V.sub.c - has a maximum negative value, the comparator has a maximum negative voltage offset V.sub.off. When V.sub.c +-V.sub.c - is zero, the voltage offsets of the transistor pairs T1,T2 and T3,T4 cancel each other out, and the voltage offset V.sub.off of the comparator 16 is zero. The voltage offset V.sub.off is continuously variable from the maximum positive value to the maximum negative value by selecting the value of the offset voltage V.sub.c +-V.sub.c -.

FIG. 7 illustrates how the output voltage V.sub.out +-V.sub.out - varies as a function of input voltage V.sub.in +-V.sub.in - for different values of offset voltage V.sub.c +-V.sub.c -. V.sub.off is a generally, but not completely, linear function of V.sub.c +-V.sub.c -. The transfer function of output voltage with respect to input voltage is (V.sub.out +-V.sub.out -)=(V.sub.in +-V.sub.in -)=V.sub.off.

When V.sub.c +-V.sub.c - has a maximum positive value, V.sub.off is positive as described above, and a negative value of V.sub.in +-V.sub.in - is required to produce a zero output voltage V.sub.out+ -V.sub.out -. This case is represented in FIG. 7 by curves V.sub.out +(max) and V.sub.out -(max). When V.sub.c +-V.sub.c - has a maximum negative value, V.sub.off is negative, and a positive value of V.sub.in +-V.sub.in - is required to produce a zero output voltage V.sub.out+ -V.sub.out -. This case is represented in FIG. 7 by curves V.sub.out +(min) and V.sub.out -(min). When V.sub.c +-V.sub.c - is zero, the voltage offset V.sub.off is zero as represented by curves V.sub.out +(zero) and V.sub.out -(zero).

The magnitude of V.sub.off is selected to be at least equal to the maximum magnitude of a reference voltage with which the comparator 16 is to compare the input voltage V.sub.in +-V.sub.in -. For example, if the reference voltage can vary by 1 V above and below an average value (a comparison range of 2 V), then V.sub.off is equal to or greater than 1 V as illustrated.

In accordance with an important feature of the present invention, the comparator 16 provides a common mode voltage V.sub.cm that is constant over the entire operating range of input, output and offset voltages, In this case, the common mode voltage V.sub.cm is defined as the voltage at which V.sub.out+ and V.sub.out - are equal. The voltage V.sub.cm is preferably at the middle of the voltage output range of the comparator 16 between V.sub.DD and a minimum value V.sub.min, but may vary somewhat in actual practice.

Since the common mode voltage V.sub.cm is constant, the comparator 16 is immune to variations in input-output transfer and delay characteristics as descried above with reference to the prior art. The comparator 16 is therefore "thresholdless" as compared with the conventional comparator illustrated in FIG. 1.

Another important advantage of the present invention is that, due to the differential configuration, the required input voltage variation at each of the inputs V.sub.in + and V.sub.in - is one-half that required by a conventional comparator. For example, a 2 V input voltage range can be produced by symmetrically varying V.sub.in + from 3 V to 2 V (a 1 V range) and V.sub.in - from 2 V to 3 V. Where V.sub.in +=3 V and V.sub.in -=2 V, V.sub.in+ -V.sub.in -=3 V-2 V=1 V. Where V.sub.in +=2 V and V.sub.in -=3 V, V.sub.in+ -V.sub.in -=2 V=3 V=-1 V.

This eases the "headspace" requirements of the comparator 16 and enables increased linearity. In addition, high speed crosstalk noise is rejected since the differential inputs of each comparator carry the same noise.

Although it is within the scope of the invention to generate offset voltages V.sub.c +-V.sub.c - corresponding to reference voltages for the comparators 16 of an ADC using resistors as illustrated in FIG. 1, this is not the preferred embodiment of the invention since the offset control transistors T5 and T6 are sources of non-linearity and clamping distortion that can reduce the resolution of the ADC.

For this reason, offset voltage generators 18 as illustrated in FIG. 3 are provided to generate offset voltages V.sub.c +-V.sub.c - in response to differential reference voltages V.sub.ref +-V.sub.ref -.

A reference voltage generator 18 as viewed in FIG. 3 comprises a comparator which is essentially similar to the comparator 16, including a first pair of differentially connected transistors T7 and T8, a second pair of differentially connected transistors T9 and T10, a first offset control transistor T11, a second offset control transistor T12, load resistors R3 and R4 and a constant current drain S2 that are identical to the elements in corresponding positions in the comparator 16.

The generator 18 further comprises a transistor T13 that is connected between the voltage supply V.sub.DD and the gate of the transistor T11 through voltage dropping diodes D1, D2 and D3, and a transistor T14 that is connected between the voltage supply V.sub.DD and the gate of the transistor T12 through voltage dropping diodes D4, D5 and D6. The gates of the transistors T13 and T14 are connected to the lower ends of the resistors R3 and R4 respectively.

The reference voltage V.sub.ref +-V.sub.ref - is applied to the gates of the transistors T7 and T10, whereas the offset voltage V.sub.c +-V.sub.c - appears across the cathodes of the diodes D3 and D6. If desired, optional amplifiers A1 and A2 can be inserted as illustrated to increase the linearity of the generator 18 by providing extremely high gain.

The offset voltage V.sub.c +-V.sub.c - is generated at the lower ends of the resistors R3 and R4, and is fed back to the gates of the transistors T11 and T12 to provide a closed feedback loop. The transistors T11 and T12 create gain and non-linearity that is equal and opposite to that created by the transistors T5 and T6 of the comparator 16, such that these undesirable effects are canceled out and the reference voltage V.sub.ref +-V.sub.ref - is applied to the comparator 16 in a substantially linear manner.

The operation of the comparator 16 in combination with the generator 18 will be described with reference being made to the simplified equivalent circuits of FIGS. 8 and 9 respectively.

The transistors T1, T2, T3 and T4 in FIG. 8 are represented by a block 30, which has an amplification factor or gain of A.sub.vs. The block 30 comprises an operational amplifier 32 that produces the differential input signal V.sub.in+ -V.sub.in -, and an operational amplifier 34 that receives V.sub.in+ -V.sub.in - at its non-inverting input.

The transistor T5 and T6 are represented by an amplifier 32 having a gain of A.sub.off, which produces the offset voltage V.sub.off at its output such that V.sub.off =(V.sub.c +-V.sub.c -).times.A.sub.off, which is applied to the inverting input of the amplifier 34. The output voltage V.sub.out+ -V.sub.out - appears at the output of the amplifier 34.

The generator 18 comprises a block 40 including amplifiers 42 and 44 that are essentially similar to the elements 30, 32 and 34, and an amplifier 46 that is similar to the amplifier 46. The amplifier 42 produces the differential input signal V.sub.ref+ -V.sub.ref - which is applied to the non-inverting of the amplifier 44. The offset voltage V.sub.c +-V.sub.c - appears at the output of the amplifier 44, and is fed back to the input of the amplifier which produces the offset signal V.sub.off as being equal to V.sub.off =(V.sub.c +-V.sub.c -).times.A.sub.off.

The transfer function of the generator 18 can be approximate by ##EQU1##

In the limiting case in which A.sub.vs and A.sub.off are very large, which is desirable in the context of the present invention,

V.sub.off .apprxeq.V.sub.ref+ -V.sub.ref -

The feedback loop in the generator 18 produces the offset voltage V.sub.c +-V.sub.c - as being substantially equal to the reference voltage V.sub.ref+ -V.sub.ref -=V.sub.off divided by the gain A.sub.off of the amplifier 46. The amplifier 36 in the comparator 16 multiplies V.sub.c +-V.sub.c - by the gain A.sub.off such that the output of the amplifier 36 is V.sub.off .apprxeq.V.sub.ref+ -V.sub.ref -. Since the amplifiers 36 and 46 are identical, division of the reference voltage by the amplifier 46 cancels multiplication of the reference voltage by the amplifier 46, such that all non-linear and other distortion is also canceled out. In this manner, the comparator 16 and generator 18 in combination can produce reference voltages with high linearity and resolution.

FIG. 4 illustrates a 4-bit comparator circuit 20 for an ADC or other application, comprising a resistor voltage divider 22 including resistors 22.sub.0 to 22.sub.8 connected in series between V.sub.DD and ground. The circuit 20 further comprises offset voltage generators 18.sub.0 to 18.sub.7 as illustrated in FIG. 3, and comparators 16.sub.7 - to 16.sub.7 + as illustrated in FIG. 2 that produce differential output voltages V.sub.o7 - to V.sub.o7 +.

The differential nature of the present invention enables the comparator circuit 20 to be embodied using approximately one-half the number of generators 18 as would be required in a prior art configuration. This is accomplished by using a single offset voltage generator to apply a positive offset to one comparator 16 and a negative offset to another comparator 16.

The circuit 20 comprises 2.sup.N -1=2.sup.4 -1=15 comparators 16, and 2.sup.N -2.sup.N-1 =2.sup.4 -2.sup.3 =8 generators 18. Since the generator 18.sub.0 generates a zero reference voltage, it could be replaced by a direct connection to ground in which case the number of generators 18 would be 2.sup.N -2.sup.N-1 -1=7 generators 18.

The V.sub.ref - inputs of all of the generators 18.sub.0 to 18.sub.7, as well as the V.sub.ref - terminal of the generator 18.sub.0, are all connected to the upper end of the resistor 22.sub.0. The V.sub.ref + inputs of the generators 18.sub.1 to 18.sub.7 are connected to the upper ends of the resistors 22.sub.1 to 22.sub.8 respectively, such that progressively larger voltages are applied to these inputs. The values of the resistors 22.sub.0 to 22.sub.8 are selected such that V.sub.ref + voltages increase in equal increments, and the input voltage range is equally divided into 16 steps.

The offset voltages V.sub.c +-V.sub.c - from the generators 18.sub.1 to 18.sub.7 are applied to the offset voltage inputs of the comparators 16.sub.1 + to 16.sub.7 + without reversal of logical sense such that the offset voltages increase in a positive direction. The offset voltages V.sub.c +-V.sub.c - from the generators 18.sub.1 to 18 .sub.7 are applied to the offset voltage inputs of the comparators 16.sub.1 - to 16.sub.7 -, with opposite (reversed) logical sense such that the offset voltages increase in a negative direction. This is accomplished by merely reversing the connections of the offset voltages V.sub.c +-V.sub.c - to the comparators 16.sub.1 - to 16.sub.7 - relative to the connections to the comparators 16.sub.1 + to 16.sub.7 +. The comparator 16.sub.0 receives a zero offset voltage.

In this manner, the comparators 16.sub.7 - to 16.sup.7 + receive offset voltages V.sub.c +-V.sub.c - that cover the entire range of the input signal to be digitized. If the input voltage V.sub.in+ -V.sub.in - is smaller than the reference voltage V.sub.ref+ -V.sub.ref - as represented by the respective offset voltage V.sub.c +-V.sub.c -, a comparator will produce a negative output voltage V.sub.out+ -V.sub.out -, and vice-versa.

EXAMPLE

FIGS. 10 and 11 illustrate a comparison of the prior art comparator circuit 10 of FIG. 1 with the present comparator circuit 20 of FIG. 4. The figures were generated by computer simulation using the SPICE analysis program.

In both cases, the power supply voltage V.sub.DD =5 V, the analog input signal had a voltage range of 2 V, the resolution was 4 bits (16 increments).

FIG. 10 illustrates the prior art arrangement, in which the input signal range was 1 V to 3 V. The resistors 12.sub.0 to 12.sub.16 had the following values:

12.sub.0 =10k.OMEGA. 12.sub.1 =1,250.OMEGA. 12.sub.2 =1,250.OMEGA. 12.sub.3 =1,250.OMEGA. 12.sub.4 =1,250.OMEGA. 12.sub.5 =1,250.OMEGA. 12.sub.6 =1,250.OMEGA. 12.sub.7 =1,250.OMEGA. 12.sub.8 =1,250.OMEGA. 12.sub.9 =1,250.OMEGA. 12.sub.10 =1,250.OMEGA. 12.sub.11 =1,250.OMEGA. 12.sub.12 =1,250.OMEGA. 12.sub.13 =1,250.OMEGA. 12.sub.14 =1,250.OMEGA. 12.sub.15 =1,250.OMEGA. 12.sub.16 =20k.OMEGA. such that the voltages at the upper ends of the resistors 12.sub.0 to 12.sub.14 had respective values of: V0=1.0256 V V1=1.1538 V V2=1.2821 V V3=1.4103 V V4=1.5385 V V5=1.6667 V V6=1.7949 V V7=1.9231 V V8=2.0513 V V9=2.1795 V V10=2.3077 V V11=2.4359 V V12=2.5641 V V13=2.6923 V V14=2.8205 V

The input voltage range was V.sub.in <1.0256 for the lowest increment (all comparator outputs low) to V.sub.in >2,8205 V (all comparator outputs high).

The comparators 14.sub.0 to 14.sub.15 of FIG. 1 are generally implemented as differential amplifiers as described above, but with no voltage offsets. FIG. 10 illustrates the transfer characteristic for each of the comparators 14.sub.0 to 14.sub.15, including the illustrated outputs V.sub.o0 to V.sub.o15 and the corresponding complementary differential outputs V.sub.o0 - to V.sub.o15 -.

The graph of FIG. 10 exhibits severe distortion which is caused by two separate effects.

1. Variation in the peak-to-peak voltage and common mode voltage of the individual comparators. The common mode voltage is designated by a line 50 which has a large downward slope.

2. Clamping of the comparator outputs when the input voltages have values that cause the output voltages to saturate or turn off the individual transistors in the comparators.

The operation of the present comparator 20 is illustrated in FIG. 11. In this exemplary case, the resistors 22.sub.0 to 22.sub.8 had the values:

22.sub.0 32 20k.OMEGA. 22.sub.1 =1328.6.OMEGA. 22.sub.2 =1428.6.OMEGA. 22.sub.3 =1428.6.OMEGA. 22.sub.4 =1428.6.OMEGA. 22.sub.5 =1428.6.OMEGA. 22.sub.6 =1428.6.OMEGA. 22.sub.7 =1428.6.OMEGA. 22.sub.8 =20k.OMEGA. such that the voltages at the upper ends of the resistors 22.sub.1 to 22.sub.8 had the respective values: V0=2.000 V V1=2.143 V V2=2.286 V V3=2.429 V V4=2.571 V V5=2.714 V V6=2.857 V V7=3.000 V

The output voltages of the comparators 16.sub.7 - to 16.sub.7 + are designated as V.sub.o0 to V.sub.o15 and V.sub.o0 - to V.sub.o15 - to enable direct comparison with the prior art example of FIG. 10. The common mode input voltage was selected to be 2.5 V, halfway between the power supply voltages (5 V and ground). The common mode input voltage was approximately 4.2 V as indicated by a line 60 which is substantially horizontal, indicating that the common mode voltage remains constant over the entire operating range of the comparator circuit 20.

In summary, it will be sen that the present voltage comparator circuit eliminates the input terminal that is dedicated to creating a threshold voltage which is present in conventional comparators, and enable all comparators within a comparator bank to be driven differentially and operated at the same common mode voltage. This eliminates variations in transfer and delay characteristics between the individual comparators, and enables the resolution of the comparator circuit to be substantially increased over the prior art.

In addition, the dynamic range required by each comparator is reduced by a factor of two, resulting in increased linearity. Another advantage of the present invention is that high speed crosstalk noise is rejected since the differential inputs of each comparator carry the same noise.

Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

Claims

1. A voltage comparator circuit comprising:

a reference voltage generator for generating a plurality of progressively larger differential reference voltages; and

a plurality of differential comparators for comparing a differential input voltage with said reference voltages and producing differential output voltages having first logical senses if said input voltage is larger than said reference voltages, and having second logical senses if said input voltage is smaller than said reference voltages respectively, in which:

each comparator has an offset voltage input; and

the circuit further comprises a plurality of differential offset voltage generators for generating and applying offset voltages having values corresponding to said reference voltages to said offset voltage inputs of the comparators in a predetermined arrangement;

the comparators having comparator voltage offsets that vary in accordance with said offset voltages respectively.

2. A circuit as in claim 1, in which each comparator comprises:

a differentially connected first transistor pair having differential first inputs for receiving said input voltage and differential first outputs at which said output voltage appears;

a differentially connected second transistor pair having differential second inputs for receiving said input voltage and differential second outputs that are connected in parallel with said first outputs;

a first offset control transistor which is connected in series with the first transistor pair and has a single-ended first offset input; and

a second offset control transistor which is connected in series with the second transistor pair and has a single-ended second offset input; in which

the first and second transistor pairs have first and second voltage offsets of opposite logical sense respectively; and

said offset voltage is applied across said first and second offset inputs.

3. A circuit as in claim 2, in which said first and second voltage offsets are symmetrical, and said comparator voltage offset is zero when said offset voltage is zero.

4. A circuit as in claim 3, in which the first and second voltage offsets are at least as large as a maximum value of said reference voltage.

5. A circuit as in claim 2, in which each offset voltage generator comprises:

a differentially connected third transistor pair having third differential inputs for receiving said reference voltage and third differential outputs at which said offset voltage appears;

a differentially connected fourth transistor pair having differential fourth inputs for receiving said reference voltage and differential fourth outputs that are connected in parallel with said third outputs;

a third offset control transistor which is connected in series with the third transistor pair and has a single-ended third offset input; and

a fourth offset control transistor which is connected in series with the second transistor pair and has a single-ended fourth offset input;

the third and fourth transistor pairs having third and fourth voltage offsets of opposite logical sense respectively; and

said offset voltage is fed back from said third outputs across said third and fourth offset inputs respectively.

6. A circuit as in claim 5, in which said third and fourth voltage offsets are substantially equal to said first and second voltage offsets respectively.

7. A circuit as in claim 6, in which:

the third and fourth transistor pairs are substantially identical to the first and second transistor pairs respectively; and

the third and fourth offset control transistors are substantially identical to the first and second offset control transistors respectively.

8. A circuit as in claim 1, in which:

each offset voltage generator applies its offset voltage to said offset voltage input of one of the comparators with a first logical sense and to said offset voltage input of another of the comparators with a second logical sense.

9. A circuit as in claim 8, in which the circuit is an N-bit comparator circuit, comprising:

2.sup.N -1 comparators; and

2.sup.N -2.sup.N-1 -1 differential offset voltage generators.

10. A circuit as in claim 9, further comprising means for applying a zero offset voltage to one of the comparators.

11. A circuit as in claim 10, in which said means comprises a differential offset voltage generator.

12. A circuit as in claim 1, in which:

the circuit comprises power supply inputs for receiving a power supply voltage thereacross; and

said input voltage has a common mode voltage that is substantially equal to one-half said power supply voltage.

13. A differential voltage comparator circuit for comparing a differential input voltage with a differential reference voltage and producing a differential output voltage a having first logical sense if said input voltage is larger than said reference voltage, and having second logical sense if said input voltage is smaller than said reference voltage, comprising:

a differentially connected first transistor pair having differential first inputs for receiving said input voltage and differential first outputs at which said output voltage appears;

a differentially connected second transistor pair having differential second inputs for receiving said input voltage and differential second outputs that are connected in parallel with said first outputs;

a first offset control transistor which is connected in series with the first transistor pair and has a single-ended first offset input; and

a second offset control transistor which is connected in series with the second transistor pair and has a single-ended second offset input; in which

the first and second transistor pairs have first and second voltage offsets of opposite logical sense; and

the first and second offset inputs are adapted to have an offset voltage corresponding to said reference voltage applied thereacross.

14. A circuit as in claim 13, in which:

said first and second voltage offsets are symmetrical; and

the comparator has a zero voltage offset when said offset voltage is zero.

15. A circuit as in claim 14, in which the first and second voltage offsets are at least as large as a maximum value of said reference voltage.

16. A circuit as in claim 13, further comprising an offset voltage generator that includes:

a differentially connected third transistor pair having third differential inputs for receiving said reference voltage and third differential outputs at which said offset voltage appears;

a differentially connected fourth transistor pair having differential fourth inputs for receiving said reference voltage and differential fourth outputs that are connected in parallel with said third outputs;

a third offset control transistor which is connected in series with the third transistor pair and has a single-ended third offset input; and

a fourth offset control transistor which is connected in series with the second transistor pair and has a single-ended fourth offset input;

the third and fourth transistor pairs having third and fourth voltage offsets of opposite logical sense respectively; and

said offset voltage is fed back from said third outputs across said third and fourth offset inputs respectively.

17. A circuit as in claim 16, in which said third and fourth voltage offsets are substantially equal to said first and second voltage offsets respectively.

18. A circuit as in claim 17, in which:

the third and fourth transistor pairs are substantially identical to the first and second transistor pairs respectively; and

the third and fourth offset control transistors are substantially identical to the first and second offset control transistors respectively.

19. A circuit as in claim 15, in which:

the circuit comprises power supply inputs for receiving a power supply voltage therebetween; and

said input voltage has a common mode voltage that is substantially equal to one-half said power supply voltage.