This application claims the benefit of and priority to U.S. patent application Ser. No. 17/077,439, filed on Oct. 22, 2020, which is hereby incorporated by reference.
This relates to a differential converter that has an offset cancellation circuit.
In electronics, a sample and hold circuit is an analog device that samples the voltage of a continuously varying analog signal and holds its value at a constant level for a specified minimum period of time. Sample and hold circuits and related peak detectors are the elementary analog memory devices. They are typically used in analog-to-digital converters (ADC) to eliminate variations in input signal that can corrupt the conversion process.
In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.
In the drawings, like elements are denoted by like reference numerals for consistency.
A typical sample and hold circuit stores electric charge in a capacitor and contains at least one switching device, such as a FET (field effect transistor), and an operational amplifier (op-amp). To sample an input signal, the FET switch connects the capacitor, referred to herein as the “sample capacitor,” to a signal to be measured, such as the output of a buffer amplifier. The buffer amplifier charges or discharges the capacitor so that the voltage across the hold capacitor is practically equal, or proportional to, the input signal voltage. In hold mode, the switch disconnects the sample capacitor from the buffer. The sample capacitor tends to be discharged by its own leakage currents and load currents from the op-amp input, which makes the circuit inherently volatile. Typically, the voltage drop within a specified hold typically time remains within an acceptable error margin.
When the sample and hold circuit switches from sample to hold, there is generally a small amount of charge dumped on the hold capacitor because of non-ideal switches. This results in a hold mode dc offset voltage which is called pedestal error. If the sample and hold circuit is driving an ADC, the pedestal error appears as a dc (direct current) offset voltage which may be removed by performing a system calibration. If the pedestal error is a function of input signal level, the resulting nonlinearity contributes to hold mode distortion. Pedestal errors may be reduced by increasing the value of the hold capacitor with a corresponding increase in acquisition time and a reduction in bandwidth and slew rate.
An example sample and hold circuit uses a unity gain op-amp with differential outputs to allow simple offset cancellation. In a typical differential sample and hold circuit, the input bandwidth is usually limited by the bandwidth of the op-amp when put in unity gain. The effective input resistance (Rin) is 1/gm (trans-conductance) of the op-amp.
An improved configuration will be described herein below that eliminates the bandwidth dependency on the op-amp by adding a complementary metal oxide semiconductor (CMOS) switch that is coupled to the sampling capacitor. This CMOS switch is tied to the inverting input of the op-amp connecting it to a fixed reference voltage, such as a common input voltage that is one half the supply voltage (VDD/2). This switch will provide a low impedance path from the reference voltage to the sampling capacitor if the width/length (W/L) is sized large enough and thereby provide high bandwidth operation of the sample and hold circuit irrespective of the op-amp gm.
Similarly, CMOS switch 112 periodically connects a Vref_Middle reference voltage on input terminal 111 to sample capacitor 113, which is connected to positive input terminal 122 of op-amp 120. Vref_Middle is approximately VDD/2, as described in more detail herein below. Feedback switch 114 periodically connects negative output 124 of op-amp 120 to input 122. Hold capacitor 115 is connected in series with feedback switch 117 that is also connected to op-amp negative output 124. Switch 116 is connected to hold capacitor 115 and periodically connects to steady reference voltage CML, which in many op-amp designs is equal to VDD/2.
The switches open/close at the sampling frequency under the control of clock signals PH1 and PH2. Clock signals PH1, PH2 are square wave signals that are out of phase with each other. PH1 is the sampling phase and PH2 is the hold phase. In the sample mode, the input voltage present on input terminal 101 and the reference voltage present on input terminal 111 are applied to the sample capacitors 103, 113 respectively. Simultaneously, hold capacitors 105, 115 are preset by switches 106, 116 respectively connecting to the CML reference voltage. When the circuit enters the hold mode, the voltage across the sampling capacitors is transferred to the hold capacitors 105, 115 by opening switches 104, 106, 114, and 116 and closing switches 107, 117 and 131. Unity gain op-amp 120 maintains the voltage across hold capacitors 105, 115, respectively. When the sample and hold circuit returns to the sample mode, the input source must charge or discharge the voltage stored on sample capacitor 103 to a new input voltage.
The maximum sampling bandwidth is limited by the settling time of op-amp 120 due to the feedback path from op-amp output 123 through switch 104 to op-amp input 121 and sample capacitor 103.
Offset is also cancelled by this configuration. Offset is large in deep submicron processes such as used in typical CMOS integrated circuits. In this example the offset is stored by connecting VOUTN from op-amp negative output 224 to INP on op-amp positive input 222 while VOUTP from op-amp positive output 223 is left unconnected during the sample phase. Because INM on op-amp input 221 is tied to CML (VDD/2) during the sampling phase, the offset is stored on the sampling capacitor 213 sampling a reference voltage on SH input terminal 211.
In this example, an analog signal is received by buffer amplifier 210. The output of buffer amplifier 210 is provided to SH input terminal 201. A steady reference voltage Vref_middle is provided to SH input terminal 211. CMOS switch 202 periodically connects the input signal on SH input terminal 201 to sample capacitor 203. The other terminal of sample capacitor 203 is connected to negative input terminal 221 of op-amp 220. Switch 204 periodically connects the CML reference voltage to negative input 221. Hold capacitor 205 is connected in series with feedback switch 207 that is also connected to op-amp positive output 223. Switch 206 is connected to hold capacitor 205 and periodically couples steady reference voltage CML, which is equal to VDD/2, to hold capacitor 205.
Similarly, CMOS switch 212 periodically connects the reference voltage on input terminal 211 to sample capacitor 213, which is connected to positive input terminal 222 of op-amp 220. Feedback switch 214 periodically connects negative output 224 of op-amp 220 to positive input 222. Hold capacitor 215 is connected in series with feedback switch 217 that is also connected to op-amp negative output 224. Switch 216 is connected to hold capacitor 215 and periodically couples hold capacitor 215 to steady reference voltage CML, which is equal to VDD/2.
The switches open/close at a sampling frequency under the control of clock signals PH1 and PH2. Clock signals PH1, PH2 are non-overlapping square wave signals that are out of phase with each other. PH1 is the sampling phase and PH2 is the hold phase. In this example, the switches 202, 212, 204, 214, 206, 216 controlled by clock signal PH1 are closed while signal PH1 is active and open while signal PH1 is not active. Similarly, the switches 231, 207, 217 controlled by PH2 are closed while signal PH2 is active and open while signal PH2 is not active. As will be explained in more detail with reference to
In the sample mode, the input voltage present on input terminal 201 and the reference voltage present on input terminal 211 are applied to the sample capacitors 203, 213 respectively. Simultaneously, hold capacitors 205, 215 are preset by switches 206, 216 respectively that are connecting to the CML reference voltage. When the circuit enters the hold mode, the voltage across the sampling capacitors is transferred to the hold capacitors 205, 215 by opening switches 204, 206, 214, and 216 and closing switches 207, 217 and 231. Unity gain op-amp 220 maintains the voltage across hold capacitors 205, 215, respectively. When the sample and hold circuit returns to the sample mode, the input source must charge or discharge the voltage stored on sample capacitor 203 to a new input voltage. This action of charging and discharging sampling capacitor 203, averaged over a period of time and for a given sampling frequency fs, makes the input impedance appear to have a primarily resistive component.
The resistive component to the input impedance can be computed by calculating the average charge that is drawn by hold capacitor 205 from the input drive source buffer amp 210. It can be shown that if sample capacitor 203 is allowed to fully charge to the input voltage before switches 202, 212 are opened that the average current into the input is the same as if there were a resistor equal to 1/(Cs*fs) connected between the inputs, where Cs is the capacitance of sample capacitor 203. In this example, Cs is 4 picofarads. Since CS is only a few picofarads, this resistive component is typically greater than several kΩ for an fs=10 MSPS (mega samples per second), for example.
In this example, a sampling capacitance (similar to sampling capacitor 213 of
The voltage values of Vref_Top and Vref_Bottom are selected for a particular application and may represent the top (Vref top) and bottom (Vref bottom) of the input range of an analog signal input. In an example, the op-amp VDDA supply is 1.8 V, the Vref_Top is about 1.6 V and Vref bottom is about 0.2 V. Therefore, the analog signal input range is 1.4 V. Vref_Middle is (Vref top+Vref bottom)/2=0.9 V. This is also the same as the CML (VDD/2) voltage level. The Analog_in range is between 0.2 V and 1.6 V.
In this example, the implementation of the various CMOS switches is shown in more detail. Each CMOS switch is implemented with back to back PMOS and NMOS devices that are controlled by a clock signal and an inverted clock signal, respectively, such as PHI1, PHI1Z and PHI2, PHI2Z. In this example, switches 204 and 214 are controlled by pre-phase clock signals PHI1PP, PHI1PPZ, which are shifted slightly in time from PHI1, PHI1Z by a small delta, such as 0.1 ns, to minimize switching overlap.
In this example, VSS switch 341 couples op-amp output 223 to a gate of NMOS transistor 342 when switched on in response to clock signal PHIPP, PHIPPZ. Similarly, VSS switch 343 couples op-amp output 224 to a gate of NMOS transistor 344 when switched on in response to clock signal PHI1PP, PHI1PPZ. VSS is ground; the source and drain of NMOS transistors 342, 344 are connected to VSS and thereby NMOS transistors 342, 344 are configured as capacitors to ground. Some op-amps, depending on architecture, require capacitors at the outputs when placed in unity gain closed loop feedback to be stable.
Nyquist sampling requires the input frequency to be under CK rate (Sample rate) divided by two to reconstruct the signal without aliasing. For example, if the sampling rate is 500 MHz, then the input frequency must be less than 250 MHz to meet the Nyquist criteria. However, there are cases where the input signal frequency may higher than the clock or sample rate divided by two; these cases are referred to as “under sampling.” When the input is a sine wave, the input frequency can be much higher than the sampling rate and there will be no aliasing since the FFT of a sine is a pulse function. The example SH circuits 200, 300 work well with sine wave inputs to allow under sampling of input signals that have a much higher frequency than the sampling rate. Offset of the op-amp is cancelled without any special timing restrictions.
In some example implementations of the sample and hold circuits of
At 502, an analog input signal is sampled by coupling it to one side of a sampling capacitor during a first phase of a clock period. An opposite side of the sampling capacitor is connected to a first input of the op-amp. A hold capacitor in the feedback path with one side coupled to the first input of the op-amp is reset by coupling an opposite side of the hold capacitor to a fixed reference voltage during a first phase of a clock period.
During the same phase, a reference signal is sampled by coupling it to one side of another sampling capacitor during a first phase of a clock period. An opposite side of this sampling capacitor is connected to a second input of the op-amp. A hold capacitor in the feedback path with one side coupled to the second input of the op-amp is reset by coupling an opposite side of the hold capacitor to a fixed reference voltage during the first phase of the clock period.
At 504, the first input of the op-amp is also coupled to the fixed reference voltage and a second input of the op-amp is coupled to an inverted output of the op-amp during the first phase of the clock period.
At 506, offset is cancelled by isolating the sampling capacitors and the hold capacitors from the analog inputs and the fixed reference voltage during a second phase of the clock period. During the second phase of the clock period, the hold capacitors are coupled to respective outputs of the op-amp and the sampling capacitors are coupled together.
Since RF ADC 708 is capable of sampling RF frequencies, thanks to high bandwidth SH circuit 709, radio frequency receiver system 700 may use the RF ADC 708 to digitize the signal without an intervening intermediate frequency mixer 605, IF amplifier 606, and BPF 607 used in system 600 in
In described examples, the analog signal sampling capacitor is shown coupled to an inverting input of the op-amp with a feedback loop coupled to a non-inverting output of the op-amp. The reference signal sampling capacitor is shown coupled to a non-inverting input amp with a feedback loop coupled to an inverting output of the op-amp. In another example, the op-amp may be “flipped” such that the analog signal sampling capacitor is coupled to a non-inverting input of the op-amp with a feedback loop coupled to an inverting output of the op-amp while the reference signal sampling capacitor is coupled to an inverting input amp with a feedback loop coupled to a non-inverting output of the op-amp.
Described examples refer to the op-amp inputs and outputs as “inverting” and “non-inverting.” In other examples, similar terms may be used to mean the same thing, such as “positive” and “negative,”
In a described example, input buffer 210 (
In described examples, CMOS switches are illustrated. In another example, another type of known or later developed semiconductor switches that can be controlled by clock signals may be used to couple and decouple the sample and hold capacitors as described hereinabove.
The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
Number | Date | Country | |
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Parent | 17077439 | Oct 2020 | US |
Child | 17483082 | US |