The present disclosure relates to current protection, and more particularly to differential current monitoring for current protection.
When distributing power from a bus it is desirable to know when the power into the bus does not equal the sum of the power out of the bus through all the loads. This condition would indicate that there is current loss from the bus to an unwanted location such as ground, i.e., ground fault condition. To implement this check, the sum of all the loads has to be arithmetically subtracted from the source current. This has conventionally required measuring all the currents and then doing the arithmetic to calculate the sums and difference, which is hardware intensive.
Conventional differential current protection can be done by analog current summing or by complex digital arithmetic and high speed communications links. The digital method is often preferred due to the accuracy it provides, however it requires complex field programmable gate arrays (FPGAs) to generate the digital data and perform the sum and difference calculations fast enough to protect against a damaging fault condition.
The conventional techniques have been considered satisfactory for their intended purpose. However, there is an ever present need for improved differential current monitoring. This disclosure provides a solution for this problem.
A system for differential current monitoring includes a control module and a plurality of nodes operatively connected to the control module. Each node is configured to monitor current from a bus to a respective load. The control module and nodes are configured to monitor current at each of the nodes, issue a pulse for each node, wherein the pulse has a duration that is proportional to current at (or through) the node, concatenate all of the pulses for the nodes to determine the total current drawn from the bus at the nodes, compare the total current drawn from the bus at the nodes to current input to the bus, and signal a fault condition if the total current drawn from the bus is not within a predetermined range of the current input to the bus.
The nodes can be arranged in a daisy chain and wherein issuing a pulse for each node includes sequentially issuing a pulse from one node to another along the daisy chain to create a pulse train, wherein each node in the daisy chain adds its pulse duration cumulatively to the total time to the end of the pulse train. The control module can be directly connected to a first one of the nodes and wherein issuing a pulse for each node includes issuing an initial pulse from a control module to the first one of the nodes to initiate transmission of the pulse train along the daisy chain. The control module can be directly connected to a final one of the nodes, wherein issuing a pulse for each node includes transmitting the pulse train back from a final one of the nodes in the daisy chain to the control module. The control module can be directly connected to each of the nodes, wherein the control module and nodes are configured to simultaneously issue a start pulse from a control module to each of the nodes so that all nodes sample their respective currents at the same time.
A method of differential current monitoring includes monitoring current at each of a plurality of nodes where loads are powered from a bus, issuing a pulse for each node, wherein the pulse has a duration that is proportional to current at the node, concatenating all of the pulses for the nodes to determine the total current drawn from the bus at the nodes, comparing the total current drawn from the bus at the nodes to current input to the bus, and signaling a fault condition if the total current drawn from the bus is not within a predetermined range of the current input to the bus.
Summing all of the pulses can include measuring duration of round trip time from the first pulse out of the control module until the end of the very last pulse back to the control module, wherein the duration of round trip time is proportional to the sum of all the current through the nodes. The method can include monitoring for a timeout condition in the control module in response to failure to receive the pulse train from the last one of the nodes in the daisy chain, and reporting a fault in response to the timeout condition. Each of the nodes can use a common time/current scale factor for issuing the respective pulse, so the number of nodes can be adjusted.
These and other features of the systems and methods of the subject disclosure will become more readily apparent to those skilled in the art from the following detailed description of the preferred embodiments taken in conjunction with the drawings.
So that those skilled in the art to which the subject disclosure appertains will readily understand how to make and use the devices and methods of the subject disclosure without undue experimentation, preferred embodiments thereof will be described in detail herein below with reference to certain figures, wherein:
Reference will now be made to the drawings wherein like reference numerals identify similar structural features or aspects of the subject disclosure. For purposes of explanation and illustration, and not limitation, a partial view of an exemplary embodiment of a system in accordance with the disclosure is shown in
System 100 for differential current monitoring includes a control module 102 and a plurality of nodes 104, 106, and 108 operatively connected to the control module 102. Each node 104, 106, and 108 is configured to monitor current from a bus 110 to a respective load 112, 114, and 116. Those skilled in the art will readily appreciate that while shown and described in the exemplary context of having three nodes 104, 106, and 108, the ellipsis in
The control module 102 and nodes 104, 106, and 108 are configured to monitor current at each of the nodes 104, 106, and 108 and issue a pulse for each node 104, 106, and 108 (the control module 102 need only directly monitor the current at input 118 of bus 110 and need have no direct bearing on the measurement of current at the nodes 104, 106, and 108). The pulse from each node has a pulse duration that is proportional to current measured or monitored at the node 104, 106, and 108. Control module 102 can sum all of the pulses, e.g. pulse durations, for the nodes 104, 106, and 108 to determine the total current drawn from the bus 110 at the nodes 104, 106, and 108. The concatenation of the pulses is what performs the sum. The control module can simply measure the resulting pulse duration from end to end and compares to the current 118. In other words the summation can be the inherent result of the daisy chain of the pulses as further explained below.
Control module 102 is connected to the input 118 of bus 110 so control module 102 can compare the total current drawn from the bus 110 at the nodes 104, 106, and 108 to the current input to the bus 110. If the total current drawn from the bus 110 is not within a predetermined range of the current input to the bus 110, control module 102 can signal a fault condition, such as a ground mode fault.
The nodes 104, 106, and 108 are arranged in a daisy chain 120. Issuing a pulse for each node 104, 106, and 108 can include sequentially issuing a pulse from one node to another along the daisy chain 120 to create a pulse train 122 shown in
The control module 102 is directly connected to a first one of the nodes 104 at line 124. Issuing a pulse for each node 104, 106, and 108 can include issuing an initial pulse from control module 102 to the first one of the nodes 104 to initiate transmission of the pulse train 122 along the daisy chain 120. The control module 102 is directly connected to a final one of the nodes 108 at line 126, wherein issuing a pulse for each node 104, 106, and 108 includes transmitting the pulse train 122 back from the final one of the nodes 108 in the daisy chain 120 to the control module 102.
The control module 102 can optionally be directly connected to each of the nodes 104, 106, and 108, e.g., using the dashed extensions of line lines 124 in
The method can include monitoring for a timeout condition in the control module 102 in response to failure to receive the pulse train 122 from the last one of the nodes 108 in the daisy chain 120, and reporting a fault in response to the timeout condition. Each of the nodes 104, 106, and 108 can use a common time/current scale factor for issuing the respective pulse, regardless of the number of nodes. The number of nodes can be adjusted, e.g., if loads are added or removed from bus 110.
As will be appreciated by one skilled in the art, aspects of the present embodiments may be embodied as a system, method or computer program product. Accordingly, aspects of the present embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
Aspects of the present disclosure are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the embodiments. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in a flowchart and/or block diagram block or blocks.
Embodiments described herein provide a hybrid digital/analog system and method for differential monitoring of multiple circuits. The methods and systems of the present disclosure, as described above and shown in the drawings, provide for differential current monitoring with superior properties including better noise immunity and accuracy than conventional analog systems and reduced hardware relative to conventional digital techniques. Potential benefits of embodiments disclosed herein include the ability to obtain digital accuracy without the need for field programmable gate arrays (FPGAs) and digital signal processing arithmetic functions, and making use of simple pulse width modulation (PWM) logic that is built into embedded controllers for generating time/current pulses and using a simple timer/counter or simple subtraction to determine if input and output currents are equal. While the apparatus and methods of the subject disclosure have been shown and described with reference to preferred embodiments, those skilled in the art will readily appreciate that changes and/or modifications may be made thereto without departing from the scope of the subject disclosure.
This application is a continuation of U.S. patent application Ser. No. 15/392,766, filed Dec. 28, 2016, the entire content of which is incorporated herein by reference.
Number | Date | Country | |
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Parent | 15392766 | Dec 2016 | US |
Child | 17379966 | US |